*** Running vivado with args -log top_rod_jfex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_jfex.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_rod_jfex.tcl -notrace Command: link_design -top top_rod_jfex -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0.dcp' for cell 'ILA_axi_chan_4' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.dcp' for cell 'proc_clock_gen' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.dcp' for cell 'top_vio' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo.dcp' for cell 'Bulk_0_64_32/ILA_packet_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32.dcp' for cell 'Bulk_0_64_32/data_width_conv' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0.dcp' for cell 'Bulk_0_64_32/main_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila.dcp' for cell 'ILA_axi_chan_12/ila_crc_check' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_wconv.dcp' for cell 'backplane/ila_dwidth_conv' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/dwidth_convert/dwidth_convert.dcp' for cell 'backplane/width_conver_s12_l1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.dcp' for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_jfex_aurora_low.dcp' for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2.dcp' for cell 'backplane/combined_ttc/ila_rx2_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.dcp' for cell 'backplane/combined_ttc/vio_gt_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.dcp' for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1.dcp' for cell 'backplane/readout_ctrl/ila_tx0_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.dcp' for cell 'backplane/readout_ctrl/vio_gt_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.dcp' for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila.dcp' for cell 'event_builder/bulk_0/bulkl_proc_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo.dcp' for cell 'event_builder/bulk_0/data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila.dcp' for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.dcp' for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.channel_fifo_vio' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila.dcp' for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila.dcp' for cell 'event_builder/readout_controller/readout_ctrl_ila2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_ev_builder.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/event_fifo_ila.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/error_ila.dcp' for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.dcp' for cell 'event_builder/ttc_input/bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.dcp' for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_in' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_out' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.dcp' for cell 'fm_interface_1/clk_blk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.dcp' for cell 'fm_interface_1/chan_0/L1ID_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode.dcp' for cell 'fm_interface_1/chan_0/ila_fm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.dcp' for cell 'fm_interface_1/chan_0/vio_fm_reset' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b.dcp' for cell 'fm_interface_1/chan_0/ram0/RAM_0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.dcp' for cell 'fm_interface_1/chan_0/u7/FIFO34b' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm.dcp' for cell 'fm_interface_1/u0/ila_resetfsm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.dcp' for cell 'ipbus_blk/ip_addr_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/ethernet_mac_rgmii.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Netlist sorting complete. Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3026.465 ; gain = 0.000 ; free physical = 912 ; free virtual = 20208 INFO: [Netlist 29-17] Analyzing 19762 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. proc_clock_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-549] Could not create 'SLEW' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'SLEW' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DRIVE' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'DRIVE' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Chipscope 16-324] Core: Bulk_0_64_32/ILA_packet_fifo UUID: 63e7dc4f-a901-5f5e-8f15-f44cac18b816 INFO: [Chipscope 16-324] Core: Bulk_1_64_32/ILA_packet_fifo UUID: b894b984-cded-5bd0-92d8-292d78f9765a INFO: [Chipscope 16-324] Core: Bulk_2_64_32/ILA_packet_fifo UUID: 020d2b63-4e4e-5e2e-aab4-4c5b2d6046e9 INFO: [Chipscope 16-324] Core: ILA_axi_chan_12/ila_crc_check UUID: 8765054d-316d-54d9-8ace-fd397f40b08b INFO: [Chipscope 16-324] Core: ILA_axi_chan_13/ila_crc_check UUID: f1a796ee-9bd0-579a-9609-a5fe7356f49b INFO: [Chipscope 16-324] Core: ILA_axi_chan_14/ila_crc_check UUID: 47a7d575-d7d3-5ca9-9e59-abc38e9b38c5 INFO: [Chipscope 16-324] Core: ILA_axi_chan_15/ila_crc_check UUID: 06d7fd57-1bd2-58c0-9db0-9b7dd2e30db2 INFO: [Chipscope 16-324] Core: ILA_axi_chan_4 UUID: 243986b7-10ae-5076-b31e-1a5deb5ff3c8 INFO: [Chipscope 16-324] Core: ILA_axi_chan_5 UUID: e6ea15cd-0e46-5889-bdc8-03e3748b4bf9 INFO: [Chipscope 16-324] Core: ILA_axi_chan_6 UUID: 20f4843a-ad73-5961-871c-7eb485b4f283 INFO: [Chipscope 16-324] Core: ILA_axi_chan_7 UUID: 1e2160fa-1e88-5cff-8e4b-c4c62d282b50 INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l1/debug1.jfex_low_ila UUID: 65d4eedf-565a-5bee-bf36-4362dc7788c7 INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l2/debug1.jfex_low_ila UUID: b2b12b08-a8e0-5271-99d0-0e6b7df3f98c INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l3/debug1.jfex_low_ila UUID: 58302d4d-07b7-51d5-9232-3595a0a49523 INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l4/debug1.jfex_low_ila UUID: 891aa488-6d6c-50b0-96af-e020ae7b0be1 INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l1/debug1.jfex_low_ila UUID: 04cd6e7b-99da-55a0-b0e0-b013b12358d5 INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l2/debug1.jfex_low_ila UUID: a96fbe40-17e9-5834-9b96-53e8ed51c472 INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l3/debug1.jfex_low_ila UUID: b2cc214f-f3f7-5971-826c-370224df996d INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l4/debug1.jfex_low_ila UUID: 065f8364-c5d0-5df8-a4e1-cc50acf2f4b0 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l1/debug1.jfex_low_ila UUID: 6d6db0f5-ca52-5ac5-a98f-d2b4e2dbf366 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l2/debug1.jfex_low_ila UUID: 42142ce3-3551-5822-b2cc-efd714d41dd1 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l3/debug1.jfex_low_ila UUID: d30a25d7-ad28-5360-8429-663c00857183 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l4/debug1.jfex_low_ila UUID: f93e8422-449b-5731-9968-7c1265d0ef9a INFO: [Chipscope 16-324] Core: backplane/combined_ttc/ila_rx2_inst UUID: f60b8007-6bf8-5822-bc32-cdf6ef756575 INFO: [Chipscope 16-324] Core: backplane/combined_ttc/vio_gt_inst UUID: a6d99938-502c-5867-8e71-028088cb558d INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv UUID: a9367127-e949-5f06-9c24-f9d2193076cd INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv_s13_l2 UUID: b9386b0a-ea93-5920-aa7f-bd9910bf8036 INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv_s9_l1 UUID: 3f7bd968-bdec-5070-86ca-655cc56e294c INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv_s9_l3 UUID: a3f79918-b294-52f3-bede-916493340664 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/ila_tx0_inst UUID: 5af42e05-e58f-565e-bd4b-e3caf0b9b4a7 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_gt_inst UUID: 0523908b-78fb-555c-8d31-f2c3c610733b INFO: [Chipscope 16-324] Core: event_builder/bulk_0/bulkl_proc_probe UUID: 7d9dc169-40d5-56ff-9a38-42ad7dd0b67d INFO: [Chipscope 16-324] Core: event_builder/bulk_1/bulkl_proc_probe UUID: 48639c55-d7f5-5b3f-bf8a-c3e17dffdced INFO: [Chipscope 16-324] Core: event_builder/bulk_2/bulkl_proc_probe UUID: f79c214c-778a-503c-82e0-558ccd7036de INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila UUID: f2dacd4d-90ac-5961-a53d-619bfee64cdf INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.channel_fifo_vio UUID: 7a22ce6a-0cfe-5884-8274-9a8c29f956b1 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila UUID: 0f381770-7687-5ee1-b02d-be51f8868775 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila UUID: b8809af5-28d1-5d4e-8a13-03533d4b2503 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila UUID: 7fd0677d-e6bf-5b61-aed4-f8dba0489f87 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.channel_fifo_vio UUID: 77106ad3-b237-593f-864b-a17b4b12fbd2 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila UUID: 0fabbc06-76f2-533c-ad08-a5b2c20e5954 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila UUID: f0474686-58b4-5a5f-9b69-2591b61a2403 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila UUID: ec779436-0c2d-5949-85d4-1344ef5d1ab4 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.channel_fifo_vio UUID: 06ee865a-842e-5e21-aa50-0e1b99aae73d INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila UUID: b69c8210-f4cf-5831-8503-72bbbb8c3540 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila UUID: e432efce-dd18-5a40-a618-8ce6e622c8cf INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila UUID: 6828f53b-6d9d-5c6a-b964-f8b861f8200d INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.channel_fifo_vio UUID: 3867c47c-0568-5173-89f4-394ab6b60e8a INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila UUID: f30ca6de-eb22-52d4-9850-cd0004597f0b INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila UUID: 027a0038-1ad0-58c3-94d9-f18ae6cc7b1e INFO: [Chipscope 16-324] Core: event_builder/readout_controller/readout_ctrl_ila2 UUID: 2118af16-197d-5a88-95e6-28dbf9962d95 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/State_machine_ILA UUID: b8ade747-7d7c-5fc7-9f63-b2cb50b3a6e1 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/ila_event_fifo UUID: 2d4141be-dbbe-5502-9616-cd358067f2ea INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila UUID: 03337b11-edd4-554c-9722-ab13aea48bfc INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_bulk_ttc_fifo UUID: 54b31265-4039-519c-ae13-a6b6c7fda705 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_in UUID: 0d145367-edc8-5440-8a43-c5b7fdc60185 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_out UUID: dea619c4-8196-5fc3-a887-501d70a94797 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/ila_fm UUID: 39f68e95-8276-57e5-b2ba-d040b8bf414c INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/vio_fm_reset UUID: b602d903-de6d-5e57-92e3-814b1496a830 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_fm UUID: 312b9249-01c3-5825-bad2-86e782be33e1 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/vio_fm_reset UUID: eec5d607-63dd-55c1-a9db-2118e9215856 INFO: [Chipscope 16-324] Core: fm_interface_1/u0/ila_resetfsm UUID: 82d99aa3-751c-5dfe-85d1-97a24142969c INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/ila_fm UUID: 6d2436f5-9843-5197-8e19-cddbe1593602 INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/vio_fm_reset UUID: 2e7b6e8a-28c2-522f-b319-a31f8d50741a INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/ila_fm UUID: f7690143-a9e0-554d-977a-d2f37b0258d0 INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/vio_fm_reset UUID: f793cc7a-6b74-5a26-9770-d018214fd2d5 INFO: [Chipscope 16-324] Core: fm_interface_2/u0/ila_resetfsm UUID: c10d06e5-8b28-51b9-aae4-8af94262c1bd INFO: [Chipscope 16-324] Core: ipbus_blk/ip_addr_probe UUID: d3bad9ce-591e-57bb-984d-9f6468850a46 INFO: [Chipscope 16-324] Core: pp_out_fifo_6432/ILA_packet_fifo UUID: b136e600-ef26-57f9-8e20-f80fc6236875 INFO: [Chipscope 16-324] Core: top_vio UUID: 7b2ee998-e565-566c-a490-bae90ac485a9 CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1281] Could not find module 'pp_ctrl_vio'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/pp_ctrl_vio/pp_ctrl_vio.xdc will not be read for this module. Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_4/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_4/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_5/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_5/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_7/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_7/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_4/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_4/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_5/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_5/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_7/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_7/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_12/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_12/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_13/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_13/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_14/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_14/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_15/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_15/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_12/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_12/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_13/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_13/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_14/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_14/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_15/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_15/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' WARNING: [Vivado 12-2489] -period contains time 3.118500 which will be rounded to 3.119 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc:72] Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_7series'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_7series/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_7series'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_7series/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1281] Could not find module 'vio_7series'. The XDC file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/vio_7series/vio_7series.xdc will not be read for this module. Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.xdc] for cell 'top_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.xdc] for cell 'top_vio' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] get_clocks: Time (s): cpu = 00:00:54 ; elapsed = 00:00:46 . Memory (MB): peak = 4683.562 ; gain = 1047.348 ; free physical = 1621 ; free virtual = 20917 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249500 which will be rounded to 0.250 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/rod_top.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/rod_top.xdc] Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc] WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_12/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_13/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_14/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_15/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] get_pins: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 5568.891 ; gain = 885.328 ; free physical = 1188 ; free virtual = 20484 Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc] Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc:34] Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/wiz_experiment.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/wiz_experiment.xdc] Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] get_pins: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5691.891 ; gain = 91.000 ; free physical = 1077 ; free virtual = 20374 Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54] Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/reset_gen_cc.rstblk_cc/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ce_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rnw_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rpn_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 5755.895 ; gain = 0.000 ; free physical = 1928 ; free virtual = 21226 INFO: [Project 1-111] Unisim Transformation Summary: A total of 7236 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 6688 instances IOBUF => IOBUF (IBUF, OBUFT): 24 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 44 instances RAM64M => RAM64M (RAMD64E(x4)): 376 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 104 instances 161 Infos, 201 Warnings, 12 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:05:31 ; elapsed = 00:06:13 . Memory (MB): peak = 5755.895 ; gain = 3926.711 ; free physical = 1928 ; free virtual = 21226 source /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design -directive Explore INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xci Sourcing Tcl File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CK_SPI_CK expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 5763.898 ; gain = 8.000 ; free physical = 1785 ; free virtual = 21189 Starting Cache Timing Information Task INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1b41be57d Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 1363 ; free virtual = 20778 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 1374 ; free virtual = 19982 Netlist sorting complete. Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.58 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 1354 ; free virtual = 19962 Phase 1 Generate And Synthesize Debug Cores | Checksum: 1b7f7abb1 Time (s): cpu = 00:03:27 ; elapsed = 00:05:54 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 1343 ; free virtual = 19951 Phase 2 Retarget INFO: [Opt 31-138] Pushed 101 inverter(s) to 240 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1ef90388f Time (s): cpu = 00:04:12 ; elapsed = 00:06:40 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 1315 ; free virtual = 19923 INFO: [Opt 31-389] Phase Retarget created 864 cells and removed 2452 cells INFO: [Opt 31-1021] In phase Retarget, 4535 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 174558d68 Time (s): cpu = 00:04:28 ; elapsed = 00:06:56 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 1047 ; free virtual = 19655 INFO: [Opt 31-389] Phase Constant propagation created 372 cells and removed 2627 cells INFO: [Opt 31-1021] In phase Constant propagation, 3276 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD11557) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. INFO: [Opt 31-120] Instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. Phase 4 Sweep | Checksum: 1d5323489 Time (s): cpu = 00:07:37 ; elapsed = 00:10:05 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 366 ; free virtual = 18974 INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 12190 cells INFO: [Opt 31-1021] In phase Sweep, 37055 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 5 BUFG optimization | Checksum: 1d5323489 Time (s): cpu = 00:07:48 ; elapsed = 00:10:16 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 371 ; free virtual = 18979 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1d5323489 Time (s): cpu = 00:07:56 ; elapsed = 00:10:24 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 369 ; free virtual = 18977 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 1d5323489 Time (s): cpu = 00:07:59 ; elapsed = 00:10:27 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 376 ; free virtual = 18984 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 3564 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 864 | 2452 | 4535 | | Constant propagation | 372 | 2627 | 3276 | | Sweep | 11 | 12190 | 37055 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 3564 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 373 ; free virtual = 18981 Ending Logic Optimization Task | Checksum: 128e516fd Time (s): cpu = 00:08:09 ; elapsed = 00:10:37 . Memory (MB): peak = 5763.898 ; gain = 0.000 ; free physical = 371 ; free virtual = 18979 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.088 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUP_INCLUDE.GEN_7Series_STARTUP.STARTUPE2_inst INFO: [Power 33-23] Power model is not available for DNA_PORT_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 574 BRAM(s) out of a total of 702 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 388 WE to EN ports Number of BRAM Ports augmented: 248 newly gated: 401 Total Ports: 1404 Ending PowerOpt Patch Enables Task | Checksum: 1627ac1b7 Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 2404 ; free virtual = 17262 Ending Power Optimization Task | Checksum: 1627ac1b7 Time (s): cpu = 00:06:30 ; elapsed = 00:06:13 . Memory (MB): peak = 7732.570 ; gain = 1968.672 ; free physical = 2728 ; free virtual = 17594 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 15acc65ef Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 2591 ; free virtual = 17502 Ending Final Cleanup Task | Checksum: 15acc65ef Time (s): cpu = 00:01:11 ; elapsed = 00:01:14 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 2590 ; free virtual = 17501 Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] from IP /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/axi4_subsys_jtag_axi_0_0.xci Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc:69] all_fanout: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 2247 ; free virtual = 17160 Finished Parsing XDC File [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 2255 ; free virtual = 17174 Ending Netlist Obfuscation Task | Checksum: 15acc65ef Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 2240 ; free virtual = 17158 INFO: [Common 17-83] Releasing license: Implementation 215 Infos, 202 Warnings, 12 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:17:12 ; elapsed = 00:19:30 . Memory (MB): peak = 7732.570 ; gain = 1976.672 ; free physical = 2246 ; free virtual = 17177 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 2246 ; free virtual = 17179 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 7732.570 ; gain = 0.000 ; free physical = 1894 ; free virtual = 17087 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:40 ; elapsed = 00:03:49 . Memory (MB): peak = 7732.574 ; gain = 0.004 ; free physical = 2013 ; free virtual = 17101 INFO: [runtcl-4] Executing : report_drc -file top_rod_jfex_drc_opted.rpt -pb top_rod_jfex_drc_opted.pb -rpx top_rod_jfex_drc_opted.rpx Command: report_drc -file top_rod_jfex_drc_opted.rpt -pb top_rod_jfex_drc_opted.pb -rpx top_rod_jfex_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 7732.574 ; gain = 0.000 ; free physical = 2496 ; free virtual = 17591 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CK_SPI_CK expects both input and output buffering but the buffers are incomplete. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Explore' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 7732.574 ; gain = 0.000 ; free physical = 2322 ; free virtual = 17421 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: eb7b6f0b Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.28 . Memory (MB): peak = 7732.574 ; gain = 0.000 ; free physical = 2321 ; free virtual = 17420 Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 7732.574 ; gain = 0.000 ; free physical = 2322 ; free virtual = 17420 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16f773339 Time (s): cpu = 00:05:09 ; elapsed = 00:06:13 . Memory (MB): peak = 7732.574 ; gain = 0.000 ; free physical = 428 ; free virtual = 15650 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 134a3f58d Time (s): cpu = 00:07:47 ; elapsed = 00:08:57 . Memory (MB): peak = 8819.484 ; gain = 1086.910 ; free physical = 793 ; free virtual = 14714 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 134a3f58d Time (s): cpu = 00:07:50 ; elapsed = 00:09:00 . Memory (MB): peak = 8819.484 ; gain = 1086.910 ; free physical = 785 ; free virtual = 14728 Phase 1 Placer Initialization | Checksum: 134a3f58d Time (s): cpu = 00:07:52 ; elapsed = 00:09:02 . Memory (MB): peak = 8819.484 ; gain = 1086.910 ; free physical = 633 ; free virtual = 14598 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1d9757fce Time (s): cpu = 00:08:44 ; elapsed = 00:09:57 . Memory (MB): peak = 8819.484 ; gain = 1086.910 ; free physical = 382 ; free virtual = 14389 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 13500 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 4467 nets or cells. Created 0 new cell, deleted 4467 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-64] No nets found for fanout-optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9009.969 ; gain = 0.000 ; free physical = 436 ; free virtual = 14427 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 4467 | 4467 | 0 | 1 | 00:00:18 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:04 | | Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 4467 | 4467 | 0 | 9 | 00:00:24 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 1bb5a0d1e Time (s): cpu = 00:19:07 ; elapsed = 00:20:48 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 359 ; free virtual = 14351 Phase 2.2 Global Placement Core | Checksum: 1cdd81399 Time (s): cpu = 00:19:31 ; elapsed = 00:21:12 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 325 ; free virtual = 14321 Phase 2 Global Placement | Checksum: 1cdd81399 Time (s): cpu = 00:19:32 ; elapsed = 00:21:12 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 490 ; free virtual = 14486 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 17d9b15ba Time (s): cpu = 00:20:38 ; elapsed = 00:22:21 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 696 ; free virtual = 14841 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: bae8010f Time (s): cpu = 00:22:25 ; elapsed = 00:24:12 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 535 ; free virtual = 14727 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: eca13136 Time (s): cpu = 00:22:34 ; elapsed = 00:24:22 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 535 ; free virtual = 14733 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1180ba5a1 Time (s): cpu = 00:22:43 ; elapsed = 00:24:30 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 529 ; free virtual = 14731 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 7c047484 Time (s): cpu = 00:24:23 ; elapsed = 00:26:15 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 824 ; free virtual = 14827 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: bbaf1881 Time (s): cpu = 00:27:34 ; elapsed = 00:29:28 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 428 ; free virtual = 14432 Phase 3.6 Small Shape Detail Placement | Checksum: bbaf1881 Time (s): cpu = 00:27:40 ; elapsed = 00:29:33 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 495 ; free virtual = 14499 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 11b23eaba Time (s): cpu = 00:28:00 ; elapsed = 00:29:54 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 537 ; free virtual = 14541 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 17ac254db Time (s): cpu = 00:28:15 ; elapsed = 00:30:08 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 512 ; free virtual = 14516 Phase 3 Detail Placement | Checksum: 17ac254db Time (s): cpu = 00:28:18 ; elapsed = 00:30:12 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 517 ; free virtual = 14521 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 206954c00 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net ipbus_blk/ipbus/clocks/rst_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 206954c00 Time (s): cpu = 00:31:48 ; elapsed = 00:33:44 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 464 ; free virtual = 14599 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.247. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 20dd6109c Time (s): cpu = 00:37:21 ; elapsed = 00:39:17 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 754 ; free virtual = 14584 Phase 4.1 Post Commit Optimization | Checksum: 20dd6109c Time (s): cpu = 00:37:25 ; elapsed = 00:39:22 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 743 ; free virtual = 14579 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 20dd6109c Time (s): cpu = 00:37:31 ; elapsed = 00:39:27 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 739 ; free virtual = 14595 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 20dd6109c Time (s): cpu = 00:37:35 ; elapsed = 00:39:31 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 715 ; free virtual = 14582 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9009.969 ; gain = 0.000 ; free physical = 715 ; free virtual = 14582 Phase 4.4 Final Placement Cleanup | Checksum: 1e0d3f421 Time (s): cpu = 00:37:39 ; elapsed = 00:39:35 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 711 ; free virtual = 14578 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e0d3f421 Time (s): cpu = 00:37:42 ; elapsed = 00:39:39 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 709 ; free virtual = 14576 Ending Placer Task | Checksum: 122bf29fd Time (s): cpu = 00:37:42 ; elapsed = 00:39:39 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 701 ; free virtual = 14571 INFO: [Common 17-83] Releasing license: Implementation 281 Infos, 203 Warnings, 12 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:38:25 ; elapsed = 00:40:23 . Memory (MB): peak = 9009.969 ; gain = 1277.395 ; free physical = 1065 ; free virtual = 14952 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9009.969 ; gain = 0.000 ; free physical = 1059 ; free virtual = 14953 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 9009.969 ; gain = 0.000 ; free physical = 245 ; free virtual = 14397 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:52 ; elapsed = 00:03:58 . Memory (MB): peak = 9009.973 ; gain = 0.004 ; free physical = 572 ; free virtual = 14251 INFO: [runtcl-4] Executing : report_io -file top_rod_jfex_io_placed.rpt report_io: Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:01 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 397 ; free virtual = 14197 INFO: [runtcl-4] Executing : report_utilization -file top_rod_jfex_utilization_placed.rpt -pb top_rod_jfex_utilization_placed.pb report_utilization: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 405 ; free virtual = 14209 INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_rod_jfex_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 371 ; free virtual = 14180 INFO: [runtcl-4] Executing : report_utilization -file top_rod_jfex_utilization_placed_1.rpt -pb top_rod_jfex_utilization_placed_1.pb report_utilization: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 336 ; free virtual = 14146 Command: phys_opt_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 832 ; free virtual = 14171 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.247 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 15ec59432 Time (s): cpu = 00:03:06 ; elapsed = 00:03:07 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 439 ; free virtual = 13844 Phase 2 SLR Crossing Optimization INFO: [Physopt 32-670] No setup violation found. SLR Crossing Optimization was not performed. Phase 2 SLR Crossing Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.247 | TNS=0.000 | Phase 3 Fanout Optimization INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed. Phase 3 Fanout Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 4 Single Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Single Cell Placement Optimization was not performed. Phase 4 Single Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 5 Multi Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Multi Cell Placement Optimization was not performed. Phase 5 Multi Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 6 Rewire INFO: [Physopt 32-670] No setup violation found. Rewire was not performed. Phase 6 Rewire | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 7 Critical Cell Optimization INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed. Phase 7 Critical Cell Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 8 Fanout Optimization INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed. Phase 8 Fanout Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 9 Single Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Single Cell Placement Optimization was not performed. Phase 9 Single Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 10 Multi Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Multi Cell Placement Optimization was not performed. Phase 10 Multi Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 11 Rewire INFO: [Physopt 32-670] No setup violation found. Rewire was not performed. Phase 11 Rewire | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 12 Critical Cell Optimization INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed. Phase 12 Critical Cell Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 13 SLR Crossing Optimization INFO: [Physopt 32-670] No setup violation found. SLR Crossing Optimization was not performed. Phase 13 SLR Crossing Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 14 Fanout Optimization INFO: [Physopt 32-670] No setup violation found. Fanout Optimization was not performed. Phase 14 Fanout Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 15 Single Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Single Cell Placement Optimization was not performed. Phase 15 Single Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 16 Multi Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Multi Cell Placement Optimization was not performed. Phase 16 Multi Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 17 Rewire INFO: [Physopt 32-670] No setup violation found. Rewire was not performed. Phase 17 Rewire | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:10 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 18 Critical Cell Optimization INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed. Phase 18 Critical Cell Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 19 DSP Register Optimization INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. Phase 19 DSP Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 20 BRAM Register Optimization INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. Phase 20 BRAM Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 21 URAM Register Optimization INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. Phase 21 URAM Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 22 Shift Register Optimization INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. Phase 22 Shift Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:09 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 23 DSP Register Optimization INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. Phase 23 DSP Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:10 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 24 BRAM Register Optimization INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. Phase 24 BRAM Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:10 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 25 URAM Register Optimization INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. Phase 25 URAM Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:10 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 26 Shift Register Optimization INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. Phase 26 Shift Register Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:10 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 27 Critical Pin Optimization INFO: [Physopt 32-670] No setup violation found. Critical Pin Optimization was not performed. Phase 27 Critical Pin Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:10 ; elapsed = 00:03:11 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13820 Phase 28 Very High Fanout Optimization INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 801 to 162 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 865 to 178 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 28 Very High Fanout Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:17 ; elapsed = 00:03:18 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 263 ; free virtual = 13819 Phase 29 Single Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Single Cell Placement Optimization was not performed. Phase 29 Single Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:17 ; elapsed = 00:03:18 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 263 ; free virtual = 13818 Phase 30 Multi Cell Placement Optimization INFO: [Physopt 32-670] No setup violation found. Multi Cell Placement Optimization was not performed. Phase 30 Multi Cell Placement Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:17 ; elapsed = 00:03:19 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 263 ; free virtual = 13818 Phase 31 SLR Crossing Optimization INFO: [Physopt 32-670] No setup violation found. SLR Crossing Optimization was not performed. Phase 31 SLR Crossing Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:17 ; elapsed = 00:03:19 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 262 ; free virtual = 13818 Phase 32 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.247 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.247 | TNS=0.000 | Phase 32 Critical Path Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:22 ; elapsed = 00:03:23 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 248 ; free virtual = 13804 Phase 33 BRAM Enable Optimization Phase 33 BRAM Enable Optimization | Checksum: 15ec59432 Time (s): cpu = 00:03:22 ; elapsed = 00:03:23 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 248 ; free virtual = 13804 INFO: [Physopt 32-960] Skip hold-fix as initial WHS does not violate hold threshold 250 ps Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 259 ; free virtual = 13815 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=0.247 | TNS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Single Cell Placement | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Multi Cell Placement | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Critical Cell | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | SLR Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Critical Pin | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Very High Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:08 | | BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:04 | | Total | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:12 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 258 ; free virtual = 13814 Ending Physical Synthesis Task | Checksum: 15ec59432 Time (s): cpu = 00:03:24 ; elapsed = 00:03:25 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 258 ; free virtual = 13814 INFO: [Common 17-83] Releasing license: Implementation 343 Infos, 203 Warnings, 12 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:06:22 ; elapsed = 00:06:25 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 466 ; free virtual = 14026 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 459 ; free virtual = 14021 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 236 ; free virtual = 14084 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:57 ; elapsed = 00:04:07 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 736 ; free virtual = 14098 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: ae010775 ConstDB: 0 ShapeSum: 74ea1006 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1ec51c660 Time (s): cpu = 00:03:03 ; elapsed = 00:03:04 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 264 ; free virtual = 13595 Post Restoration Checksum: NetGraph: fb83c147 NumContArr: f0ce0519 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 1ec51c660 Time (s): cpu = 00:03:08 ; elapsed = 00:03:09 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 334 ; free virtual = 13691 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 1ec51c660 Time (s): cpu = 00:03:11 ; elapsed = 00:03:12 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 300 ; free virtual = 13665 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 1ec51c660 Time (s): cpu = 00:03:12 ; elapsed = 00:03:13 . Memory (MB): peak = 9009.973 ; gain = 0.000 ; free physical = 295 ; free virtual = 13659 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1503fc602 Time (s): cpu = 00:10:02 ; elapsed = 00:10:27 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 1437 ; free virtual = 13332 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.145 | TNS=0.000 | WHS=-1.074 | THS=-35237.481| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1a5ab9103 Time (s): cpu = 00:11:57 ; elapsed = 00:12:23 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 1353 ; free virtual = 13257 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.145 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1863f8ecd Time (s): cpu = 00:12:01 ; elapsed = 00:12:27 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 1323 ; free virtual = 13236 Phase 2 Router Initialization | Checksum: 21e21d0ee Time (s): cpu = 00:12:02 ; elapsed = 00:12:28 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 1320 ; free virtual = 13234 Router Utilization Summary Global Vertical Routing Utilization = 0.458996 % Global Horizontal Routing Utilization = 0.551716 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 345519 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 345519 Number of Partially Routed Nets = 0 Number of Node Overlaps = 43 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 1a87aad83 Time (s): cpu = 00:14:45 ; elapsed = 00:15:13 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 1283 ; free virtual = 13200 INFO: [Route 35-580] Design has 1 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | CLK_125_pin | CLK_125_pin | event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/reset_timer/rx_pwr_reset_reg/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 28001 Number of Nodes with overlaps = 3634 Number of Nodes with overlaps = 1740 Number of Nodes with overlaps = 555 Number of Nodes with overlaps = 82 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.132 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 167902859 Time (s): cpu = 00:41:07 ; elapsed = 00:41:58 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 523 ; free virtual = 12573 Phase 4 Rip-up And Reroute | Checksum: 167902859 Time (s): cpu = 00:41:08 ; elapsed = 00:41:59 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 523 ; free virtual = 12573 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1493d2abb Time (s): cpu = 00:41:55 ; elapsed = 00:42:47 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 357 ; free virtual = 12407 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.218 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 137bead99 Time (s): cpu = 00:41:57 ; elapsed = 00:42:49 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 289 ; free virtual = 12339 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 137bead99 Time (s): cpu = 00:41:59 ; elapsed = 00:42:50 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 243 ; free virtual = 12294 Phase 5 Delay and Skew Optimization | Checksum: 137bead99 Time (s): cpu = 00:42:00 ; elapsed = 00:42:51 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 202 ; free virtual = 12253 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1228cf78b Time (s): cpu = 00:42:54 ; elapsed = 00:43:46 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 260 ; free virtual = 12264 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.218 | TNS=0.000 | WHS=-0.644 | THS=-1956.872| Phase 6.1.2 Lut RouteThru Assignment for hold Phase 6.1.2 Lut RouteThru Assignment for hold | Checksum: 102d905fc Time (s): cpu = 00:44:15 ; elapsed = 00:45:07 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 304 ; free virtual = 12308 Phase 6.1 Hold Fix Iter | Checksum: 102d905fc Time (s): cpu = 00:44:16 ; elapsed = 00:45:09 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 366 ; free virtual = 12370 Phase 6 Post Hold Fix | Checksum: 1b94c957f Time (s): cpu = 00:44:20 ; elapsed = 00:45:12 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 386 ; free virtual = 12391 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 144d23c59 Time (s): cpu = 00:45:40 ; elapsed = 00:46:32 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 360 ; free virtual = 12368 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.218 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 144d23c59 Time (s): cpu = 00:45:41 ; elapsed = 00:46:34 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 360 ; free virtual = 12368 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 20.9644 % Global Horizontal Routing Utilization = 20.2181 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 144d23c59 Time (s): cpu = 00:45:45 ; elapsed = 00:46:37 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 316 ; free virtual = 12324 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 144d23c59 Time (s): cpu = 00:45:46 ; elapsed = 00:46:39 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 350 ; free virtual = 12358 Phase 10 Depositing Routes INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y11/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y10/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y8/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y0/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y15/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y14/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y30/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y31/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y36/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y37/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y35/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y34/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y33/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y32/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y12/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y13/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y36/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y37/GTNORTHREFCLK1 Phase 10 Depositing Routes | Checksum: 10066a2ac Time (s): cpu = 00:46:22 ; elapsed = 00:47:15 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 349 ; free virtual = 12358 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.217 | TNS=0.000 | WHS=0.050 | THS=0.000 | INFO: [Route 35-61] The design met the timing requirement. Phase 11 Post Router Timing | Checksum: 189496e8d Time (s): cpu = 00:49:28 ; elapsed = 00:50:22 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 160 ; free virtual = 12021 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:49:29 ; elapsed = 00:50:23 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 865 ; free virtual = 12750 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 387 Infos, 203 Warnings, 12 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:51:03 ; elapsed = 00:52:00 . Memory (MB): peak = 10815.078 ; gain = 1805.105 ; free physical = 819 ; free virtual = 12741 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for rod_jfex... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Top/rod_jfex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 26E0527, will use most recent tag v0.5.8. As this is an official tag, patch will be incremented to 9. INFO: [Hog:Msg-0] Git describe set to: v0.5.8-4-g26e0527 INFO: [Hog:Msg-0] Evaluating last git SHA in which rod_jfex was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Top/rod_jfex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 26E0527, will use most recent tag v0.5.8. As this is an official tag, patch will be incremented to 9. INFO: [Hog:Msg-0] The git SHA value 26e0527 will be set as bitstream USERID. INFO: [Hog:Msg-0] Evaluating Git sha for rod_jfex... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/Top/rod_jfex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 26E0527, will use most recent tag v0.5.8. As this is an official tag, patch will be incremented to 9. INFO: [Hog:Msg-0] Git describe set to: v0.5.8-4-g26e0527 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/bin/rod_jfex-v0.5.8-4-g26e0527... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.