## Repository info
- Merge request number: 122
- Branch name: major_version/111-p2

## MR Description
rewrite of fifo layer block input_fifos_p2 to use a vhdl for-generate to make signal connections more simple


## Changelog

- Dual TOB Processor has been added to _p2 versions

## rod_efex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.130142       |
| TNS:          | 0.000000       |
| WHS:          | 0.040515       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    37062    |    0         |   0              |    346400        |    10.70     |   
| Slice  Registers |    51601    |    81        |   0              |    692800        |    7.45      |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    86326    |   0         |   0              |    346400        |    24.92     |    
| Slice  Registers |    135062   |   0         |   0              |    692800        |    19.50     |    
| Block  RAM       Tile |        393 |         0   |              0    |             1180 |         33.31
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 5c4fb36        | 1.0.0       |
| Constraints       | 5c4fb36d       | 1.0.0       |
| IPbus XML         | 4cd3b7b        | 1.0.0       |
| Top Directory     | 989ee7c        | 0.5.24      |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_efex | 124a225        | 1.0.0       |
| **Lib:** others   | 7f1c6f3        | 1.0.0       |



</details>
</p>

 
## rod_jfex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.124625       |
| TNS:          | 0.000000       |
| WHS:          | 0.044541       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    52185    |    0         |   0              |    346400        |    15.06     |   
| Slice  Registers |    76706    |    81        |   0              |    692800        |    11.07     |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex Implementation Utilization report


                                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         --- |              ---  |             ---  |              
| Slice  LUTs      |    128887   |     0         |   0              |    346400        |    37.21     |    
| Slice  Registers |    212869   |     0         |   0              |    692800        |    30.73     |    
| Block  RAM       Tile |        662.5 |         0   |              0    |             1180 |         56.14
| DSPs   |         0    |        0     |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |     111       |   0              |    600           |    18.50     |    
                                                                                                           
## rod_jfex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 5c4fb36        | 1.0.0       |
| Constraints       | 5c4fb36d       | 1.0.0       |
| IPbus XML         | 4cd3b7b        | 1.0.0       |
| Top Directory     | 1f87e68        | 0.5.15      |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_jfex | 124a225        | 1.0.0       |
| **Lib:** others   | 7f1c6f3        | 1.0.0       |



</details>
</p>

 
## rod_efex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.155809       |
| TNS:          | 0.000000       |
| WHS:          | 0.048010       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    44506    |    0         |   0              |    346400        |    12.85     |   
| Slice  Registers |    59713    |    81        |   0              |    692800        |    8.62      |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex_p2 Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    102920   |   0         |   0              |    346400        |    29.71     |    
| Slice  Registers |    159091   |   0         |   0              |    692800        |    22.96     |    
| Block  RAM       Tile |        536 |         0   |              0    |             1180 |         45.42
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | e15c892        | 1.0.0       |
| Constraints          | 5c4fb36d       | 1.0.0       |
| IPbus XML            | e15c892        | 1.0.0       |
| Top Directory        | 36d5328        | 1.0.0       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_efex_p2 | 7571353        | 1.0.0       |
| **Lib:** others      | 7f1c6f3        | 1.0.0       |



</details>
</p>

 
## rod_jfex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.061541       |
| TNS:          | 0.000000       |
| WHS:          | 0.048388       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    60267    |    0         |   0              |    346400        |    17.40     |   
| Slice  Registers |    86270    |    81        |   0              |    692800        |    12.45     |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex_p2 Implementation Utilization report


                                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         --- |              ---  |             ---  |              
| Slice  LUTs      |    124425   |     0         |   0              |    346400        |    35.92     |    
| Slice  Registers |    205785   |     0         |   0              |    692800        |    29.70     |    
| Block  RAM       Tile |        863.5 |         0   |              0    |             1180 |         73.18
| DSPs   |         0    |        0     |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |     111       |   0              |    600           |    18.50     |    
                                                                                                           
## rod_jfex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | e15c892        | 1.0.0       |
| Constraints          | 5c4fb36d       | 1.0.0       |
| IPbus XML            | e15c892        | 1.0.0       |
| Top Directory        | b53c0f3        | 1.0.0       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_jfex_p2 | 7571353        | 1.0.0       |
| **Lib:** others      | 7f1c6f3        | 1.0.0       |



</details>
</p>