Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022 | Date : Thu Jan 4 19:54:07 2024 | Host : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core) | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/bin/rod_jfex-v1.0.0-5C4FB36/reports/hierarchical_utilization.txt | Design : top_rod_jfex | Device : xc7vx550tffg1927-2 | Speed File : -2 | Design State : Routed ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +---------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+----------------+----------------+-------------+--------------+----------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +---------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+----------------+----------------+-------------+--------------+----------------+-------------+-----------+------------+ | top_rod_jfex | (top) | 128887(37.21%) | 116644(33.67%) | 1825(1.05%) | 10418(5.98%) | 212869(30.73%) | 647(54.83%) | 31(1.31%) | 0(0.00%) | | (top_rod_jfex) | (top) | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_0_64_32 | packet_fifo__xdcDup__1 | 1596(0.46%) | 1323(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (Bulk_0_64_32) | packet_fifo__xdcDup__1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo_HD438 | 1399(0.40%) | 1126(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo_HD438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila_HD439 | 1399(0.40%) | 1126(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila_HD439 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core_HD440 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core_HD440 | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory_HD441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5_HD442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth_HD443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD456 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD456 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD457 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7_HD458 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1_HD459 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD460 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD460 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1_HD461 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD462 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD462 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1_HD463 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1_HD464 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6_HD465 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1_HD466 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD467 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD468 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD468 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72_HD469 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73_HD470 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD471 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD471 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4_HD472 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5_HD473 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2_HD474 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay_HD475 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD476 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD477 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD477 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD478 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD479 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2_HD480 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD481 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD482 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD482 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68_HD483 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69_HD484 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register_HD485 | 910(0.26%) | 909(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register_HD485 | 326(0.09%) | 325(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s_HD486 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD487 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD488 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD489 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD490 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD491 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD492 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD493 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD494 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD495 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD496 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD497 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD498 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD499 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs_HD500 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50_HD501 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62_HD502 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51_HD503 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61_HD504 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52_HD505 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60_HD506 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53_HD507 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59_HD508 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54_HD509 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58_HD510 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55_HD511 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57_HD512 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35_HD513 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65_HD514 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36_HD515 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD516 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37_HD517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64_HD518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56_HD519 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56_HD520 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57_HD521 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55_HD522 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58_HD523 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD524 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59_HD525 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54_HD526 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60_HD527 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53_HD528 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61_HD529 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52_HD530 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63_HD531 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51_HD532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65_HD533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50_HD534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49_HD536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38_HD537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63_HD538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD539 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream_HD540 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_HD541 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD542 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD542 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_HD543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD544 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD544 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection_HD545 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD548 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer_HD549 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD550 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger_HD551 | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger_HD551 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match_HD552 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match_HD552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_HD553 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_HD553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA_HD554 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA_HD554 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD555 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD556 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match_HD557 | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match_HD557 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD558 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD559 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD560 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD560 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39_HD561 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40_HD562 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41_HD563 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42_HD564 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43_HD565 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44_HD566 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45_HD567 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD568 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD569 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD570 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD571 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD571 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD572 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD573 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD574 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD575 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD575 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD576 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD577 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD578 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD579 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD579 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD580 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD581 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD582 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD583 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD583 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD584 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD585 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD586 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD587 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD587 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD588 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD589 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD590 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD591 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD591 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32_HD592 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD593 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD594 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD595 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD595 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29_HD596 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD597 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD598 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD599 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD599 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23_HD600 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24_HD601 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25_HD602 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD603 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD604 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD605 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD606 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD606 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17_HD607 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18_HD608 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19_HD609 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD610 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD611 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD612 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD613 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD613 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD614 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD615 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD616 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD617 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD617 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_HD618 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9_HD619 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10_HD620 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD621 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD622 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD623 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD624 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD624 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD625 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd_HD626 | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32_HD1008 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD1009 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD1009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer_HD1010 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0_HD1020 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0_HD1020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top_HD1021 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis_HD1022 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis_HD1022 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3_HD1023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base_HD1024 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base_HD1024 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1_HD1025 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray_HD1026 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_HD1027 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_HD1028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0_HD1029 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1_HD1030 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0_HD1031 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2_HD1032 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn_HD1033 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base_HD1034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_HD1035 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_HD1036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit_HD1037 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2_HD1038 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3_HD1039 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2_HD1040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst_HD1041 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst_HD1041 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst_HD1042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4_HD1043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_1_64_32 | packet_fifo__xdcDup__2 | 1595(0.46%) | 1322(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (Bulk_1_64_32) | packet_fifo__xdcDup__2 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo_HD627 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo_HD627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila_HD628 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila_HD628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core_HD629 | 1397(0.40%) | 1124(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core_HD629 | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory_HD630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5_HD631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth_HD632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD645 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD645 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD646 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7_HD647 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1_HD648 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD649 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD649 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1_HD650 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD651 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD651 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1_HD652 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1_HD653 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6_HD654 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1_HD655 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD656 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD657 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD657 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72_HD658 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73_HD659 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD660 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD660 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4_HD661 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5_HD662 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2_HD663 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay_HD664 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD665 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD666 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD666 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD667 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD668 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2_HD669 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD670 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD671 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD671 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68_HD672 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69_HD673 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register_HD674 | 909(0.26%) | 908(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register_HD674 | 325(0.09%) | 324(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s_HD675 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD676 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD677 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD678 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD679 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD680 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD681 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD682 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD683 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD684 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD685 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD686 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD687 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD688 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs_HD689 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50_HD690 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62_HD691 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51_HD692 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61_HD693 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52_HD694 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60_HD695 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53_HD696 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59_HD697 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54_HD698 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58_HD699 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55_HD700 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57_HD701 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35_HD702 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65_HD703 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36_HD704 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD705 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37_HD706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64_HD707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56_HD708 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56_HD709 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57_HD710 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55_HD711 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58_HD712 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD713 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59_HD714 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54_HD715 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60_HD716 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53_HD717 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61_HD718 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52_HD719 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63_HD720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51_HD721 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65_HD722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50_HD723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49_HD725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38_HD726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63_HD727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD728 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream_HD729 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_HD730 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD731 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD731 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_HD732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD733 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD733 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection_HD734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD737 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer_HD738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger_HD740 | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger_HD740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match_HD741 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match_HD741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_HD742 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_HD742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA_HD743 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA_HD743 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD744 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD745 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match_HD746 | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match_HD746 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD747 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD748 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD749 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD749 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39_HD750 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40_HD751 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41_HD752 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42_HD753 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43_HD754 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44_HD755 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45_HD756 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD757 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD758 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD759 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD760 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD760 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD761 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD762 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD763 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD764 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD764 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD765 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD766 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD767 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD768 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD768 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD769 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD770 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD771 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD772 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD772 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD773 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD774 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD775 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD776 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD776 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD777 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD778 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD779 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD780 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD780 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32_HD781 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD782 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD783 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD784 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD784 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29_HD785 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD786 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD787 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD788 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD788 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23_HD789 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24_HD790 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25_HD791 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD792 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD793 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD794 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD795 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD795 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17_HD796 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18_HD797 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19_HD798 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD799 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD800 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD801 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD802 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD802 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD803 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD804 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD805 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD806 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD806 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_HD807 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9_HD808 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10_HD809 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD810 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD811 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD812 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD813 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD813 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD814 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd_HD815 | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32_HD1011 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD1012 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD1012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer_HD1013 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0_HD1044 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0_HD1044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top_HD1045 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis_HD1046 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis_HD1046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3_HD1047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base_HD1048 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base_HD1048 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1_HD1049 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray_HD1050 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_HD1051 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_HD1052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0_HD1053 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1_HD1054 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0_HD1055 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2_HD1056 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn_HD1057 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base_HD1058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_HD1059 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_HD1060 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit_HD1061 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2_HD1062 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3_HD1063 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2_HD1064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst_HD1065 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst_HD1065 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst_HD1066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4_HD1067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_2_64_32 | packet_fifo__xdcDup__3 | 1596(0.46%) | 1323(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (Bulk_2_64_32) | packet_fifo__xdcDup__3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo_HD816 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo_HD816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila_HD817 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila_HD817 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core_HD818 | 1397(0.40%) | 1124(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core_HD818 | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory_HD819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5_HD820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth_HD821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD834 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD834 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD835 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7_HD836 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1_HD837 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD838 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD838 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1_HD839 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD840 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD840 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1_HD841 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1_HD842 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6_HD843 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1_HD844 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD845 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD846 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD846 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72_HD847 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73_HD848 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD849 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD849 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4_HD850 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5_HD851 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2_HD852 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay_HD853 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD854 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD855 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD855 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD856 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD857 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2_HD858 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD859 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD860 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD860 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68_HD861 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69_HD862 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register_HD863 | 909(0.26%) | 908(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register_HD863 | 325(0.09%) | 324(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s_HD864 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD865 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD866 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD867 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD868 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD869 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD870 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD871 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD872 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD873 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD874 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD875 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD876 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD877 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs_HD878 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50_HD879 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62_HD880 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51_HD881 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61_HD882 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52_HD883 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60_HD884 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53_HD885 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59_HD886 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54_HD887 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58_HD888 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55_HD889 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57_HD890 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35_HD891 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65_HD892 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36_HD893 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD894 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37_HD895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64_HD896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56_HD897 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56_HD898 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57_HD899 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55_HD900 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58_HD901 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD902 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59_HD903 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54_HD904 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60_HD905 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53_HD906 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61_HD907 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52_HD908 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63_HD909 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51_HD910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65_HD911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50_HD912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49_HD914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38_HD915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63_HD916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD917 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream_HD918 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_HD919 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD920 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD920 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_HD921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD922 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD922 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection_HD923 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD925 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD926 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer_HD927 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD928 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger_HD929 | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger_HD929 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match_HD930 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match_HD930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_HD931 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_HD931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA_HD932 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA_HD932 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD933 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD934 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match_HD935 | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match_HD935 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD936 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD937 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD938 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD938 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39_HD939 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40_HD940 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41_HD941 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42_HD942 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43_HD943 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44_HD944 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45_HD945 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD946 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD947 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD948 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD949 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD949 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD950 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD951 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD952 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD953 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD953 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD954 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD955 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD956 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD957 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD957 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD958 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD959 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD960 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD961 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD961 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD962 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD963 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD964 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD965 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD965 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD966 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD967 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD968 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD969 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD969 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32_HD970 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD971 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD972 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD973 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD973 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29_HD974 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD975 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD976 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD977 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD977 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23_HD978 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24_HD979 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25_HD980 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD981 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD982 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD983 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD984 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD984 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17_HD985 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18_HD986 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19_HD987 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD988 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD989 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD990 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD991 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD991 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD992 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD993 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD994 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD995 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD995 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_HD996 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9_HD997 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10_HD998 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD999 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD1000 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD1000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1001 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1002 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1002 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1003 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd_HD1004 | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32_HD1014 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD1015 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD1015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer_HD1016 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0_HD1068 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0_HD1068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top_HD1069 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis_HD1070 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis_HD1070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3_HD1071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base_HD1072 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base_HD1072 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1_HD1073 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray_HD1074 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_HD1075 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_HD1076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0_HD1077 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1_HD1078 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0_HD1079 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2_HD1080 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn_HD1081 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base_HD1082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_HD1083 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_HD1084 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit_HD1085 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2_HD1086 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3_HD1087 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2_HD1088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst_HD1089 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst_HD1089 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst_HD1090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4_HD1091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_0 | fex_rx_checker__xdcDup__1 | 1463(0.42%) | 1283(0.37%) | 0(0.00%) | 180(0.10%) | 1964(0.28%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ILA_axi_chan_0) | fex_rx_checker__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | backplane_crc__5 | 309(0.09%) | 309(0.09%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | backplane_crc__5 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_2014 | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_2015 | 214(0.06%) | 214(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_crc_check | chan_crc_ila_HD1096 | 1154(0.33%) | 974(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_crc_check) | chan_crc_ila_HD1096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | chan_crc_ila_ila_v6_2_12_ila_HD1097 | 1154(0.33%) | 974(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | chan_crc_ila_ila_v6_2_12_ila_HD1097 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | chan_crc_ila_ila_v6_2_12_ila_core_HD1098 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1783(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | chan_crc_ila_ila_v6_2_12_ila_core_HD1098 | 38(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.02%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | chan_crc_ila_ila_v6_2_12_ila_trace_memory_HD1099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | chan_crc_ila_blk_mem_gen_v8_4_5_HD1100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_synth_HD1101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD1108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD1109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1110 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1110 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | chan_crc_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD1111 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | chan_crc_ila_ltlib_v1_0_0_cfglut7_HD1112 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | chan_crc_ila_ltlib_v1_0_0_cfglut7__1_HD1113 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1114 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1114 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | chan_crc_ila_ltlib_v1_0_0_cfglut6__1_HD1115 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1116 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1116 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | chan_crc_ila_ltlib_v1_0_0_cfglut4__1_HD1117 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__1_HD1118 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | chan_crc_ila_ltlib_v1_0_0_cfglut6_HD1119 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__1_HD1120 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1121 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1122 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1122 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_59_HD1123 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_60_HD1124 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1125 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1125 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | chan_crc_ila_ltlib_v1_0_0_cfglut4_HD1126 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5_HD1127 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__2_HD1128 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay_HD1129 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1130 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1131 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1131 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1132 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1133 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__2_HD1134 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1135 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1136 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1136 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_55_HD1137 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_56_HD1138 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | chan_crc_ila_ila_v6_2_12_ila_register_HD1139 | 843(0.24%) | 842(0.24%) | 0(0.00%) | 1(0.01%) | 1223(0.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | chan_crc_ila_ila_v6_2_12_ila_register_HD1139 | 321(0.09%) | 320(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s_HD1140 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1141 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1142 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1143 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1144 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1145 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1146 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1147 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1148 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1149 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1150 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1151 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | chan_crc_ila_xsdbs_v1_0_2_xsdbs_HD1152 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized46_HD1153 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_49_HD1154 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized47_HD1155 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_48_HD1156 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized48_HD1157 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_47_HD1158 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized49_HD1159 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_46_HD1160 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized50_HD1161 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_45_HD1162 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized51_HD1163 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_44_HD1164 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized31_HD1165 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_52_HD1166 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized32_HD1167 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1168 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized33_HD1169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_51_HD1170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized52_HD1171 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_43_HD1172 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized53_HD1173 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_42_HD1174 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized54_HD1175 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1176 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized55_HD1177 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_41_HD1178 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized56_HD1179 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_40_HD1180 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized57_HD1181 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_39_HD1182 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized59_HD1183 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_38_HD1184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized61_HD1185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_37_HD1186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_36_HD1188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized34_HD1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_50_HD1190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1191 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | chan_crc_ila_xsdbs_v1_0_2_reg_stream_HD1192 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_HD1193 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1194 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1194 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_HD1195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1196 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1196 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection_HD1197 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__2_HD1198 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__3_HD1199 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__1_HD1200 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer_HD1201 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection__1_HD1202 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1203 | 130(0.04%) | 38(0.01%) | 0(0.00%) | 92(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1203 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | chan_crc_ila_ltlib_v1_0_0_match_HD1204 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | chan_crc_ila_ltlib_v1_0_0_match_HD1204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1205 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1206 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1206 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_34_HD1207 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD1208 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1209 | 120(0.03%) | 37(0.01%) | 0(0.00%) | 83(0.05%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1209 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1210 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1211 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1212 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1212 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_HD1213 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_27_HD1214 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_28_HD1215 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_29_HD1216 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_30_HD1217 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_31_HD1218 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_32_HD1219 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1220 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1221 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1222 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1223 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1223 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1224 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1225 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1226 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1227 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1227 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD1228 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1229 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1230 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1231 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1231 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23_HD1232 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1233 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1234 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1235 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1235 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD1236 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1237 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1238 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1239 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1239 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD1240 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1241 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1242 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1243 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1243 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD1244 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1245 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1246 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1247 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1247 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD1248 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1249 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1250 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1251 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1251 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1252 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1253 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1254 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1255 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1255 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD1256 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1257 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1258 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1259 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1259 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD1260 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | chan_crc_ila_ltlib_v1_0_0_generic_memrd_HD1261 | 55(0.02%) | 53(0.02%) | 0(0.00%) | 2(0.01%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_12 | fex_rx_checker__xdcDup__2 | 1455(0.42%) | 1275(0.37%) | 0(0.00%) | 180(0.10%) | 1964(0.28%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ILA_axi_chan_12) | fex_rx_checker__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | backplane_crc__6 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | backplane_crc__6 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_2012 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_2013 | 211(0.06%) | 211(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_crc_check | chan_crc_ila_HD1262 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_crc_check) | chan_crc_ila_HD1262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | chan_crc_ila_ila_v6_2_12_ila_HD1263 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | chan_crc_ila_ila_v6_2_12_ila_HD1263 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | chan_crc_ila_ila_v6_2_12_ila_core_HD1264 | 1152(0.33%) | 972(0.28%) | 0(0.00%) | 180(0.10%) | 1783(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | chan_crc_ila_ila_v6_2_12_ila_core_HD1264 | 38(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.02%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | chan_crc_ila_ila_v6_2_12_ila_trace_memory_HD1265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | chan_crc_ila_blk_mem_gen_v8_4_5_HD1266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_synth_HD1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD1274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD1275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1276 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1276 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | chan_crc_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD1277 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | chan_crc_ila_ltlib_v1_0_0_cfglut7_HD1278 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | chan_crc_ila_ltlib_v1_0_0_cfglut7__1_HD1279 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1280 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1280 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | chan_crc_ila_ltlib_v1_0_0_cfglut6__1_HD1281 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1282 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1282 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | chan_crc_ila_ltlib_v1_0_0_cfglut4__1_HD1283 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__1_HD1284 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | chan_crc_ila_ltlib_v1_0_0_cfglut6_HD1285 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__1_HD1286 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1287 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1288 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1288 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_59_HD1289 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_60_HD1290 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1291 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1291 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | chan_crc_ila_ltlib_v1_0_0_cfglut4_HD1292 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5_HD1293 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__2_HD1294 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay_HD1295 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1296 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1297 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1297 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1298 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1299 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__2_HD1300 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1301 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1302 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1302 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_55_HD1303 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_56_HD1304 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | chan_crc_ila_ila_v6_2_12_ila_register_HD1305 | 842(0.24%) | 841(0.24%) | 0(0.00%) | 1(0.01%) | 1223(0.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | chan_crc_ila_ila_v6_2_12_ila_register_HD1305 | 320(0.09%) | 319(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s_HD1306 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1307 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1308 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1309 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1310 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1311 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1312 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1313 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1314 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1315 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1316 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1317 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | chan_crc_ila_xsdbs_v1_0_2_xsdbs_HD1318 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized46_HD1319 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_49_HD1320 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized47_HD1321 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_48_HD1322 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized48_HD1323 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_47_HD1324 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized49_HD1325 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_46_HD1326 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized50_HD1327 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_45_HD1328 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized51_HD1329 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_44_HD1330 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized31_HD1331 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_52_HD1332 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized32_HD1333 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1334 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized33_HD1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_51_HD1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized52_HD1337 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_43_HD1338 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized53_HD1339 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_42_HD1340 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized54_HD1341 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1342 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized55_HD1343 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_41_HD1344 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized56_HD1345 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_40_HD1346 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized57_HD1347 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_39_HD1348 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized59_HD1349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_38_HD1350 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized61_HD1351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_37_HD1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_36_HD1354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized34_HD1355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_50_HD1356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1357 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | chan_crc_ila_xsdbs_v1_0_2_reg_stream_HD1358 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_HD1359 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1360 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1360 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_HD1361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1362 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1362 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection_HD1363 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__2_HD1364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__3_HD1365 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__1_HD1366 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer_HD1367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection__1_HD1368 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1369 | 130(0.04%) | 38(0.01%) | 0(0.00%) | 92(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1369 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | chan_crc_ila_ltlib_v1_0_0_match_HD1370 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | chan_crc_ila_ltlib_v1_0_0_match_HD1370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1371 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1372 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1372 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_34_HD1373 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD1374 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1375 | 120(0.03%) | 37(0.01%) | 0(0.00%) | 83(0.05%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1375 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1376 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1377 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1378 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1378 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_HD1379 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_27_HD1380 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_28_HD1381 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_29_HD1382 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_30_HD1383 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_31_HD1384 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_32_HD1385 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1386 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1387 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1388 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1389 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1389 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1390 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1391 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1392 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1393 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1393 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD1394 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1395 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1396 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1397 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1397 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23_HD1398 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1399 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1400 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1401 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1401 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD1402 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1403 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1404 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1405 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1405 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD1406 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1407 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1408 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1409 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1409 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD1410 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1411 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1412 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1413 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1413 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD1414 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1415 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1416 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1417 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1417 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1418 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1419 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1420 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1421 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1421 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD1422 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1423 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1424 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1425 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1425 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD1426 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | chan_crc_ila_ltlib_v1_0_0_generic_memrd_HD1427 | 55(0.02%) | 53(0.02%) | 0(0.00%) | 2(0.01%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_13 | fex_rx_checker__xdcDup__3 | 1455(0.42%) | 1275(0.37%) | 0(0.00%) | 180(0.10%) | 1964(0.28%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ILA_axi_chan_13) | fex_rx_checker__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | backplane_crc__7 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | backplane_crc__7 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_2010 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_2011 | 212(0.06%) | 212(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_crc_check | chan_crc_ila_HD1428 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_crc_check) | chan_crc_ila_HD1428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | chan_crc_ila_ila_v6_2_12_ila_HD1429 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | chan_crc_ila_ila_v6_2_12_ila_HD1429 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | chan_crc_ila_ila_v6_2_12_ila_core_HD1430 | 1152(0.33%) | 972(0.28%) | 0(0.00%) | 180(0.10%) | 1783(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | chan_crc_ila_ila_v6_2_12_ila_core_HD1430 | 38(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.02%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | chan_crc_ila_ila_v6_2_12_ila_trace_memory_HD1431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | chan_crc_ila_blk_mem_gen_v8_4_5_HD1432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_synth_HD1433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD1440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD1441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1442 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1442 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | chan_crc_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD1443 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | chan_crc_ila_ltlib_v1_0_0_cfglut7_HD1444 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | chan_crc_ila_ltlib_v1_0_0_cfglut7__1_HD1445 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1446 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1446 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | chan_crc_ila_ltlib_v1_0_0_cfglut6__1_HD1447 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1448 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1448 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | chan_crc_ila_ltlib_v1_0_0_cfglut4__1_HD1449 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__1_HD1450 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | chan_crc_ila_ltlib_v1_0_0_cfglut6_HD1451 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__1_HD1452 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1453 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1454 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1454 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_59_HD1455 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_60_HD1456 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1457 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1457 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | chan_crc_ila_ltlib_v1_0_0_cfglut4_HD1458 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5_HD1459 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__2_HD1460 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay_HD1461 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1462 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1463 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1463 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1464 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1465 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__2_HD1466 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1467 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1468 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1468 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_55_HD1469 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_56_HD1470 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | chan_crc_ila_ila_v6_2_12_ila_register_HD1471 | 842(0.24%) | 841(0.24%) | 0(0.00%) | 1(0.01%) | 1223(0.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | chan_crc_ila_ila_v6_2_12_ila_register_HD1471 | 320(0.09%) | 319(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s_HD1472 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1473 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1474 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1475 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1476 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1477 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1478 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1479 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1480 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1481 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1482 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1483 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | chan_crc_ila_xsdbs_v1_0_2_xsdbs_HD1484 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized46_HD1485 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_49_HD1486 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized47_HD1487 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_48_HD1488 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized48_HD1489 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_47_HD1490 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized49_HD1491 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_46_HD1492 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized50_HD1493 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_45_HD1494 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized51_HD1495 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_44_HD1496 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized31_HD1497 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_52_HD1498 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized32_HD1499 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1500 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized33_HD1501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_51_HD1502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized52_HD1503 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_43_HD1504 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized53_HD1505 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_42_HD1506 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized54_HD1507 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1508 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized55_HD1509 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_41_HD1510 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized56_HD1511 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_40_HD1512 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized57_HD1513 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_39_HD1514 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized59_HD1515 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_38_HD1516 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized61_HD1517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_37_HD1518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_36_HD1520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized34_HD1521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_50_HD1522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1523 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | chan_crc_ila_xsdbs_v1_0_2_reg_stream_HD1524 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_HD1525 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1526 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1526 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_HD1527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1528 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1528 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection_HD1529 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__2_HD1530 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__3_HD1531 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__1_HD1532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer_HD1533 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection__1_HD1534 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1535 | 130(0.04%) | 38(0.01%) | 0(0.00%) | 92(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1535 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | chan_crc_ila_ltlib_v1_0_0_match_HD1536 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | chan_crc_ila_ltlib_v1_0_0_match_HD1536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1537 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1538 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1538 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_34_HD1539 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD1540 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1541 | 120(0.03%) | 37(0.01%) | 0(0.00%) | 83(0.05%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1541 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1542 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1543 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1544 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1544 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_HD1545 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_27_HD1546 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_28_HD1547 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_29_HD1548 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_30_HD1549 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_31_HD1550 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_32_HD1551 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1552 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1553 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1554 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1555 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1555 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1556 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1557 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1558 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1559 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1559 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD1560 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1561 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1562 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1563 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1563 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23_HD1564 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1565 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1566 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1567 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1567 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD1568 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1569 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1570 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1571 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1571 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD1572 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1573 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1574 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1575 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1575 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD1576 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1577 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1578 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1579 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1579 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD1580 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1581 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1582 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1583 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1583 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1584 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1585 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1586 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1587 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1587 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD1588 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1589 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1590 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1591 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1591 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD1592 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | chan_crc_ila_ltlib_v1_0_0_generic_memrd_HD1593 | 55(0.02%) | 53(0.02%) | 0(0.00%) | 2(0.01%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_14 | fex_rx_checker__xdcDup__4 | 1460(0.42%) | 1280(0.37%) | 0(0.00%) | 180(0.10%) | 1964(0.28%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ILA_axi_chan_14) | fex_rx_checker__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | backplane_crc__8 | 307(0.09%) | 307(0.09%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | backplane_crc__8 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_2008 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_2009 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_crc_check | chan_crc_ila_HD1594 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_crc_check) | chan_crc_ila_HD1594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | chan_crc_ila_ila_v6_2_12_ila_HD1595 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | chan_crc_ila_ila_v6_2_12_ila_HD1595 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | chan_crc_ila_ila_v6_2_12_ila_core_HD1596 | 1152(0.33%) | 972(0.28%) | 0(0.00%) | 180(0.10%) | 1783(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | chan_crc_ila_ila_v6_2_12_ila_core_HD1596 | 38(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.02%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | chan_crc_ila_ila_v6_2_12_ila_trace_memory_HD1597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | chan_crc_ila_blk_mem_gen_v8_4_5_HD1598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_synth_HD1599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD1606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD1607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1608 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD1608 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | chan_crc_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD1609 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | chan_crc_ila_ltlib_v1_0_0_cfglut7_HD1610 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | chan_crc_ila_ltlib_v1_0_0_cfglut7__1_HD1611 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1612 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD1612 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | chan_crc_ila_ltlib_v1_0_0_cfglut6__1_HD1613 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1614 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD1614 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | chan_crc_ila_ltlib_v1_0_0_cfglut4__1_HD1615 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__1_HD1616 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | chan_crc_ila_ltlib_v1_0_0_cfglut6_HD1617 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__1_HD1618 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1619 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD1619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1620 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD1620 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_59_HD1621 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_60_HD1622 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1623 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD1623 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | chan_crc_ila_ltlib_v1_0_0_cfglut4_HD1624 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5_HD1625 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__2_HD1626 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay_HD1627 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1628 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD1628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1629 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD1629 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1630 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1631 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__2_HD1632 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1633 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD1633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1634 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD1634 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_55_HD1635 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_56_HD1636 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | chan_crc_ila_ila_v6_2_12_ila_register_HD1637 | 842(0.24%) | 841(0.24%) | 0(0.00%) | 1(0.01%) | 1223(0.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | chan_crc_ila_ila_v6_2_12_ila_register_HD1637 | 321(0.09%) | 320(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s_HD1638 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1639 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1640 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1641 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1642 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1643 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1644 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1645 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1646 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1647 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1648 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1649 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | chan_crc_ila_xsdbs_v1_0_2_xsdbs_HD1650 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized46_HD1651 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_49_HD1652 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized47_HD1653 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_48_HD1654 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized48_HD1655 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_47_HD1656 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized49_HD1657 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_46_HD1658 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized50_HD1659 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_45_HD1660 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized51_HD1661 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_44_HD1662 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized31_HD1663 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_52_HD1664 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized32_HD1665 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1666 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized33_HD1667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_51_HD1668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized52_HD1669 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_43_HD1670 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized53_HD1671 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_42_HD1672 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized54_HD1673 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1674 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized55_HD1675 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_41_HD1676 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized56_HD1677 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_40_HD1678 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized57_HD1679 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_39_HD1680 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized59_HD1681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_38_HD1682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized61_HD1683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_37_HD1684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_36_HD1686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized34_HD1687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_50_HD1688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1689 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | chan_crc_ila_xsdbs_v1_0_2_reg_stream_HD1690 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_HD1691 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1692 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1692 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_HD1693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1694 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1694 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection_HD1695 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__2_HD1696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__3_HD1697 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__1_HD1698 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer_HD1699 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection__1_HD1700 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1701 | 130(0.04%) | 38(0.01%) | 0(0.00%) | 92(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | chan_crc_ila_ltlib_v1_0_0_match_HD1702 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | chan_crc_ila_ltlib_v1_0_0_match_HD1702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1703 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1704 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1704 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_34_HD1705 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD1706 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1707 | 120(0.03%) | 37(0.01%) | 0(0.00%) | 83(0.05%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1707 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1708 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1709 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1710 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1710 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_HD1711 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_27_HD1712 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_28_HD1713 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_29_HD1714 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_30_HD1715 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_31_HD1716 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_32_HD1717 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1718 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1719 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1720 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1721 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1721 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1722 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1723 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1724 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1725 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1725 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD1726 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1727 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1728 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1729 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1729 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23_HD1730 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1731 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1732 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1733 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1733 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD1734 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1735 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1736 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1737 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1737 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD1738 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1739 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1740 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1741 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1741 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD1742 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1743 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1744 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1745 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1745 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD1746 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1747 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1748 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1749 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1749 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1750 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1751 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1752 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1753 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1753 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD1754 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1755 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1756 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1757 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1757 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD1758 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | chan_crc_ila_ltlib_v1_0_0_generic_memrd_HD1759 | 55(0.02%) | 53(0.02%) | 0(0.00%) | 2(0.01%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_15 | fex_rx_checker | 1454(0.42%) | 1274(0.37%) | 0(0.00%) | 180(0.10%) | 1964(0.28%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ILA_axi_chan_15) | fex_rx_checker | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | backplane_crc | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | backplane_crc | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_2006 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_2007 | 212(0.06%) | 212(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_crc_check | chan_crc_ila | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_crc_check) | chan_crc_ila | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | chan_crc_ila_ila_v6_2_12_ila | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | chan_crc_ila_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | chan_crc_ila_ila_v6_2_12_ila_core | 1152(0.33%) | 972(0.28%) | 0(0.00%) | 180(0.10%) | 1783(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | chan_crc_ila_ila_v6_2_12_ila_core | 38(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.02%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | chan_crc_ila_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | chan_crc_ila_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | chan_crc_ila_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | chan_crc_ila_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | chan_crc_ila_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | chan_crc_ila_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | chan_crc_ila_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | chan_crc_ila_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_60 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | chan_crc_ila_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_56 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | chan_crc_ila_ila_v6_2_12_ila_register | 842(0.24%) | 841(0.24%) | 0(0.00%) | 1(0.01%) | 1223(0.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | chan_crc_ila_ila_v6_2_12_ila_register | 320(0.09%) | 319(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | chan_crc_ila_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized59 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_38 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | chan_crc_ila_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | chan_crc_ila_ila_v6_2_12_ila_trigger | 130(0.04%) | 38(0.01%) | 0(0.00%) | 92(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | chan_crc_ila_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | chan_crc_ila_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | chan_crc_ila_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | chan_crc_ila_ila_v6_2_12_ila_trig_match | 120(0.03%) | 37(0.01%) | 0(0.00%) | 83(0.05%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | chan_crc_ila_ila_v6_2_12_ila_trig_match | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | chan_crc_ila_ltlib_v1_0_0_generic_memrd | 55(0.02%) | 53(0.02%) | 0(0.00%) | 2(0.01%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_4 | axi_ch0 | 898(0.26%) | 754(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ILA_axi_chan_4) | axi_ch0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_ch0_ila_v6_2_12_ila | 898(0.26%) | 754(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_ch0_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | axi_ch0_ila_v6_2_12_ila_core | 897(0.26%) | 753(0.22%) | 0(0.00%) | 144(0.08%) | 1482(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | axi_ch0_ila_v6_2_12_ila_core | 36(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.02%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | axi_ch0_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | axi_ch0_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | valid.cstr | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | axi_ch0_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | axi_ch0_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | axi_ch0_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | axi_ch0_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | axi_ch0_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | axi_ch0_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | axi_ch0_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | axi_ch0_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | axi_ch0_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | axi_ch0_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | axi_ch0_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | axi_ch0_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | axi_ch0_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | axi_ch0_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | axi_ch0_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | axi_ch0_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | axi_ch0_ila_v6_2_12_ila_register | 612(0.18%) | 611(0.18%) | 0(0.00%) | 1(0.01%) | 964(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | axi_ch0_ila_v6_2_12_ila_register | 273(0.08%) | 272(0.08%) | 0(0.00%) | 1(0.01%) | 160(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | axi_ch0_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | axi_ch0_xsdbs_v1_0_2_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | axi_ch0_xsdbs_v1_0_2_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | axi_ch0_xsdbs_v1_0_2_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | axi_ch0_xsdbs_v1_0_2_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | axi_ch0_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | axi_ch0_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | axi_ch0_xsdbs_v1_0_2_reg__parameterized19 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | axi_ch0_xsdbs_v1_0_2_reg__parameterized20 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | axi_ch0_xsdbs_v1_0_2_reg__parameterized21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | axi_ch0_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | axi_ch0_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_24 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | axi_ch0_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | axi_ch0_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_23 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | axi_ch0_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_22 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | axi_ch0_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | axi_ch0_xsdbs_v1_0_2_reg__parameterized47 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | axi_ch0_xsdbs_v1_0_2_reg__parameterized49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | axi_ch0_xsdbs_v1_0_2_reg__parameterized52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | axi_ch0_xsdbs_v1_0_2_reg__parameterized52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | axi_ch0_xsdbs_v1_0_2_reg__parameterized22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | axi_ch0_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | axi_ch0_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | axi_ch0_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | axi_ch0_ila_v6_2_12_ila_trigger | 93(0.03%) | 35(0.01%) | 0(0.00%) | 58(0.03%) | 154(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | axi_ch0_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | axi_ch0_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | axi_ch0_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | axi_ch0_ila_v6_2_12_ila_trig_match | 87(0.03%) | 34(0.01%) | 0(0.00%) | 53(0.03%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | axi_ch0_ila_v6_2_12_ila_trig_match | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | axi_ch0_ltlib_v1_0_0_generic_memrd | 69(0.02%) | 67(0.02%) | 0(0.00%) | 2(0.01%) | 92(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_5 | axi_ch0_HD4 | 899(0.26%) | 755(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ILA_axi_chan_5) | axi_ch0_HD4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_ch0_ila_v6_2_12_ila_HD5 | 899(0.26%) | 755(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_ch0_ila_v6_2_12_ila_HD5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | axi_ch0_ila_v6_2_12_ila_core_HD6 | 898(0.26%) | 754(0.22%) | 0(0.00%) | 144(0.08%) | 1482(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | axi_ch0_ila_v6_2_12_ila_core_HD6 | 36(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.02%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | axi_ch0_ila_v6_2_12_ila_trace_memory_HD7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | axi_ch0_blk_mem_gen_v8_4_5_HD8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_synth_HD9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | valid.cstr | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy_HD16 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy_HD16 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | axi_ch0_ltlib_v1_0_0_cfglut6__parameterized0_HD17 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | axi_ch0_ltlib_v1_0_0_cfglut7_HD18 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | axi_ch0_ltlib_v1_0_0_cfglut7__1_HD19 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | axi_ch0_ila_v6_2_12_ila_cap_addrgen_HD20 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | axi_ch0_ila_v6_2_12_ila_cap_addrgen_HD20 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | axi_ch0_ltlib_v1_0_0_cfglut6__1_HD21 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | axi_ch0_ila_v6_2_12_ila_cap_sample_counter_HD22 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | axi_ch0_ila_v6_2_12_ila_cap_sample_counter_HD22 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | axi_ch0_ltlib_v1_0_0_cfglut4__1_HD23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__1_HD24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | axi_ch0_ltlib_v1_0_0_cfglut6_HD25 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | axi_ch0_ltlib_v1_0_0_match_nodelay__1_HD26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39_HD27 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39_HD27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40_HD28 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40_HD28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_41_HD29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_42_HD30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | axi_ch0_ila_v6_2_12_ila_cap_window_counter_HD31 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | axi_ch0_ila_v6_2_12_ila_cap_window_counter_HD31 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | axi_ch0_ltlib_v1_0_0_cfglut4_HD32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5_HD33 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__2_HD34 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | axi_ch0_ltlib_v1_0_0_match_nodelay_HD35 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_HD36 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_HD36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_HD37 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_HD37 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | axi_ch0_ltlib_v1_0_0_match_nodelay__2_HD40 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35_HD41 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35_HD41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36_HD42 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36_HD42 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_37_HD43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_38_HD44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | axi_ch0_ila_v6_2_12_ila_register_HD45 | 613(0.18%) | 612(0.18%) | 0(0.00%) | 1(0.01%) | 964(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | axi_ch0_ila_v6_2_12_ila_register_HD45 | 274(0.08%) | 273(0.08%) | 0(0.00%) | 1(0.01%) | 160(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s_HD46 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized0_HD47 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized1_HD48 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized2_HD49 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized3_HD50 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized4_HD51 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | axi_ch0_xsdbs_v1_0_2_xsdbs_HD52 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | axi_ch0_xsdbs_v1_0_2_reg__parameterized34_HD53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_31_HD54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | axi_ch0_xsdbs_v1_0_2_reg__parameterized35_HD55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_30_HD56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | axi_ch0_xsdbs_v1_0_2_reg__parameterized36_HD57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_29_HD58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | axi_ch0_xsdbs_v1_0_2_reg__parameterized37_HD59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_28_HD60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | axi_ch0_xsdbs_v1_0_2_reg__parameterized38_HD61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_27_HD62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | axi_ch0_xsdbs_v1_0_2_reg__parameterized39_HD63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_26_HD64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | axi_ch0_xsdbs_v1_0_2_reg__parameterized19_HD65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_34_HD66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | axi_ch0_xsdbs_v1_0_2_reg__parameterized20_HD67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized0_HD68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | axi_ch0_xsdbs_v1_0_2_reg__parameterized21_HD69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_33_HD70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | axi_ch0_xsdbs_v1_0_2_reg__parameterized40_HD71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_25_HD72 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | axi_ch0_xsdbs_v1_0_2_reg__parameterized41_HD73 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_24_HD74 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | axi_ch0_xsdbs_v1_0_2_reg__parameterized42_HD75 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_HD76 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | axi_ch0_xsdbs_v1_0_2_reg__parameterized43_HD77 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_23_HD78 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | axi_ch0_xsdbs_v1_0_2_reg__parameterized44_HD79 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_22_HD80 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | axi_ch0_xsdbs_v1_0_2_reg__parameterized45_HD81 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_21_HD82 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | axi_ch0_xsdbs_v1_0_2_reg__parameterized47_HD83 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_20_HD84 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | axi_ch0_xsdbs_v1_0_2_reg__parameterized49_HD85 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_19_HD86 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | axi_ch0_xsdbs_v1_0_2_reg__parameterized52_HD87 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | axi_ch0_xsdbs_v1_0_2_reg__parameterized52_HD87 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_18_HD88 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | axi_ch0_xsdbs_v1_0_2_reg__parameterized22_HD89 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_32_HD90 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized5_HD91 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | axi_ch0_xsdbs_v1_0_2_reg_stream_HD92 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_HD93 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0_HD94 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0_HD94 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_HD95 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | axi_ch0_ila_v6_2_12_ila_reset_ctrl_HD96 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | axi_ch0_ila_v6_2_12_ila_reset_ctrl_HD96 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection_HD97 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__2_HD98 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__3_HD99 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__1_HD100 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer_HD101 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection__1_HD102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | axi_ch0_ila_v6_2_12_ila_trigger_HD103 | 93(0.03%) | 35(0.01%) | 0(0.00%) | 58(0.03%) | 154(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | axi_ch0_ila_v6_2_12_ila_trigger_HD103 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | axi_ch0_ltlib_v1_0_0_match_HD104 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | axi_ch0_ltlib_v1_0_0_match_HD104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_HD105 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_HD105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_16_HD106 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_16_HD106 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_17_HD107 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | axi_ch0_ila_v6_2_12_ila_trig_match_HD108 | 87(0.03%) | 34(0.01%) | 0(0.00%) | 53(0.03%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | axi_ch0_ila_v6_2_12_ila_trig_match_HD108 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized0_HD109 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized0_HD109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0_HD110 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0_HD110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0_HD111 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0_HD111 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD112 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_9_HD113 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD114 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD115 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_12_HD116 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD117 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD118 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_15_HD119 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__1_HD120 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__1_HD120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD121 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_7_HD122 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_7_HD122 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_8_HD123 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__2_HD124 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__2_HD124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD125 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_4_HD126 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_4_HD126 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_5_HD127 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__3_HD128 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__3_HD128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD129 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_1_HD130 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_1_HD130 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_2_HD131 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1_HD132 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1_HD132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_HD133 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_HD133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_HD134 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_HD134 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_HD135 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | axi_ch0_ltlib_v1_0_0_generic_memrd_HD136 | 69(0.02%) | 67(0.02%) | 0(0.00%) | 2(0.01%) | 92(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_6 | axi_ch0_HD137 | 897(0.26%) | 753(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ILA_axi_chan_6) | axi_ch0_HD137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_ch0_ila_v6_2_12_ila_HD138 | 897(0.26%) | 753(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_ch0_ila_v6_2_12_ila_HD138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | axi_ch0_ila_v6_2_12_ila_core_HD139 | 896(0.26%) | 752(0.22%) | 0(0.00%) | 144(0.08%) | 1482(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | axi_ch0_ila_v6_2_12_ila_core_HD139 | 36(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.02%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | axi_ch0_ila_v6_2_12_ila_trace_memory_HD140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | axi_ch0_blk_mem_gen_v8_4_5_HD141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_synth_HD142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | valid.cstr | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy_HD149 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy_HD149 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | axi_ch0_ltlib_v1_0_0_cfglut6__parameterized0_HD150 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | axi_ch0_ltlib_v1_0_0_cfglut7_HD151 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | axi_ch0_ltlib_v1_0_0_cfglut7__1_HD152 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | axi_ch0_ila_v6_2_12_ila_cap_addrgen_HD153 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | axi_ch0_ila_v6_2_12_ila_cap_addrgen_HD153 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | axi_ch0_ltlib_v1_0_0_cfglut6__1_HD154 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | axi_ch0_ila_v6_2_12_ila_cap_sample_counter_HD155 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | axi_ch0_ila_v6_2_12_ila_cap_sample_counter_HD155 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | axi_ch0_ltlib_v1_0_0_cfglut4__1_HD156 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__1_HD157 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | axi_ch0_ltlib_v1_0_0_cfglut6_HD158 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | axi_ch0_ltlib_v1_0_0_match_nodelay__1_HD159 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39_HD160 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39_HD160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40_HD161 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40_HD161 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_41_HD162 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_42_HD163 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | axi_ch0_ila_v6_2_12_ila_cap_window_counter_HD164 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | axi_ch0_ila_v6_2_12_ila_cap_window_counter_HD164 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | axi_ch0_ltlib_v1_0_0_cfglut4_HD165 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5_HD166 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__2_HD167 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | axi_ch0_ltlib_v1_0_0_match_nodelay_HD168 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_HD169 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_HD169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_HD170 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_HD170 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD171 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD172 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | axi_ch0_ltlib_v1_0_0_match_nodelay__2_HD173 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35_HD174 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35_HD174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36_HD175 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36_HD175 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_37_HD176 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_38_HD177 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | axi_ch0_ila_v6_2_12_ila_register_HD178 | 611(0.18%) | 610(0.18%) | 0(0.00%) | 1(0.01%) | 964(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | axi_ch0_ila_v6_2_12_ila_register_HD178 | 274(0.08%) | 273(0.08%) | 0(0.00%) | 1(0.01%) | 160(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s_HD179 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized0_HD180 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized1_HD181 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized2_HD182 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized3_HD183 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized4_HD184 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | axi_ch0_xsdbs_v1_0_2_xsdbs_HD185 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | axi_ch0_xsdbs_v1_0_2_reg__parameterized34_HD186 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_31_HD187 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | axi_ch0_xsdbs_v1_0_2_reg__parameterized35_HD188 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_30_HD189 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | axi_ch0_xsdbs_v1_0_2_reg__parameterized36_HD190 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_29_HD191 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | axi_ch0_xsdbs_v1_0_2_reg__parameterized37_HD192 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_28_HD193 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | axi_ch0_xsdbs_v1_0_2_reg__parameterized38_HD194 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_27_HD195 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | axi_ch0_xsdbs_v1_0_2_reg__parameterized39_HD196 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_26_HD197 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | axi_ch0_xsdbs_v1_0_2_reg__parameterized19_HD198 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_34_HD199 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | axi_ch0_xsdbs_v1_0_2_reg__parameterized20_HD200 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized0_HD201 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | axi_ch0_xsdbs_v1_0_2_reg__parameterized21_HD202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_33_HD203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | axi_ch0_xsdbs_v1_0_2_reg__parameterized40_HD204 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_25_HD205 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | axi_ch0_xsdbs_v1_0_2_reg__parameterized41_HD206 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_24_HD207 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | axi_ch0_xsdbs_v1_0_2_reg__parameterized42_HD208 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_HD209 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | axi_ch0_xsdbs_v1_0_2_reg__parameterized43_HD210 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_23_HD211 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | axi_ch0_xsdbs_v1_0_2_reg__parameterized44_HD212 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_22_HD213 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | axi_ch0_xsdbs_v1_0_2_reg__parameterized45_HD214 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_21_HD215 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | axi_ch0_xsdbs_v1_0_2_reg__parameterized47_HD216 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_20_HD217 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | axi_ch0_xsdbs_v1_0_2_reg__parameterized49_HD218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_19_HD219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | axi_ch0_xsdbs_v1_0_2_reg__parameterized52_HD220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | axi_ch0_xsdbs_v1_0_2_reg__parameterized52_HD220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_18_HD221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | axi_ch0_xsdbs_v1_0_2_reg__parameterized22_HD222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_32_HD223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized5_HD224 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | axi_ch0_xsdbs_v1_0_2_reg_stream_HD225 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_HD226 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0_HD227 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0_HD227 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_HD228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | axi_ch0_ila_v6_2_12_ila_reset_ctrl_HD229 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | axi_ch0_ila_v6_2_12_ila_reset_ctrl_HD229 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection_HD230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__2_HD231 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__3_HD232 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__1_HD233 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer_HD234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection__1_HD235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | axi_ch0_ila_v6_2_12_ila_trigger_HD236 | 93(0.03%) | 35(0.01%) | 0(0.00%) | 58(0.03%) | 154(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | axi_ch0_ila_v6_2_12_ila_trigger_HD236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | axi_ch0_ltlib_v1_0_0_match_HD237 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | axi_ch0_ltlib_v1_0_0_match_HD237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_HD238 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_HD238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_16_HD239 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_16_HD239 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_17_HD240 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | axi_ch0_ila_v6_2_12_ila_trig_match_HD241 | 87(0.03%) | 34(0.01%) | 0(0.00%) | 53(0.03%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | axi_ch0_ila_v6_2_12_ila_trig_match_HD241 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized0_HD242 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized0_HD242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0_HD243 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0_HD243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0_HD244 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0_HD244 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD245 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_9_HD246 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD247 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD248 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_12_HD249 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD250 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD251 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_15_HD252 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__1_HD253 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__1_HD253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD254 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_7_HD255 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_7_HD255 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_8_HD256 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__2_HD257 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__2_HD257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD258 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_4_HD259 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_4_HD259 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_5_HD260 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__3_HD261 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__3_HD261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD262 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_1_HD263 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_1_HD263 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_2_HD264 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1_HD265 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1_HD265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_HD266 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_HD266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_HD267 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_HD267 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_HD268 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | axi_ch0_ltlib_v1_0_0_generic_memrd_HD269 | 69(0.02%) | 67(0.02%) | 0(0.00%) | 2(0.01%) | 92(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_7 | axi_ch0_HD270 | 898(0.26%) | 754(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ILA_axi_chan_7) | axi_ch0_HD270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_ch0_ila_v6_2_12_ila_HD271 | 898(0.26%) | 754(0.22%) | 0(0.00%) | 144(0.08%) | 1488(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_ch0_ila_v6_2_12_ila_HD271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | axi_ch0_ila_v6_2_12_ila_core_HD272 | 897(0.26%) | 753(0.22%) | 0(0.00%) | 144(0.08%) | 1482(0.21%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | axi_ch0_ila_v6_2_12_ila_core_HD272 | 36(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.02%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | axi_ch0_ila_v6_2_12_ila_trace_memory_HD273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | axi_ch0_blk_mem_gen_v8_4_5_HD274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_synth_HD275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | valid.cstr | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_ch0_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy_HD282 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | axi_ch0_ila_v6_2_12_ila_cap_ctrl_legacy_HD282 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | axi_ch0_ltlib_v1_0_0_cfglut6__parameterized0_HD283 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | axi_ch0_ltlib_v1_0_0_cfglut7_HD284 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | axi_ch0_ltlib_v1_0_0_cfglut7__1_HD285 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | axi_ch0_ila_v6_2_12_ila_cap_addrgen_HD286 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | axi_ch0_ila_v6_2_12_ila_cap_addrgen_HD286 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | axi_ch0_ltlib_v1_0_0_cfglut6__1_HD287 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | axi_ch0_ila_v6_2_12_ila_cap_sample_counter_HD288 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | axi_ch0_ila_v6_2_12_ila_cap_sample_counter_HD288 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | axi_ch0_ltlib_v1_0_0_cfglut4__1_HD289 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__1_HD290 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | axi_ch0_ltlib_v1_0_0_cfglut6_HD291 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | axi_ch0_ltlib_v1_0_0_match_nodelay__1_HD292 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39_HD293 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_39_HD293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40_HD294 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_40_HD294 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_41_HD295 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_42_HD296 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | axi_ch0_ila_v6_2_12_ila_cap_window_counter_HD297 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | axi_ch0_ila_v6_2_12_ila_cap_window_counter_HD297 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | axi_ch0_ltlib_v1_0_0_cfglut4_HD298 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5_HD299 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | axi_ch0_ltlib_v1_0_0_cfglut5__2_HD300 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | axi_ch0_ltlib_v1_0_0_match_nodelay_HD301 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_HD302 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_HD302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_HD303 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_HD303 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD304 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD305 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | axi_ch0_ltlib_v1_0_0_match_nodelay__2_HD306 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35_HD307 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_nodelay_35_HD307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36_HD308 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized1_36_HD308 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized1_37_HD309 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized2_38_HD310 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | axi_ch0_ila_v6_2_12_ila_register_HD311 | 612(0.18%) | 611(0.18%) | 0(0.00%) | 1(0.01%) | 964(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | axi_ch0_ila_v6_2_12_ila_register_HD311 | 274(0.08%) | 273(0.08%) | 0(0.00%) | 1(0.01%) | 160(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s_HD312 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized0_HD313 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized1_HD314 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized2_HD315 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized3_HD316 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized4_HD317 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | axi_ch0_xsdbs_v1_0_2_xsdbs_HD318 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | axi_ch0_xsdbs_v1_0_2_reg__parameterized34_HD319 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_31_HD320 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | axi_ch0_xsdbs_v1_0_2_reg__parameterized35_HD321 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_30_HD322 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | axi_ch0_xsdbs_v1_0_2_reg__parameterized36_HD323 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_29_HD324 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | axi_ch0_xsdbs_v1_0_2_reg__parameterized37_HD325 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_28_HD326 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | axi_ch0_xsdbs_v1_0_2_reg__parameterized38_HD327 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_27_HD328 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | axi_ch0_xsdbs_v1_0_2_reg__parameterized39_HD329 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_26_HD330 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | axi_ch0_xsdbs_v1_0_2_reg__parameterized19_HD331 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_34_HD332 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | axi_ch0_xsdbs_v1_0_2_reg__parameterized20_HD333 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized0_HD334 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | axi_ch0_xsdbs_v1_0_2_reg__parameterized21_HD335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_33_HD336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | axi_ch0_xsdbs_v1_0_2_reg__parameterized40_HD337 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_25_HD338 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | axi_ch0_xsdbs_v1_0_2_reg__parameterized41_HD339 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_24_HD340 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | axi_ch0_xsdbs_v1_0_2_reg__parameterized42_HD341 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl__parameterized1_HD342 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | axi_ch0_xsdbs_v1_0_2_reg__parameterized43_HD343 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_23_HD344 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | axi_ch0_xsdbs_v1_0_2_reg__parameterized44_HD345 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_22_HD346 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | axi_ch0_xsdbs_v1_0_2_reg__parameterized45_HD347 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_21_HD348 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | axi_ch0_xsdbs_v1_0_2_reg__parameterized47_HD349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_20_HD350 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | axi_ch0_xsdbs_v1_0_2_reg__parameterized49_HD351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_19_HD352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | axi_ch0_xsdbs_v1_0_2_reg__parameterized52_HD353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | axi_ch0_xsdbs_v1_0_2_reg__parameterized52_HD353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_18_HD354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | axi_ch0_xsdbs_v1_0_2_reg__parameterized22_HD355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_32_HD356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | axi_ch0_xsdbs_v1_0_2_reg_p2s__parameterized5_HD357 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | axi_ch0_xsdbs_v1_0_2_reg_stream_HD358 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | axi_ch0_xsdbs_v1_0_2_reg_ctl_HD359 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0_HD360 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | axi_ch0_xsdbs_v1_0_2_reg_stream__parameterized0_HD360 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | axi_ch0_xsdbs_v1_0_2_reg_stat_HD361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | axi_ch0_ila_v6_2_12_ila_reset_ctrl_HD362 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | axi_ch0_ila_v6_2_12_ila_reset_ctrl_HD362 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection_HD363 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__2_HD364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__3_HD365 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer__1_HD366 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | axi_ch0_ltlib_v1_0_0_async_edge_xfer_HD367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | axi_ch0_ltlib_v1_0_0_rising_edge_detection__1_HD368 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | axi_ch0_ila_v6_2_12_ila_trigger_HD369 | 93(0.03%) | 35(0.01%) | 0(0.00%) | 58(0.03%) | 154(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | axi_ch0_ila_v6_2_12_ila_trigger_HD369 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | axi_ch0_ltlib_v1_0_0_match_HD370 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | axi_ch0_ltlib_v1_0_0_match_HD370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA_HD371 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA_HD371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_16_HD372 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_16_HD372 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_17_HD373 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | axi_ch0_ila_v6_2_12_ila_trig_match_HD374 | 87(0.03%) | 34(0.01%) | 0(0.00%) | 53(0.03%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | axi_ch0_ila_v6_2_12_ila_trig_match_HD374 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized0_HD375 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized0_HD375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0_HD376 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized0_HD376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0_HD377 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA__parameterized0_HD377 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD378 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_9_HD379 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD380 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD381 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_12_HD382 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD383 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD384 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_15_HD385 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__1_HD386 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__1_HD386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD387 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_7_HD388 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_7_HD388 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_8_HD389 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__2_HD390 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__2_HD390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD391 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_4_HD392 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_4_HD392 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_5_HD393 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1__3_HD394 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1__3_HD394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD395 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_1_HD396 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_1_HD396 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_2_HD397 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | axi_ch0_ltlib_v1_0_0_match__parameterized1_HD398 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | axi_ch0_ltlib_v1_0_0_match__parameterized1_HD398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_HD399 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | axi_ch0_ltlib_v1_0_0_allx_typeA__parameterized1_HD399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | axi_ch0_ltlib_v1_0_0_all_typeA_HD400 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | axi_ch0_ltlib_v1_0_0_all_typeA_HD400 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | axi_ch0_ltlib_v1_0_0_all_typeA_slice_HD401 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | axi_ch0_ltlib_v1_0_0_generic_memrd_HD402 | 69(0.02%) | 67(0.02%) | 0(0.00%) | 2(0.01%) | 92(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | alternate_cttc.fm_interface_3 | Full_Mode_CTTC | 5725(1.65%) | 4985(1.44%) | 64(0.04%) | 676(0.39%) | 9279(1.34%) | 16(1.36%) | 4(0.17%) | 0(0.00%) | | (alternate_cttc.fm_interface_3) | Full_Mode_CTTC | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CTTC_receiver | combined_ttc_no_mgt | 1747(0.50%) | 1428(0.41%) | 0(0.00%) | 319(0.18%) | 3092(0.45%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (CTTC_receiver) | combined_ttc_no_mgt | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_frame_check | sume_RO_Rx_GT_FRAME_CHECK | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_rx2_inst | ila_2 | 1573(0.45%) | 1254(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_rx2_inst) | ila_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_2_ila_v6_2_12_ila | 1573(0.45%) | 1254(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_2_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_2_ila_v6_2_12_ila_core | 1572(0.45%) | 1253(0.36%) | 0(0.00%) | 319(0.18%) | 2578(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_2_ila_v6_2_12_ila_core | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 255(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_2_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_2_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[10].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[11].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[8].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[9].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy | 81(0.02%) | 34(0.01%) | 0(0.00%) | 47(0.03%) | 137(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_2_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_2_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_2_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_2_ila_v6_2_12_ila_cap_addrgen | 66(0.02%) | 29(0.01%) | 0(0.00%) | 37(0.02%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_2_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_2_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_2_ila_v6_2_12_ila_cap_sample_counter | 33(0.01%) | 20(0.01%) | 0(0.00%) | 13(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_2_ila_v6_2_12_ila_cap_sample_counter | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_2_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_2_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_2_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_2_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_83 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_84 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_2_ila_v6_2_12_ila_cap_window_counter | 30(0.01%) | 9(0.01%) | 0(0.00%) | 21(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_2_ila_v6_2_12_ila_cap_window_counter | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_2_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_2_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_2_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_2_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_2_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_79 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_80 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_2_ila_v6_2_12_ila_register | 1004(0.29%) | 1003(0.29%) | 0(0.00%) | 1(0.01%) | 1439(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_2_ila_v6_2_12_ila_register | 329(0.09%) | 328(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_2_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_2_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_73 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_2_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_72 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_2_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_2_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_2_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_2_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_2_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_76 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_2_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_2_xsdbs_v1_0_2_reg__parameterized43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_2_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_2_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_2_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_2_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_2_xsdbs_v1_0_2_reg__parameterized66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_2_xsdbs_v1_0_2_reg__parameterized67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_2_xsdbs_v1_0_2_reg__parameterized69 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_2_xsdbs_v1_0_2_reg__parameterized71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_2_xsdbs_v1_0_2_reg__parameterized74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_2_xsdbs_v1_0_2_reg__parameterized74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_2_xsdbs_v1_0_2_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_2_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_2_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_2_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_2_ila_v6_2_12_ila_trigger | 268(0.08%) | 107(0.03%) | 0(0.00%) | 161(0.09%) | 475(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_2_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_2_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_2_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_58 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_2_ila_v6_2_12_ila_trig_match | 258(0.07%) | 106(0.03%) | 0(0.00%) | 152(0.09%) | 456(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_2_ila_v6_2_12_ila_trig_match | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_54 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_56 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_57 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__5 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_2_ltlib_v1_0_0_match__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_2_ltlib_v1_0_0_match__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_2_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_51 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_2_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_2_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_2_ltlib_v1_0_0_generic_memrd | 102(0.03%) | 100(0.03%) | 0(0.00%) | 2(0.01%) | 238(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_regs | rx_registers | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_ttc | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_ttc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_stretcher | pulse_stretch__parameterized7 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_0 | FM_channel__xdcDup__3 | 1816(0.52%) | 1609(0.46%) | 32(0.02%) | 175(0.10%) | 2787(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_0) | FM_channel__xdcDup__3 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD2208 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD2209 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD2210 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD2211 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD2212 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD2213 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD2213 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD2214 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD2215 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD2216 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD2218 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD2219 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD2220 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD2221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD2222 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory_HD2223 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem_HD2224 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD2225 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD2225 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD2226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD2227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD2228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD2229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__5 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux_4 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD2277 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD2277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD2278 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD2278 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD2279 | 1191(0.34%) | 1019(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD2279 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD2280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD2281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD2282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD2283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD2284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD2285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD2286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD2287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD2288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2289 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2289 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD2290 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD2291 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD2292 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2293 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2293 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD2294 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2295 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2295 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD2296 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD2297 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD2298 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD2299 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2300 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2301 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2301 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD2302 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD2303 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2304 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2304 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD2305 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD2306 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD2307 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD2308 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2309 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2310 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2310 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD2311 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD2312 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD2313 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2314 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2315 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2315 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD2316 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD2317 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD2318 | 913(0.26%) | 912(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD2318 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD2319 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD2320 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD2321 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD2322 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD2323 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD2324 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD2325 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD2326 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD2327 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD2328 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD2329 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD2330 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD2331 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD2332 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD2333 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD2334 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD2335 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD2336 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD2337 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD2338 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD2339 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD2340 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD2341 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD2342 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD2343 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD2344 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD2345 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD2346 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD2347 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD2348 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD2349 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD2350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD2351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD2352 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD2353 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD2354 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD2355 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD2356 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD2357 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD2358 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD2359 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD2360 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD2361 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD2362 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD2363 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD2364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD2365 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD2366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD2367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD2369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD2370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD2371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD2372 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD2373 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD2374 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2375 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2375 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD2376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2377 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2377 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD2378 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD2379 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD2380 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD2381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD2382 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD2383 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD2384 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD2384 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD2385 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD2385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2386 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2387 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2387 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD2388 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD2389 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD2390 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD2390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2391 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2392 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2392 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD2393 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD2394 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2395 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2395 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2396 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2397 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2398 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2398 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD2399 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD2400 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD2401 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD2402 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2403 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2404 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2405 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2405 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD2406 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2407 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2408 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2409 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2409 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD2410 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2411 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2412 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2413 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2413 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD2414 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD2415 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD2416 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD2417 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2418 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2419 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2420 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2420 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD2421 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2422 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2423 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2424 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2424 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD2425 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2426 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2427 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2428 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2428 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD2429 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2430 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2431 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2432 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2432 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD2433 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2434 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2435 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2436 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2436 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD2437 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2438 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2439 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2440 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2440 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD2441 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2442 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2443 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2444 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2444 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD2445 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2446 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2447 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2448 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2448 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD2449 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD2450 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__3 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__3 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__5 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__5 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 168(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__5 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_5 | 154(0.04%) | 154(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_6 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_7 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__3 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2859 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2860 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2861 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2862 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2863 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2864 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2864 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2865 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2866 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2867 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2869 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2870 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2871 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as_HD2872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2873 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2874 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2875 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2876 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2877 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2878 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2879 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2880 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2880 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2881 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2882 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2882 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2802 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2803 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2804 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2805 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2806 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2806 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2807 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2808 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2809 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2810 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2811 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_1 | FM_channel | 1822(0.53%) | 1615(0.47%) | 32(0.02%) | 175(0.10%) | 2793(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_1) | FM_channel | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__4 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core | 1191(0.34%) | 1019(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register | 913(0.26%) | 912(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register | 329(0.09%) | 328(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__4 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__4 | 177(0.05%) | 177(0.05%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__4 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4 | 153(0.04%) | 153(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eob_space_trig | pulse_pdxx_pwxx | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sob_space_trig | pulse_pdxx_pwxx_1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_blk | clk_wiz_240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_240_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | combined_transceiver | FullMode_tx_CTTC_rx_support | 235(0.07%) | 228(0.07%) | 0(0.00%) | 7(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (combined_transceiver) | FullMode_tx_CTTC_rx_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_CTTC_rx_init_i | FullMode_tx_CTTC_rx | 156(0.05%) | 149(0.04%) | 0(0.00%) | 7(0.01%) | 237(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | FullMode_tx_CTTC_rx_init | 156(0.05%) | 149(0.04%) | 0(0.00%) | 7(0.01%) | 237(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | FullMode_tx_CTTC_rx_init | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_CTTC_rx_i | FullMode_tx_CTTC_rx_multi_gt | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | FullMode_tx_CTTC_rx_cpll_railing | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_FullMode_tx_CTTC_rx_i | FullMode_tx_CTTC_rx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | FullMode_tx_CTTC_rx_RX_STARTUP_FSM | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | FullMode_tx_CTTC_rx_RX_STARTUP_FSM | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullMode_tx_CTTC_rx_sync_block_5 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullMode_tx_CTTC_rx_sync_block_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullMode_tx_CTTC_rx_sync_block_7 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullMode_tx_CTTC_rx_sync_block_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullMode_tx_CTTC_rx_sync_block_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullMode_tx_CTTC_rx_sync_block_10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullMode_tx_CTTC_rx_sync_block_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | FullMode_tx_CTTC_rx_TX_STARTUP_FSM | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | FullMode_tx_CTTC_rx_TX_STARTUP_FSM | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | FullMode_tx_CTTC_rx_sync_block | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | FullMode_tx_CTTC_rx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullMode_tx_CTTC_rx_sync_block_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullMode_tx_CTTC_rx_sync_block_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullMode_tx_CTTC_rx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | FullMode_tx_CTTC_rx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_i | FullMode_tx | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | FullMode_tx_init | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_i | FullMode_tx_multi_gt | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_FullMode_tx_i | FullMode_tx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | FullMode_tx_TX_STARTUP_FSM | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | FullMode_tx_TX_STARTUP_FSM | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | FullMode_tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | FullMode_tx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullMode_tx_sync_block_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullMode_tx_sync_block_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullMode_tx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | FullMode_tx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | FullMode_tx_CTTC_rx_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | FullMode_tx_CTTC_rx_common_reset | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | FullMode_tx_CTTC_rx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | polarity | vio_ttc_HD407 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (polarity) | vio_ttc_HD407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD408 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD409 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD410 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD411 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD411 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD412 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD413 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | backplane | jfex_backplane | 13630(3.93%) | 12318(3.56%) | 0(0.00%) | 1312(0.75%) | 24545(3.54%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (backplane) | jfex_backplane | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s12_l1 | aurora_1ln_rx_exdes__parameterized3__xdcDup__4 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s12_l1) | aurora_1ln_rx_exdes__parameterized3__xdcDup__4 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__xdcDup__5 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3754 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3755 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3756 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3757 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3757 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3758 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3759 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3760 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3761 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3762 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3763 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3764 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3765 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3766 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3767 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3768 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3769 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3771 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3772 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3775 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3778 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3778 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3780 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3784 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3785 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3786 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3787 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3788 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3789 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3789 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3793 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3793 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3794 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3795 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3796 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3796 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3798 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3809 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2089 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s12_l2 | aurora_1ln_rx_exdes__parameterized1__xdcDup__4 | 442(0.13%) | 404(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s12_l2) | aurora_1ln_rx_exdes__parameterized1__xdcDup__4 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1__xdcDup__4 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3290 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3291 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3292 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3293 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3293 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3294 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3295 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3296 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3297 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3298 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3299 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3300 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3301 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3302 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3302 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3303 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3304 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3305 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3307 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3308 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3311 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3312 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3314 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3314 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3316 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3320 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3321 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3322 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3324 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3325 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3325 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3329 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3329 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3330 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3331 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3332 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3332 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3334 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3337 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2085 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s12_l3 | aurora_1ln_rx_exdes__parameterized3__xdcDup__5 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s12_l3) | aurora_1ln_rx_exdes__parameterized3__xdcDup__5 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__xdcDup__6 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3812 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3813 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3814 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3815 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3815 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3816 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3817 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3818 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3819 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3820 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3821 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3822 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3823 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3824 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3824 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3825 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3826 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3827 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3829 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3830 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3833 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3834 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3836 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3836 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3838 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3842 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3843 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3844 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3845 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3846 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3847 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3847 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3851 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3851 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3852 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3853 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3854 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3854 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3856 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3859 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3867 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s12_l4 | aurora_1ln_rx_exdes__parameterized1__xdcDup__5 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s12_l4) | aurora_1ln_rx_exdes__parameterized1__xdcDup__5 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1__xdcDup__5 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3348 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3349 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3350 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3351 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3351 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3352 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3353 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3354 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3355 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3356 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3357 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3358 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3359 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3360 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3360 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3361 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3362 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3363 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3365 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3366 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3369 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3370 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3372 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3372 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3374 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3378 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3379 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3380 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3382 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3383 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3383 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3387 | 141(0.04%) | 133(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3387 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3388 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3389 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3390 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3390 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3392 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3395 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3403 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2078 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s13_l1 | aurora_1ln_rx_exdes__parameterized3 | 441(0.13%) | 403(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s13_l1) | aurora_1ln_rx_exdes__parameterized3 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3522 | 411(0.12%) | 373(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3523 | 411(0.12%) | 373(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3524 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3525 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3525 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3526 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3527 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3528 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3529 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3530 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3531 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3532 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3533 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3534 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3534 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3535 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3536 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3537 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3539 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3540 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3543 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3546 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3546 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3548 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3552 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3553 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3554 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3556 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3557 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3557 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3561 | 139(0.04%) | 131(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3561 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3562 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3563 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3564 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3564 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3566 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3569 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3577 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s13_l2 | aurora_1ln_rx_exdes__parameterized1__xdcDup__6 | 442(0.13%) | 404(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s13_l2) | aurora_1ln_rx_exdes__parameterized1__xdcDup__6 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1__xdcDup__6 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3406 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3407 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3408 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3409 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3409 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3410 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3411 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3412 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3413 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3414 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3415 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3416 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3417 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3418 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3418 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3419 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3420 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3421 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3423 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3424 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3427 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3428 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3430 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3430 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3432 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3436 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3437 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3438 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3439 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3440 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3441 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3441 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3445 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3445 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3446 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3447 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3448 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3448 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3450 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3461 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2071 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s13_l3 | aurora_1ln_rx_exdes__parameterized1__xdcDup__7 | 441(0.13%) | 403(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s13_l3) | aurora_1ln_rx_exdes__parameterized1__xdcDup__7 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1__xdcDup__7 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3464 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3465 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3466 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3467 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3467 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3468 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3469 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3470 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3471 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3472 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3473 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3474 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3475 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3476 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3476 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3477 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3478 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3479 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3481 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3482 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3485 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3486 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3488 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3488 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3490 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3494 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3495 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3496 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3497 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3498 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3499 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3499 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3503 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3503 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3504 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3505 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3506 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3506 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3508 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3511 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3519 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2068 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s13_l4 | aurora_1ln_rx_exdes__parameterized1 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s13_l4) | aurora_1ln_rx_exdes__parameterized1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3058 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3059 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3060 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3061 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3061 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3062 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3063 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3064 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3065 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3066 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3067 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3068 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3069 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3070 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3071 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3072 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3073 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3075 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3076 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3079 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3080 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3082 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3082 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3084 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3088 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3089 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3090 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3091 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3092 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3093 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3093 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3097 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3097 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3098 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3099 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3100 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3100 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3102 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3105 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2065 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s4_l1 | aurora_1ln_rx_exdes | 444(0.13%) | 406(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s4_l1) | aurora_1ln_rx_exdes | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__xdcDup__1 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common.aurora_1ln_rx_i | aurora_1ln_rx_lpm | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER | 141(0.04%) | 133(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2062 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s4_l2 | aurora_1ln_rx_no_comm__xdcDup__1 | 444(0.13%) | 406(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s4_l2) | aurora_1ln_rx_no_comm__xdcDup__1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__1 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3928 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3929 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3930 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3931 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3931 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3932 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3933 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3934 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3935 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3936 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3937 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3938 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3939 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3940 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3940 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3941 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3942 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3943 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3945 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3946 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3949 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3950 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3952 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3952 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3954 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3958 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3959 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3960 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3961 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3962 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3963 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3963 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3967 | 141(0.04%) | 133(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3967 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3968 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3969 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3970 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3970 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3972 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3983 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2058 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s4_l3 | aurora_1ln_rx_no_comm__xdcDup__2 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s4_l3) | aurora_1ln_rx_no_comm__xdcDup__2 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__2 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3986 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3987 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3988 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3989 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3989 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3990 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3991 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3992 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3993 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3994 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3995 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3996 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3997 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3998 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3998 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3999 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD4000 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD4001 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD4002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD4003 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD4004 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD4005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD4006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD4007 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD4008 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD4009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4010 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4010 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD4011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD4012 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD4013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD4015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD4016 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD4017 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD4018 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD4019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD4020 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD4021 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD4021 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD4022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD4024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD4025 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD4025 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD4026 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD4027 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD4028 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD4028 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD4030 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD4032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD4033 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD4035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD4036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD4039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD4040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD4041 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD4043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2055 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s4_l4 | aurora_1ln_rx_no_comm__xdcDup__3 | 442(0.13%) | 404(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s4_l4) | aurora_1ln_rx_no_comm__xdcDup__3 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__3 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD4044 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD4045 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD4046 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD4047 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD4047 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD4048 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD4049 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD4050 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD4051 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD4052 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD4053 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD4054 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD4055 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4056 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4056 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD4057 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD4058 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD4059 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD4060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD4061 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD4062 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD4063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD4064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD4065 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD4066 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD4067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4068 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4068 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD4069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD4070 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD4071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD4073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD4074 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD4075 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD4076 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD4077 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD4078 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD4079 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD4079 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD4080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD4081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD4082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD4083 | 139(0.04%) | 131(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD4083 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD4084 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD4085 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD4086 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD4086 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD4088 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD4090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD4091 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD4093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD4094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD4097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD4098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD4099 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD4101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s5_l1 | aurora_1ln_rx_exdes__parameterized1__xdcDup__1 | 444(0.13%) | 406(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s5_l1) | aurora_1ln_rx_exdes__parameterized1__xdcDup__1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1__xdcDup__1 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3116 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3117 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3118 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3119 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3119 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3120 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3121 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3122 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3123 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3124 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3125 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3126 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3127 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3128 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3129 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3130 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3131 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3133 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3134 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3137 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3140 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3140 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3142 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3146 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3147 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3148 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3150 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3151 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3151 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3155 | 142(0.04%) | 134(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3155 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3156 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3157 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3158 | 93(0.03%) | 93(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3158 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3160 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3171 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2049 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s5_l2 | aurora_1ln_rx_no_comm__xdcDup__4 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s5_l2) | aurora_1ln_rx_no_comm__xdcDup__4 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__4 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD4102 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD4103 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD4104 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD4105 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD4105 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD4106 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD4107 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD4108 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD4109 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD4110 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD4111 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD4112 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD4113 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4114 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4114 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD4115 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD4116 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD4117 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD4118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD4119 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD4120 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD4121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD4122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD4123 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD4124 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD4125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4126 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4126 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD4127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD4128 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD4129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD4131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD4132 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD4133 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD4134 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD4135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD4136 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD4137 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD4137 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD4138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD4140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD4141 | 141(0.04%) | 133(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD4141 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD4142 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD4143 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD4144 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD4144 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD4146 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD4148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD4149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD4151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD4152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD4155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD4156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD4157 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD4159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s5_l3 | aurora_1ln_rx_exdes__parameterized3__xdcDup__1 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s5_l3) | aurora_1ln_rx_exdes__parameterized3__xdcDup__1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__xdcDup__2 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3580 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3581 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3582 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3583 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3583 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3584 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3585 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3586 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3587 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3588 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3589 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3590 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3591 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3592 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3593 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3594 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3595 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3597 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3598 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3601 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3602 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3604 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3604 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3606 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3610 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3611 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3612 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3613 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3614 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3619 | 141(0.04%) | 133(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3619 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3620 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3621 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3622 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3622 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3624 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3635 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2043 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s5_l4 | aurora_1ln_rx_no_comm__xdcDup__5 | 444(0.13%) | 406(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s5_l4) | aurora_1ln_rx_no_comm__xdcDup__5 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__5 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD4160 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD4161 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD4162 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD4163 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD4163 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD4164 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD4165 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD4166 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD4167 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD4168 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD4169 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD4170 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD4171 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4172 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD4173 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD4174 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD4175 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD4176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD4177 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD4178 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD4179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD4180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD4181 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD4182 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4184 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4184 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD4185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD4186 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD4187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD4189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD4190 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD4191 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD4192 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD4193 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD4194 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD4195 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD4195 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD4196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD4197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD4198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD4199 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD4199 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD4200 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD4201 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD4202 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD4202 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD4204 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD4206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD4207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD4209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD4210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD4213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD4214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD4215 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD4217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2039 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s8_l1 | aurora_1ln_rx_exdes__parameterized3__xdcDup__2 | 446(0.13%) | 408(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s8_l1) | aurora_1ln_rx_exdes__parameterized3__xdcDup__2 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__xdcDup__3 | 416(0.12%) | 378(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3638 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3639 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3640 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3641 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3641 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3642 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3643 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3644 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3645 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3646 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3647 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3648 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3649 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3650 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3651 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3652 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3653 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3655 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3656 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3659 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3660 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3662 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3662 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3664 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3668 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3669 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3670 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3672 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3673 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3673 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3677 | 142(0.04%) | 134(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3677 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3678 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3679 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3680 | 93(0.03%) | 93(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3680 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3682 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3685 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3693 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s8_l2 | aurora_1ln_rx_no_comm__xdcDup__6 | 446(0.13%) | 408(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s8_l2) | aurora_1ln_rx_no_comm__xdcDup__6 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__6 | 416(0.12%) | 378(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD4218 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD4219 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD4220 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD4221 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD4221 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD4222 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD4223 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD4224 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD4225 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD4226 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD4227 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD4228 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD4229 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4230 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD4231 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD4232 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD4233 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD4234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD4235 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD4236 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD4237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD4238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD4239 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD4240 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD4241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4242 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4242 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD4243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD4244 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD4245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD4247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD4248 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD4249 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD4250 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD4251 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD4252 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD4253 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD4253 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD4254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD4255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD4256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD4257 | 142(0.04%) | 134(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD4257 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD4258 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD4259 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD4260 | 93(0.03%) | 93(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD4260 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD4262 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD4264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD4265 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD4267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD4268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD4271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD4272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD4273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD4275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2032 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s8_l3 | aurora_1ln_rx_no_comm__xdcDup__7 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s8_l3) | aurora_1ln_rx_no_comm__xdcDup__7 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__7 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD4276 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD4277 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD4278 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD4279 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD4279 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD4280 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD4281 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD4282 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD4283 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD4284 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD4285 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD4286 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD4287 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4288 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4288 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD4289 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD4290 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD4291 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD4292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD4293 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD4294 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD4295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD4296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD4297 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD4298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4300 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4300 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD4301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD4302 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD4305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD4306 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD4307 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD4308 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD4309 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD4310 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD4311 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD4311 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD4312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD4313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD4314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD4315 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD4315 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD4316 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD4317 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD4318 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD4318 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD4320 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD4322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD4323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD4325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD4326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD4329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD4330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD4331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD4333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2029 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s8_l4 | aurora_1ln_rx_no_comm__xdcDup__8 | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s8_l4) | aurora_1ln_rx_no_comm__xdcDup__8 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm__xdcDup__8 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD4334 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD4335 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD4336 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD4337 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD4337 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD4338 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD4339 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD4340 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD4341 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD4342 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD4343 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD4344 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD4345 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4346 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD4346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD4347 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD4348 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD4349 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD4350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD4351 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD4352 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD4353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD4354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD4355 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD4356 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD4357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4358 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD4358 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD4359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD4360 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD4361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD4363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD4364 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD4365 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD4366 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD4367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD4368 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD4369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD4369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD4370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD4371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD4372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD4373 | 141(0.04%) | 133(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD4373 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD4374 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD4375 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD4376 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD4376 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD4378 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD4380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD4381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD4383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD4384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD4387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD4388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD4389 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD4391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC_2025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2026 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s9_l1 | aurora_1ln_rx_exdes__parameterized3__xdcDup__3 | 444(0.13%) | 406(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s9_l1) | aurora_1ln_rx_exdes__parameterized3__xdcDup__3 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__xdcDup__4 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3696 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3697 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3698 | 125(0.04%) | 124(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3699 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3699 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3700 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3701 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3702 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3703 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3704 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3705 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3706 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3707 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3708 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3708 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3709 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3710 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3711 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3713 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3714 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3717 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3718 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3720 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3720 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3722 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3726 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3727 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3728 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3730 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3731 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3731 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3735 | 141(0.04%) | 133(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3735 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3736 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3737 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3738 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3738 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3740 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3743 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2023 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s9_l2 | aurora_1ln_rx_exdes__parameterized1__xdcDup__2 | 442(0.13%) | 404(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s9_l2) | aurora_1ln_rx_exdes__parameterized1__xdcDup__2 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1__xdcDup__2 | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE_2019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3174 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3175 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3176 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3177 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3177 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3178 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3179 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3180 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3181 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3182 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3183 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3184 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3185 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3186 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3186 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3187 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3188 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3189 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3191 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3192 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3195 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3196 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3198 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3198 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3200 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3204 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3205 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3206 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3208 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3209 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3209 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3213 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3213 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3214 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3215 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3216 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3216 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3218 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3229 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2020 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s9_l3 | aurora_1ln_rx_no_comm | 443(0.13%) | 405(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s9_l3) | aurora_1ln_rx_no_comm | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support_no_comm | 413(0.12%) | 375(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support_no_comm | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3870 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3871 | 412(0.12%) | 374(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3872 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3873 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3873 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3874 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3875 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3876 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3877 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3878 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3879 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3880 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3881 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3882 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3882 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3883 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3884 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3885 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3887 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3888 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3891 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3894 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3894 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3896 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3900 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3901 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3902 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3904 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3905 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3905 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3909 | 140(0.04%) | 132(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3909 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3910 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3911 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3912 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3912 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3914 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3917 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3925 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MOD_NC | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC_2017 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_s9_l4 | aurora_1ln_rx_exdes__parameterized1__xdcDup__3 | 444(0.13%) | 406(0.12%) | 0(0.00%) | 38(0.02%) | 722(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_s9_l4) | aurora_1ln_rx_exdes__parameterized1__xdcDup__3 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_1ln_rx_support__parameterized1__xdcDup__3 | 415(0.12%) | 377(0.11%) | 0(0.00%) | 38(0.02%) | 715(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_1ln_rx_support__parameterized1__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_1ln_rx_CLOCK_MODULE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_1ln_rx_i | aurora_1ln_rx_lpm_HD3232 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_1ln_rx_lpm_core_HD3233 | 414(0.12%) | 376(0.11%) | 0(0.00%) | 38(0.02%) | 710(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i | aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE_HD3234 | 124(0.04%) | 123(0.04%) | 0(0.00%) | 1(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_hotplug_i | aurora_1ln_rx_lpm_HOTPLUG_HD3235 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_1ln_rx_lpm_hotplug_i) | aurora_1ln_rx_lpm_HOTPLUG_HD3235 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_16_HD3236 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i | aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE_HD3237 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i | aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE_HD3238 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_sym_dec_4byte_i | aurora_1ln_rx_lpm_SYM_DEC_4BYTE_HD3239 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_global_logic_simplex_i | aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX_HD3240 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3241 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX_HD3242 | 30(0.01%) | 27(0.01%) | 0(0.00%) | 3(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_rx_ll_i | aurora_1ln_rx_lpm_RX_LL_HD3243 | 114(0.03%) | 88(0.03%) | 0(0.00%) | 26(0.01%) | 293(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3244 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 192(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH_HD3244 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_1ln_rx_lpm_OUTPUT_MUX_HD3245 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_1ln_rx_lpm_SIDEBAND_OUTPUT_HD3246 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_1ln_rx_lpm_RX_LL_DEFRAMER_HD3247 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL_HD3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15_HD3249 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_1ln_rx_lpm_LEFT_ALIGN_MUX_HD3250 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL_HD3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_1ln_rx_lpm_STORAGE_CE_CONTROL_HD3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL_HD3253 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL_HD3254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_1ln_rx_lpm_STORAGE_MUX_HD3255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3256 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH_HD3256 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL_HD3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_HD3258 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_1ln_rx_lpm_UFC_OUTPUT_MUX_HD3259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT_HD3261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL_HD3262 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_1ln_rx_lpm_UFC_STORAGE_MUX_HD3263 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL_HD3264 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_1ln_rx_lpm_VALID_DATA_COUNTER_HD3265 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_1ln_rx_lpm_UFC_FILTER_HD3266 | 38(0.01%) | 12(0.01%) | 0(0.00%) | 26(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_1ln_rx_lpm_RESET_LOGIC_HD3267 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_1ln_rx_lpm_RESET_LOGIC_HD3267 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_13_HD3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_14_HD3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_HD3270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_1ln_rx_lpm_GT_WRAPPER_HD3271 | 142(0.04%) | 134(0.04%) | 0(0.00%) | 8(0.01%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_1ln_rx_lpm_GT_WRAPPER_HD3271 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_1ln_rx_lpm_multi_gt_i | aurora_1ln_rx_lpm_multi_gt_HD3272 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_1ln_rx_lpm_i | aurora_1ln_rx_lpm_gt_HD3273 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_1ln_rx_lpm_rx_startup_fsm_HD3274 | 93(0.03%) | 93(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_1ln_rx_lpm_rx_startup_fsm_HD3274 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_3_HD3276 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_5_HD3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_6_HD3279 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_8_HD3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_9_HD3282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_12_HD3285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync__parameterized2_HD3286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_0_HD3287 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_1ln_rx_lpm_cdc_sync_1_HD3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_1ln_rx_SUPPORT_RESET_LOGIC | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_reset | aurora_reset_2016 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | combined_ttc | combined_ttc_rx | 1852(0.53%) | 1526(0.44%) | 0(0.00%) | 326(0.19%) | 3244(0.47%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (combined_ttc) | combined_ttc_rx | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_frame_check | sume_RO_Rx_GT_FRAME_CHECK__2 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_rx2_inst | ila_2_HD1765 | 1570(0.45%) | 1251(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_rx2_inst) | ila_2_HD1765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_2_ila_v6_2_12_ila_HD1766 | 1570(0.45%) | 1251(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_2_ila_v6_2_12_ila_HD1766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_2_ila_v6_2_12_ila_core_HD1767 | 1569(0.45%) | 1250(0.36%) | 0(0.00%) | 319(0.18%) | 2578(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_2_ila_v6_2_12_ila_core_HD1767 | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 255(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_2_ila_v6_2_12_ila_trace_memory_HD1768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_2_blk_mem_gen_v8_4_5_HD1769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_synth_HD1770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[10].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized9_HD1775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized9_HD1776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[11].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized10_HD1777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized10_HD1778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD1781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD1782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD1783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD1784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD1785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD1786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4_HD1787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4_HD1788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5_HD1789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5_HD1790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized6_HD1791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized6_HD1792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[8].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized7_HD1793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized7_HD1794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[9].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized8_HD1795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized8_HD1796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD1797 | 81(0.02%) | 34(0.01%) | 0(0.00%) | 47(0.03%) | 137(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD1797 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_2_ltlib_v1_0_0_cfglut6__parameterized0_HD1798 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_2_ltlib_v1_0_0_cfglut7_HD1799 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_2_ltlib_v1_0_0_cfglut7__1_HD1800 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_2_ila_v6_2_12_ila_cap_addrgen_HD1801 | 66(0.02%) | 29(0.01%) | 0(0.00%) | 37(0.02%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_2_ila_v6_2_12_ila_cap_addrgen_HD1801 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_2_ltlib_v1_0_0_cfglut6__1_HD1802 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD1803 | 33(0.01%) | 20(0.01%) | 0(0.00%) | 13(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD1803 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_2_ltlib_v1_0_0_cfglut4__1_HD1804 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_2_ltlib_v1_0_0_cfglut5__1_HD1805 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_2_ltlib_v1_0_0_cfglut6_HD1806 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_2_ltlib_v1_0_0_match_nodelay__1_HD1807 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD1808 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD1808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD1809 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD1809 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_83_HD1810 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_84_HD1811 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_2_ila_v6_2_12_ila_cap_window_counter_HD1812 | 30(0.01%) | 9(0.01%) | 0(0.00%) | 21(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_2_ila_v6_2_12_ila_cap_window_counter_HD1812 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_2_ltlib_v1_0_0_cfglut4_HD1813 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_2_ltlib_v1_0_0_cfglut5_HD1814 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_2_ltlib_v1_0_0_cfglut5__2_HD1815 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_2_ltlib_v1_0_0_match_nodelay_HD1816 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD1817 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD1817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD1818 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD1818 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1819 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1820 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_2_ltlib_v1_0_0_match_nodelay__2_HD1821 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD1822 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD1822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD1823 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD1823 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_79_HD1824 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_80_HD1825 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_2_ila_v6_2_12_ila_register_HD1826 | 1001(0.29%) | 1000(0.29%) | 0(0.00%) | 1(0.01%) | 1439(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_2_ila_v6_2_12_ila_register_HD1826 | 327(0.09%) | 326(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s_HD1827 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1828 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1829 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1830 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized12_HD1831 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized13_HD1832 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized14_HD1833 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1834 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1835 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1836 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1837 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1838 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1839 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1840 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1841 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1842 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized15_HD1843 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_2_xsdbs_v1_0_2_xsdbs_HD1844 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_2_xsdbs_v1_0_2_reg__parameterized56_HD1845 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_73_HD1846 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_2_xsdbs_v1_0_2_reg__parameterized57_HD1847 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_72_HD1848 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_2_xsdbs_v1_0_2_reg__parameterized58_HD1849 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_71_HD1850 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_2_xsdbs_v1_0_2_reg__parameterized59_HD1851 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_70_HD1852 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_2_xsdbs_v1_0_2_reg__parameterized60_HD1853 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_69_HD1854 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_2_xsdbs_v1_0_2_reg__parameterized61_HD1855 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_68_HD1856 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_2_xsdbs_v1_0_2_reg__parameterized41_HD1857 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_76_HD1858 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_2_xsdbs_v1_0_2_reg__parameterized42_HD1859 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1860 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_2_xsdbs_v1_0_2_reg__parameterized43_HD1861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_75_HD1862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_2_xsdbs_v1_0_2_reg__parameterized62_HD1863 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_67_HD1864 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_2_xsdbs_v1_0_2_reg__parameterized63_HD1865 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_66_HD1866 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_2_xsdbs_v1_0_2_reg__parameterized64_HD1867 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1868 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_2_xsdbs_v1_0_2_reg__parameterized65_HD1869 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_65_HD1870 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_2_xsdbs_v1_0_2_reg__parameterized66_HD1871 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_64_HD1872 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_2_xsdbs_v1_0_2_reg__parameterized67_HD1873 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_63_HD1874 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_2_xsdbs_v1_0_2_reg__parameterized69_HD1875 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_62_HD1876 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_2_xsdbs_v1_0_2_reg__parameterized71_HD1877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_61_HD1878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD1879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD1879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_60_HD1880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_2_xsdbs_v1_0_2_reg__parameterized44_HD1881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_74_HD1882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized16_HD1883 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_2_xsdbs_v1_0_2_reg_stream_HD1884 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_HD1885 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD1886 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD1886 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_HD1887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_2_ila_v6_2_12_ila_reset_ctrl_HD1888 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_2_ila_v6_2_12_ila_reset_ctrl_HD1888 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection_HD1889 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__2_HD1890 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__3_HD1891 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__1_HD1892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer_HD1893 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection__1_HD1894 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_2_ila_v6_2_12_ila_trigger_HD1895 | 268(0.08%) | 107(0.03%) | 0(0.00%) | 161(0.09%) | 475(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_2_ila_v6_2_12_ila_trigger_HD1895 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_2_ltlib_v1_0_0_match_HD1896 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_2_ltlib_v1_0_0_match_HD1896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_HD1897 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_HD1897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA_HD1898 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA_HD1898 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_58_HD1899 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_59_HD1900 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_2_ila_v6_2_12_ila_trig_match_HD1901 | 258(0.07%) | 106(0.03%) | 0(0.00%) | 152(0.09%) | 456(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_2_ila_v6_2_12_ila_trig_match_HD1901 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD1902 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD1902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD1903 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD1903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD1904 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD1904 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_54_HD1905 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_55_HD1906 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_56_HD1907 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_57_HD1908 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD1909 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD1909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD1910 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD1910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD1911 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD1911 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_13_HD1912 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_14_HD1913 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_15_HD1914 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD1915 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_2_ltlib_v1_0_0_match__parameterized0_HD1916 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0_HD1916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD1917 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD1917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD1918 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD1918 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_HD1919 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_8_HD1920 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_9_HD1921 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD1922 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD1923 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD1923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD1924 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD1924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD1925 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD1925 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD1926 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD1927 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD1927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD1928 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD1928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD1929 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD1929 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD1930 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_2_ltlib_v1_0_0_match__parameterized3_HD1931 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3_HD1931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD1932 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD1932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD1933 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD1933 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD1934 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_2_ltlib_v1_0_0_match__parameterized1_HD1935 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1_HD1935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD1936 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD1936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD1937 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD1937 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1938 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD1939 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD1939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD1940 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD1940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD1941 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD1941 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_51_HD1942 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD1943 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD1943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD1944 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD1944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD1945 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD1945 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD1946 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD1947 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD1947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD1948 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD1948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD1949 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD1949 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_42_HD1950 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_43_HD1951 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_44_HD1952 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_45_HD1953 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD1954 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD1954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD1955 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD1955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD1956 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD1956 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_36_HD1957 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_37_HD1958 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_38_HD1959 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_39_HD1960 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD1961 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD1961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD1962 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD1962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD1963 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD1963 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_30_HD1964 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_31_HD1965 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_32_HD1966 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1967 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_2_ltlib_v1_0_0_match__parameterized2_HD1968 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_2_ltlib_v1_0_0_match__parameterized2_HD1968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD1969 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD1969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD1970 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD1970 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD1971 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD1972 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD1972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD1973 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD1973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1974 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1974 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD1975 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD1976 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD1976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD1977 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD1977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1978 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1978 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD1979 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD1980 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD1980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD1981 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD1981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD1982 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD1982 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD1983 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_2_ltlib_v1_0_0_generic_memrd_HD1984 | 102(0.03%) | 100(0.03%) | 0(0.00%) | 2(0.01%) | 238(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_regs | rx_registers__2 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sume_RO_Rx_support_i | sume_RO_Rx_support | 104(0.03%) | 97(0.03%) | 0(0.00%) | 7(0.01%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (sume_RO_Rx_support_i) | sume_RO_Rx_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cttc_Rx_init_i | MGT_combined_ttc_rx | 104(0.03%) | 97(0.03%) | 0(0.00%) | 7(0.01%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | MGT_combined_ttc_rx_init | 104(0.03%) | 97(0.03%) | 0(0.00%) | 7(0.01%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | MGT_combined_ttc_rx_init | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_combined_ttc_rx_i | MGT_combined_ttc_rx_multi_gt | 9(0.01%) | 2(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | MGT_combined_ttc_rx_cpll_railing | 9(0.01%) | 2(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_MGT_combined_ttc_rx_i | MGT_combined_ttc_rx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | MGT_combined_ttc_rx_RX_STARTUP_FSM | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | MGT_combined_ttc_rx_RX_STARTUP_FSM | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 91(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_combined_ttc_rx_sync_block | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_combined_ttc_rx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_combined_ttc_rx_sync_block_1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_combined_ttc_rx_sync_block_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_combined_ttc_rx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_combined_ttc_rx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_combined_ttc_rx_sync_block_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | sume_RO_Rx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_ttc_HD414 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_ttc_HD414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD415 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD416 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD417 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD418 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD418 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD419 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD420 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pwer_on_rst | pwr_on_timer | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | readout_ctrl | rod_RO_Tx_exdes | 802(0.23%) | 728(0.21%) | 0(0.00%) | 74(0.04%) | 1394(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (readout_ctrl) | rod_RO_Tx_exdes | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_tx0_inst | ila_1 | 628(0.18%) | 561(0.16%) | 0(0.00%) | 67(0.04%) | 1038(0.15%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_tx0_inst) | ila_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_1_ila_v6_2_12_ila | 628(0.18%) | 561(0.16%) | 0(0.00%) | 67(0.04%) | 1038(0.15%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_1_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_1_ila_v6_2_12_ila_core | 627(0.18%) | 560(0.16%) | 0(0.00%) | 67(0.04%) | 1032(0.15%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_1_ila_v6_2_12_ila_core | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_1_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_1_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_1_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | u_ila_cap_ctrl | ila_1_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_1_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_1_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_1_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_1_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_1_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_1_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_1_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_1_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_1_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_1_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_1_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_1_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_1_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_27 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized1_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_1_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_1_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_1_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_1_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_1_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_1_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA__parameterized0 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_1_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_22 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_23 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized0_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized1_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_1_ila_v6_2_12_ila_register | 495(0.14%) | 494(0.14%) | 0(0.00%) | 1(0.01%) | 819(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_1_ila_v6_2_12_ila_register | 245(0.07%) | 244(0.07%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_1_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_1_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_1_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_1_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_1_xsdbs_v1_0_2_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_1_xsdbs_v1_0_2_reg__parameterized29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_1_xsdbs_v1_0_2_reg__parameterized30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_1_xsdbs_v1_0_2_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_1_xsdbs_v1_0_2_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_1_xsdbs_v1_0_2_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized1_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_1_xsdbs_v1_0_2_reg__parameterized13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_1_xsdbs_v1_0_2_reg__parameterized14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_1_xsdbs_v1_0_2_reg__parameterized15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_1_xsdbs_v1_0_2_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized1_12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_1_xsdbs_v1_0_2_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_1_xsdbs_v1_0_2_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_1_xsdbs_v1_0_2_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_10 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_1_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_9 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_1_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_8 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_1_xsdbs_v1_0_2_reg__parameterized41 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_1_xsdbs_v1_0_2_reg__parameterized43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_1_xsdbs_v1_0_2_reg__parameterized46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_1_xsdbs_v1_0_2_reg__parameterized46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_1_xsdbs_v1_0_2_reg__parameterized16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_1_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_1_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_1_xsdbs_v1_0_2_reg_stream__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_1_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_1_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_1_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_1_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_1_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_1_ila_v6_2_12_ila_trigger | 17(0.01%) | 2(0.01%) | 0(0.00%) | 15(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_1_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_1_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_1_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_1_ila_v6_2_12_ila_trig_match | 11(0.01%) | 1(0.01%) | 0(0.00%) | 10(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_1_ila_v6_2_12_ila_trig_match | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_1_ltlib_v1_0_0_match__parameterized0__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_1_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_1_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_1_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_1_ltlib_v1_0_0_generic_memrd | 26(0.01%) | 24(0.01%) | 0(0.00%) | 2(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_RO_Tx_support_i | rod_RO_Tx_support | 71(0.02%) | 64(0.02%) | 0(0.00%) | 7(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rod_RO_Tx_support_i) | rod_RO_Tx_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | rod_RO_Tx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_RO_Tx_init_i | rod_RO_Tx | 71(0.02%) | 64(0.02%) | 0(0.00%) | 7(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | rod_RO_Tx_init | 71(0.02%) | 64(0.02%) | 0(0.00%) | 7(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | rod_RO_Tx_TX_STARTUP_FSM | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | rod_RO_Tx_TX_STARTUP_FSM | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | rod_RO_Tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | rod_RO_Tx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | rod_RO_Tx_sync_block_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | rod_RO_Tx_sync_block_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | rod_RO_Tx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | rod_RO_Tx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_RO_Tx_i | rod_RO_Tx_multi_gt | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | rod_RO_Tx_cpll_railing | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rod_RO_Tx_i | rod_RO_Tx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_0 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_0_vio_v3_0_22_vio | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_0_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_0_vio_v3_0_22_decoder | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_0_vio_v3_0_22_probe_in_one | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_0_vio_v3_0_22_probe_out_all | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_0_vio_v3_0_22_probe_out_all | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_0_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_0_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s12_l1 | dwidth_convert | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s12_l2 | dwidth_convert_HD2966 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2967 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2968 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s12_l3 | dwidth_convert_HD2969 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2970 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2971 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s12_l4 | dwidth_convert_HD2972 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2973 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2974 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s13_l1 | dwidth_convert_HD2975 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2976 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2977 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s13_l2 | dwidth_convert_HD2978 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2979 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2980 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s13_l3 | dwidth_convert_HD2981 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2982 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2983 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s13_l4 | dwidth_convert_HD2984 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2985 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2986 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s4_l1 | dwidth_convert_HD2987 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2988 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2989 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s4_l2 | dwidth_convert_HD2990 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2991 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2992 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s4_l3 | dwidth_convert_HD2993 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2994 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2995 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s4_l4 | dwidth_convert_HD2996 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2997 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD2998 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s5_l1 | dwidth_convert_HD2999 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3000 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3001 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s5_l2 | dwidth_convert_HD3002 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3003 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3004 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s5_l3 | dwidth_convert_HD3005 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3006 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3007 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s5_l4 | dwidth_convert_HD3008 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3009 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3010 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s8_l1 | dwidth_convert_HD3011 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3012 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3013 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s8_l2 | dwidth_convert_HD3014 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3015 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3016 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s8_l3 | dwidth_convert_HD3017 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3018 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3019 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s8_l4 | dwidth_convert_HD3020 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3021 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3022 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s9_l1 | dwidth_convert_HD3023 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3024 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3025 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s9_l2 | dwidth_convert_HD3026 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3027 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3028 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s9_l3 | dwidth_convert_HD3029 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3030 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3031 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | width_conver_s9_l4 | dwidth_convert_HD3032 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3033 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | dwidth_convert_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_upsizer_conversion.axisc_upsizer_0 | dwidth_convert_axis_dwidth_converter_v1_1_25_axisc_upsizer_HD3034 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_hub | dbg_hub | 1119(0.32%) | 1095(0.32%) | 24(0.01%) | 0(0.00%) | 1396(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dbg_hub) | dbg_hub | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dbg_hub_xsdbm_v3_0_0_xsdbm | 1119(0.32%) | 1095(0.32%) | 24(0.01%) | 0(0.00%) | 1396(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BSCANID.u_xsdbm_id | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 1119(0.32%) | 1095(0.32%) | 24(0.01%) | 0(0.00%) | 1396(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (BSCANID.u_xsdbm_id) | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.UUT_MASTER | dbg_hub_xsdbm_v3_0_0_icon2xsdb | 942(0.27%) | 918(0.27%) | 24(0.01%) | 0(0.00%) | 1209(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_ICON_INTERFACE | dbg_hub_xsdbm_v3_0_0_if | 419(0.12%) | 395(0.11%) | 24(0.01%) | 0(0.00%) | 804(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_ICON_INTERFACE) | dbg_hub_xsdbm_v3_0_0_if | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD1 | dbg_hub_xsdbm_v3_0_0_ctl_reg | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD2 | dbg_hub_xsdbm_v3_0_0_stat_reg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD3 | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized0 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD4 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized0 | 148(0.04%) | 148(0.04%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD5 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_RD | dbg_hub_xsdbm_v3_0_0_rdreg | 66(0.02%) | 54(0.02%) | 12(0.01%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_RD) | dbg_hub_xsdbm_v3_0_0_rdreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_FIFO | dbg_hub_xsdbm_v3_0_0_rdfifo | 64(0.02%) | 52(0.02%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_RD_FIFO) | dbg_hub_xsdbm_v3_0_0_rdfifo | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst) | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs_6 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs_6 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | dbg_hub_rd_fwft | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr_17 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as_13 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory__parameterized0 | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | dbg_hub_memory__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem_12 | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo_7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_WR | dbg_hub_xsdbm_v3_0_0_wrreg | 45(0.01%) | 33(0.01%) | 12(0.01%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_WR) | dbg_hub_xsdbm_v3_0_0_wrreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WR_FIFO | dbg_hub_xsdbm_v3_0_0_wrfifo | 43(0.01%) | 31(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_WR_FIFO) | dbg_hub_xsdbm_v3_0_0_wrfifo | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst | dbg_hub_fifo_generator_v13_1_4 | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst) | dbg_hub_fifo_generator_v13_1_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_CTL | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_STAT | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STATIC_STATUS | dbg_hub_xsdbm_v3_0_0_if_static_status | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_ADDRESS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_addr_ctl | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BURST_WD_LEN_CONTROLLER | dbg_hub_xsdbm_v3_0_0_burst_wdlen_ctl | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_bus_ctl | 198(0.06%) | 198(0.06%) | 0(0.00%) | 0(0.00%) | 349(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_CONTROLLER) | dbg_hub_xsdbm_v3_0_0_bus_ctl | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 338(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_ABORT_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_REQ_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TIMER | dbg_hub_xsdbm_v3_0_0_bus_ctl_cnt | 182(0.05%) | 182(0.05%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_MSTR2SL_PORT_IFACE | dbg_hub_xsdbm_v3_0_0_bus_mstr2sl_if | 286(0.08%) | 286(0.08%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_MSTR2SL_PORT_IFACE) | dbg_hub_xsdbm_v3_0_0_bus_mstr2sl_if | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_DIN_BUS_MUX | dbg_hub_ltlib_v1_0_0_generic_mux | 273(0.08%) | 273(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.U_ICON | dbg_hub_xsdbm_v3_0_0_icon | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (CORE_XSDB.U_ICON) | dbg_hub_xsdbm_v3_0_0_icon | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD | dbg_hub_xsdbm_v3_0_0_cmd_decode | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STAT | dbg_hub_xsdbm_v3_0_0_stat | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SYNC | dbg_hub_xsdbm_v3_0_0_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_inst | dbg_hub_ltlib_v1_0_0_bscan | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_switch | dbg_hub_xsdbm_v3_0_0_bscan_switch | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 125(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_builder | packet_processor | 73759(21.29%) | 67395(19.46%) | 1328(0.76%) | 5036(2.89%) | 127085(18.34%) | 530(44.92%) | 8(0.34%) | 0(0.00%) | | (event_builder) | packet_processor | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CTTC_receiver | combined_ttc_no_mgt__xdcDup__1 | 1744(0.50%) | 1425(0.41%) | 0(0.00%) | 319(0.18%) | 3092(0.45%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (CTTC_receiver) | combined_ttc_no_mgt__xdcDup__1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_frame_check | sume_RO_Rx_GT_FRAME_CHECK__3 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_rx2_inst | ila_2_HD1985 | 1571(0.45%) | 1252(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_rx2_inst) | ila_2_HD1985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_2_ila_v6_2_12_ila_HD1986 | 1571(0.45%) | 1252(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_2_ila_v6_2_12_ila_HD1986 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_2_ila_v6_2_12_ila_core_HD1987 | 1570(0.45%) | 1251(0.36%) | 0(0.00%) | 319(0.18%) | 2578(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_2_ila_v6_2_12_ila_core_HD1987 | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 255(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_2_ila_v6_2_12_ila_trace_memory_HD1988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_2_blk_mem_gen_v8_4_5_HD1989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_synth_HD1990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[10].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized9_HD1995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized9_HD1996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[11].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized10_HD1997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized10_HD1998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD2000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD2001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD2002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD2003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD2004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD2005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD2006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4_HD2007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4_HD2008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5_HD2009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5_HD2010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized6_HD2011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized6_HD2012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[8].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized7_HD2013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized7_HD2014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[9].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized8_HD2015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized8_HD2016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD2017 | 81(0.02%) | 34(0.01%) | 0(0.00%) | 47(0.03%) | 137(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD2017 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_2_ltlib_v1_0_0_cfglut6__parameterized0_HD2018 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_2_ltlib_v1_0_0_cfglut7_HD2019 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_2_ltlib_v1_0_0_cfglut7__1_HD2020 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_2_ila_v6_2_12_ila_cap_addrgen_HD2021 | 66(0.02%) | 29(0.01%) | 0(0.00%) | 37(0.02%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_2_ila_v6_2_12_ila_cap_addrgen_HD2021 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_2_ltlib_v1_0_0_cfglut6__1_HD2022 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD2023 | 33(0.01%) | 20(0.01%) | 0(0.00%) | 13(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD2023 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_2_ltlib_v1_0_0_cfglut4__1_HD2024 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_2_ltlib_v1_0_0_cfglut5__1_HD2025 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_2_ltlib_v1_0_0_cfglut6_HD2026 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_2_ltlib_v1_0_0_match_nodelay__1_HD2027 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD2028 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD2028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD2029 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD2029 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_83_HD2030 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_84_HD2031 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_2_ila_v6_2_12_ila_cap_window_counter_HD2032 | 30(0.01%) | 9(0.01%) | 0(0.00%) | 21(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_2_ila_v6_2_12_ila_cap_window_counter_HD2032 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_2_ltlib_v1_0_0_cfglut4_HD2033 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_2_ltlib_v1_0_0_cfglut5_HD2034 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_2_ltlib_v1_0_0_cfglut5__2_HD2035 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_2_ltlib_v1_0_0_match_nodelay_HD2036 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD2037 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD2037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD2038 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD2038 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD2039 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD2040 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_2_ltlib_v1_0_0_match_nodelay__2_HD2041 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD2042 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD2042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD2043 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD2043 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_79_HD2044 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_80_HD2045 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_2_ila_v6_2_12_ila_register_HD2046 | 1002(0.29%) | 1001(0.29%) | 0(0.00%) | 1(0.01%) | 1439(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_2_ila_v6_2_12_ila_register_HD2046 | 328(0.09%) | 327(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s_HD2047 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized9_HD2048 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized10_HD2049 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized11_HD2050 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized12_HD2051 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized13_HD2052 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized14_HD2053 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized0_HD2054 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized1_HD2055 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized2_HD2056 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized3_HD2057 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized4_HD2058 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized5_HD2059 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized6_HD2060 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized7_HD2061 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized8_HD2062 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized15_HD2063 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_2_xsdbs_v1_0_2_xsdbs_HD2064 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_2_xsdbs_v1_0_2_reg__parameterized56_HD2065 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_73_HD2066 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_2_xsdbs_v1_0_2_reg__parameterized57_HD2067 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_72_HD2068 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_2_xsdbs_v1_0_2_reg__parameterized58_HD2069 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_71_HD2070 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_2_xsdbs_v1_0_2_reg__parameterized59_HD2071 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_70_HD2072 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_2_xsdbs_v1_0_2_reg__parameterized60_HD2073 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_69_HD2074 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_2_xsdbs_v1_0_2_reg__parameterized61_HD2075 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_68_HD2076 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_2_xsdbs_v1_0_2_reg__parameterized41_HD2077 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_76_HD2078 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_2_xsdbs_v1_0_2_reg__parameterized42_HD2079 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized0_HD2080 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_2_xsdbs_v1_0_2_reg__parameterized43_HD2081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_75_HD2082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_2_xsdbs_v1_0_2_reg__parameterized62_HD2083 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_67_HD2084 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_2_xsdbs_v1_0_2_reg__parameterized63_HD2085 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_66_HD2086 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_2_xsdbs_v1_0_2_reg__parameterized64_HD2087 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_HD2088 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_2_xsdbs_v1_0_2_reg__parameterized65_HD2089 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_65_HD2090 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_2_xsdbs_v1_0_2_reg__parameterized66_HD2091 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_64_HD2092 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_2_xsdbs_v1_0_2_reg__parameterized67_HD2093 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_63_HD2094 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_2_xsdbs_v1_0_2_reg__parameterized69_HD2095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_62_HD2096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_2_xsdbs_v1_0_2_reg__parameterized71_HD2097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_61_HD2098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD2099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD2099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_60_HD2100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_2_xsdbs_v1_0_2_reg__parameterized44_HD2101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_74_HD2102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized16_HD2103 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_2_xsdbs_v1_0_2_reg_stream_HD2104 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_HD2105 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD2106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD2106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_HD2107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_2_ila_v6_2_12_ila_reset_ctrl_HD2108 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_2_ila_v6_2_12_ila_reset_ctrl_HD2108 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection_HD2109 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__2_HD2110 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__3_HD2111 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__1_HD2112 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer_HD2113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection__1_HD2114 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_2_ila_v6_2_12_ila_trigger_HD2115 | 268(0.08%) | 107(0.03%) | 0(0.00%) | 161(0.09%) | 475(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_2_ila_v6_2_12_ila_trigger_HD2115 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_2_ltlib_v1_0_0_match_HD2116 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_2_ltlib_v1_0_0_match_HD2116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_HD2117 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_HD2117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA_HD2118 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA_HD2118 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_58_HD2119 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_59_HD2120 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_2_ila_v6_2_12_ila_trig_match_HD2121 | 258(0.07%) | 106(0.03%) | 0(0.00%) | 152(0.09%) | 456(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_2_ila_v6_2_12_ila_trig_match_HD2121 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD2122 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD2122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD2123 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD2123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD2124 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD2124 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_54_HD2125 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_55_HD2126 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_56_HD2127 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_57_HD2128 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD2129 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD2129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD2130 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD2130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD2131 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD2131 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_13_HD2132 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_14_HD2133 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_15_HD2134 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD2135 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_2_ltlib_v1_0_0_match__parameterized0_HD2136 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0_HD2136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD2137 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD2137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD2138 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD2138 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_HD2139 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_8_HD2140 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_9_HD2141 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD2142 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD2143 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD2143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD2144 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD2144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD2145 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD2145 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD2146 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD2147 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD2147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD2148 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD2148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD2149 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD2149 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD2150 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_2_ltlib_v1_0_0_match__parameterized3_HD2151 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3_HD2151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD2152 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD2152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD2153 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD2153 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD2154 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_2_ltlib_v1_0_0_match__parameterized1_HD2155 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1_HD2155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD2156 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD2156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD2157 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD2157 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD2158 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD2159 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD2159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD2160 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD2160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD2161 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD2161 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_51_HD2162 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD2163 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD2163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD2164 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD2164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD2165 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD2165 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD2166 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD2167 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD2167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD2168 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD2168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD2169 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD2169 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_42_HD2170 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_43_HD2171 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_44_HD2172 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_45_HD2173 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD2174 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD2174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD2175 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD2175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD2176 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD2176 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_36_HD2177 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_37_HD2178 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_38_HD2179 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_39_HD2180 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD2181 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD2181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD2182 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD2182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD2183 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD2183 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_30_HD2184 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_31_HD2185 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_32_HD2186 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD2187 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_2_ltlib_v1_0_0_match__parameterized2_HD2188 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_2_ltlib_v1_0_0_match__parameterized2_HD2188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD2189 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD2189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD2190 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD2190 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD2191 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD2192 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD2192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD2193 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD2193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2194 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2194 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD2195 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD2196 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD2196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD2197 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD2197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2198 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2198 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD2199 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD2200 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD2200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD2201 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD2201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD2202 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD2202 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD2203 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_2_ltlib_v1_0_0_generic_memrd_HD2204 | 102(0.03%) | 100(0.03%) | 0(0.00%) | 2(0.01%) | 238(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_regs | rx_registers__3 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_ttc_HD421 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_ttc_HD421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD422 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD423 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD424 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD425 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD425 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD426 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD427 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | alt_cttc_crc | cttc_crc_test | 846(0.24%) | 739(0.21%) | 0(0.00%) | 107(0.06%) | 1321(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (alt_cttc_crc) | cttc_crc_test | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_check_ila | ila_CRC | 779(0.22%) | 672(0.19%) | 0(0.00%) | 107(0.06%) | 1312(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (crc_check_ila) | ila_CRC | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_CRC_ila_v6_2_12_ila | 779(0.22%) | 672(0.19%) | 0(0.00%) | 107(0.06%) | 1312(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_CRC_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_CRC_ila_v6_2_12_ila_core | 778(0.22%) | 671(0.19%) | 0(0.00%) | 107(0.06%) | 1306(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_CRC_ila_v6_2_12_ila_core | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_CRC_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_CRC_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_CRC_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_CRC_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_CRC_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_CRC_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_CRC_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_CRC_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_CRC_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_CRC_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_CRC_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_CRC_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_CRC_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_CRC_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_CRC_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_CRC_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_CRC_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_31 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_32 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized1_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized2_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_CRC_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_CRC_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_CRC_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_CRC_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_CRC_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_CRC_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_CRC_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_27 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_28 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized1_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized2_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_CRC_ila_v6_2_12_ila_register | 569(0.16%) | 568(0.16%) | 0(0.00%) | 1(0.01%) | 920(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_CRC_ila_v6_2_12_ila_register | 263(0.08%) | 262(0.08%) | 0(0.00%) | 1(0.01%) | 159(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_CRC_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_CRC_xsdbs_v1_0_2_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_23 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_CRC_xsdbs_v1_0_2_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_22 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_CRC_xsdbs_v1_0_2_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_CRC_xsdbs_v1_0_2_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_20 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_CRC_xsdbs_v1_0_2_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_19 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_CRC_xsdbs_v1_0_2_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized1_18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_CRC_xsdbs_v1_0_2_reg__parameterized17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_CRC_xsdbs_v1_0_2_reg__parameterized18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_CRC_xsdbs_v1_0_2_reg__parameterized19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_CRC_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized1_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_CRC_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_CRC_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_CRC_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_CRC_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_CRC_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_CRC_xsdbs_v1_0_2_reg__parameterized45 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_CRC_xsdbs_v1_0_2_reg__parameterized47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_CRC_xsdbs_v1_0_2_reg__parameterized50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_CRC_xsdbs_v1_0_2_reg__parameterized50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_CRC_xsdbs_v1_0_2_reg__parameterized20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_CRC_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_CRC_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_CRC_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_CRC_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_CRC_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_CRC_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_CRC_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_CRC_ila_v6_2_12_ila_trigger | 56(0.02%) | 19(0.01%) | 0(0.00%) | 37(0.02%) | 87(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_CRC_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_CRC_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_CRC_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA_8 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_CRC_ila_v6_2_12_ila_trig_match | 50(0.01%) | 18(0.01%) | 0(0.00%) | 32(0.02%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_CRC_ila_v6_2_12_ila_trig_match | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized2__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_CRC_ltlib_v1_0_0_generic_memrd | 46(0.01%) | 44(0.01%) | 0(0.00%) | 2(0.01%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cttc_crc | osum_crc9d32__11 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bkpln_rst_pulse_stretcher | pulse_stretch__parameterized1 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_0 | bulk_processor__xdcDup__1 | 1119(0.32%) | 1119(0.32%) | 0(0.00%) | 0(0.00%) | 1415(0.20%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (bulk_0) | bulk_processor__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | bulk_controller_1952 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF__parameterized1_2004 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | bulk_data_fifo_HD4394 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | bulk_data_fifo_axis_data_fifo_v2_0_8_top_HD4395 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | bulk_data_fifo_xpm_fifo_axis_HD4396 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | bulk_data_fifo_xpm_fifo_axis_HD4396 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | bulk_data_fifo_xpm_cdc_sync_rst_HD4397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | bulk_data_fifo_xpm_fifo_base_HD4398 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | bulk_data_fifo_xpm_fifo_base_HD4398 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized1_HD4399 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | bulk_data_fifo_xpm_memory_base_HD4400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_HD4401 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_HD4402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | bulk_data_fifo_xpm_fifo_reg_bit_HD4403 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_0_HD4404 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_1_HD4405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | bulk_data_fifo_xpm_counter_updn__parameterized0_HD4406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | bulk_data_fifo_xpm_fifo_rst_HD4407 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_2005 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | bulk_channel_mux_1953 | 231(0.07%) | 231(0.07%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_regs | bulk_proc_regs_1954 | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1166(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (status_regs) | bulk_proc_regs_1954 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_counter | threshold_counter_1955 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_flag | threshold_counter__parameterized0_1956 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_counter | threshold_counter_1957 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_flag | threshold_counter__parameterized0_1958 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Bulk_proc_status_reg | ipbus_syncreg_v_1959 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.Bulk_proc_status_reg) | ipbus_syncreg_v_1959 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2003 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_control_reg | ipbus_reg_v_1960 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_reset_reg | ipbus_reg_v_1961 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Full_mode_control_reg | ipbus_reg_v_1962 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_busy_Count_reg | ipbus_syncreg_v_1963 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_busy_Count_reg) | ipbus_syncreg_v_1963 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2002 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_fifo_status_reg | ipbus_syncreg_v_1964 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_fifo_status_reg) | ipbus_syncreg_v_1964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2001 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_xoff_Count_reg | ipbus_syncreg_v_1965 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_xoff_Count_reg) | ipbus_syncreg_v_1965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2000 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_control_reg | ipbus_reg_v_1966 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_fifo_resets_reg | ipbus_reg_v_1967 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_thresholds_reg | ipbus_reg_v_1968 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_1969 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_1969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1999 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_watermark | watermark_1970 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.flx_bp_time_reg | ipbus_syncreg_v_1971 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.flx_bp_time_reg) | ipbus_syncreg_v_1971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1998 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_L1id_reg | ipbus_syncreg_v_1972 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fm_L1id_reg) | ipbus_syncreg_v_1972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1997 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_fifo_watermark | watermark_1973 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.full_mode_status_reg | ipbus_syncreg_v_1974 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.full_mode_status_reg) | ipbus_syncreg_v_1974 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1996 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_1975 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_1975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1995 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_1976 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_1976 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1994 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_watermark | watermark_1977 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_capture | pkt_capture_regs__parameterized1_1978 | 199(0.06%) | 199(0.06%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (packet_capture) | pkt_capture_regs__parameterized1_1978 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_1979 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_1980 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_1980 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1993 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_1981 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_1981 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1992 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_1982 | 104(0.03%) | 104(0.03%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_1982 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1991 | 103(0.03%) | 103(0.03%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_1983 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_1983 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1990 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_1984 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_1984 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1989 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_1985 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_1985 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1988 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_1986 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_1986 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1987 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized1__29 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_1 | bulk_processor__xdcDup__2 | 1080(0.31%) | 1080(0.31%) | 0(0.00%) | 0(0.00%) | 1414(0.20%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (bulk_1) | bulk_processor__xdcDup__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | bulk_controller_1898 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF__parameterized1_1950 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | bulk_data_fifo_HD4408 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | bulk_data_fifo_axis_data_fifo_v2_0_8_top_HD4409 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | bulk_data_fifo_xpm_fifo_axis_HD4410 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | bulk_data_fifo_xpm_fifo_axis_HD4410 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | bulk_data_fifo_xpm_cdc_sync_rst_HD4411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | bulk_data_fifo_xpm_fifo_base_HD4412 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | bulk_data_fifo_xpm_fifo_base_HD4412 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized1_HD4413 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | bulk_data_fifo_xpm_memory_base_HD4414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_HD4415 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_HD4416 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | bulk_data_fifo_xpm_fifo_reg_bit_HD4417 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_0_HD4418 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_1_HD4419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | bulk_data_fifo_xpm_counter_updn__parameterized0_HD4420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | bulk_data_fifo_xpm_fifo_rst_HD4421 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9__5 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9__5 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_1951 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | bulk_channel_mux_1899 | 234(0.07%) | 234(0.07%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_regs | bulk_proc_regs_1900 | 576(0.17%) | 576(0.17%) | 0(0.00%) | 0(0.00%) | 1165(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (status_regs) | bulk_proc_regs_1900 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_counter | threshold_counter_1901 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_flag | threshold_counter__parameterized0_1902 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_counter | threshold_counter_1903 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_flag | threshold_counter__parameterized0_1904 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Bulk_proc_status_reg | ipbus_syncreg_v_1905 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.Bulk_proc_status_reg) | ipbus_syncreg_v_1905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1949 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_control_reg | ipbus_reg_v_1906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_reset_reg | ipbus_reg_v_1907 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Full_mode_control_reg | ipbus_reg_v_1908 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_busy_Count_reg | ipbus_syncreg_v_1909 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_busy_Count_reg) | ipbus_syncreg_v_1909 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1948 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_fifo_status_reg | ipbus_syncreg_v_1910 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_fifo_status_reg) | ipbus_syncreg_v_1910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1947 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_xoff_Count_reg | ipbus_syncreg_v_1911 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_xoff_Count_reg) | ipbus_syncreg_v_1911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1946 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_control_reg | ipbus_reg_v_1912 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_fifo_resets_reg | ipbus_reg_v_1913 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_thresholds_reg | ipbus_reg_v_1914 | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_1915 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_1915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1945 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_watermark | watermark_1916 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.flx_bp_time_reg | ipbus_syncreg_v_1917 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.flx_bp_time_reg) | ipbus_syncreg_v_1917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1944 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_L1id_reg | ipbus_syncreg_v_1918 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fm_L1id_reg) | ipbus_syncreg_v_1918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1943 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_fifo_watermark | watermark_1919 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.full_mode_status_reg | ipbus_syncreg_v_1920 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.full_mode_status_reg) | ipbus_syncreg_v_1920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1942 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_1921 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_1921 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1941 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_1922 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_1922 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1940 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_watermark | watermark_1923 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_capture | pkt_capture_regs__parameterized1_1924 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (packet_capture) | pkt_capture_regs__parameterized1_1924 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_1925 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_1926 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_1926 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1939 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_1927 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_1927 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1938 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_1928 | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_1928 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1937 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_1929 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_1929 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1936 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_1930 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_1930 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1935 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_1931 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_1931 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1934 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_1932 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_1932 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1933 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized1__28 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_2 | bulk_processor | 1077(0.31%) | 1077(0.31%) | 0(0.00%) | 0(0.00%) | 1415(0.20%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (bulk_2) | bulk_processor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | bulk_controller | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF__parameterized1 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | bulk_data_fifo | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | bulk_data_fifo_axis_data_fifo_v2_0_8_top | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | bulk_data_fifo_xpm_fifo_axis | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | bulk_data_fifo_xpm_fifo_axis | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | bulk_data_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | bulk_data_fifo_xpm_fifo_base | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | bulk_data_fifo_xpm_fifo_base | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | bulk_data_fifo_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | bulk_data_fifo_xpm_fifo_reg_bit | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | bulk_data_fifo_xpm_counter_updn__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | bulk_data_fifo_xpm_fifo_rst | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9__4 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9__4 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_1897 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | bulk_channel_mux | 234(0.07%) | 234(0.07%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_regs | bulk_proc_regs | 575(0.17%) | 575(0.17%) | 0(0.00%) | 0(0.00%) | 1166(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (status_regs) | bulk_proc_regs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_counter | threshold_counter_1849 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_flag | threshold_counter__parameterized0_1850 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_counter | threshold_counter_1851 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_flag | threshold_counter__parameterized0_1852 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Bulk_proc_status_reg | ipbus_syncreg_v_1853 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.Bulk_proc_status_reg) | ipbus_syncreg_v_1853 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1896 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_control_reg | ipbus_reg_v_1854 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_reset_reg | ipbus_reg_v_1855 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Full_mode_control_reg | ipbus_reg_v_1856 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_busy_Count_reg | ipbus_syncreg_v_1857 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_busy_Count_reg) | ipbus_syncreg_v_1857 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1895 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_fifo_status_reg | ipbus_syncreg_v_1858 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_fifo_status_reg) | ipbus_syncreg_v_1858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1894 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_xoff_Count_reg | ipbus_syncreg_v_1859 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_xoff_Count_reg) | ipbus_syncreg_v_1859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1893 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_control_reg | ipbus_reg_v_1860 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_fifo_resets_reg | ipbus_reg_v_1861 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_thresholds_reg | ipbus_reg_v_1862 | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_1863 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_1863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1892 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_watermark | watermark_1864 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.flx_bp_time_reg | ipbus_syncreg_v_1865 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.flx_bp_time_reg) | ipbus_syncreg_v_1865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1891 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_L1id_reg | ipbus_syncreg_v_1866 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fm_L1id_reg) | ipbus_syncreg_v_1866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1890 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_fifo_watermark | watermark_1867 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.full_mode_status_reg | ipbus_syncreg_v_1868 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.full_mode_status_reg) | ipbus_syncreg_v_1868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1889 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_1869 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_1869 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1888 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_1870 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_1870 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1887 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_watermark | watermark_1871 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_capture | pkt_capture_regs__parameterized1 | 167(0.05%) | 167(0.05%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (packet_capture) | pkt_capture_regs__parameterized1 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_1872 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_1873 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_1873 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1886 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_1874 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_1874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1885 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_1875 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_1875 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1884 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_1876 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_1876 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1883 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_1877 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_1877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1882 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_1878 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_1878 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1881 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_1879 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_1879 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1880 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized1__27 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_layer | input_fifos | 52115(15.04%) | 49087(14.17%) | 0(0.00%) | 3028(1.74%) | 98722(14.25%) | 468(39.66%) | 4(0.17%) | 0(0.00%) | | (fifo_layer) | input_fifos | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0 | channel_fifo | 2991(0.86%) | 2773(0.80%) | 0(0.00%) | 218(0.13%) | 5064(0.73%) | 20(1.69%) | 0(0.00%) | 0(0.00%) | | (ch0) | channel_fifo | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1513 | 920(0.27%) | 920(0.27%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1513 | 309(0.09%) | 309(0.09%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1518 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1519 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1520 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1582 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1521 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1581 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1522 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1580 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1523 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1524 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1525 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1579 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1526 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1578 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1527 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1577 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1528 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1529 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1576 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1530 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1575 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1531 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1532 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1574 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1533 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1534 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1573 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1535 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1572 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1536 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1571 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1537 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1570 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1538 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1539 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1569 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1540 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1541 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1568 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1542 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1543 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1567 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1544 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1545 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1566 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1547 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1565 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1548 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1549 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1550 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1562 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1563 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1564 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1551 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1561 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1552 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1553 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1554 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1555 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1556 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1557 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1558 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1559 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1560 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1516 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1517 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__1 | 217(0.06%) | 213(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__1 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.fifo_ila.clk_cross_tob_fifo | jfex_test_input_fifo__xdcDup__1 | 1703(0.49%) | 1489(0.43%) | 0(0.00%) | 214(0.12%) | 2620(0.38%) | 11(0.93%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.fifo_ila.clk_cross_tob_fifo) | jfex_test_input_fifo__xdcDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4469 | 106(0.03%) | 103(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4470 | 106(0.03%) | 103(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4471 | 106(0.03%) | 103(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4472 | 106(0.03%) | 103(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4473 | 106(0.03%) | 103(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4474 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4474 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4475 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4476 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4477 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4478 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4480 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4481 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4483 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4484 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc1.wdcext | aurora_in_fifo_wr_dc_fwft_ext_as_HD4485 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4486 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4486 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4488 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4489 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4490 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4491 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4492 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4493 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4494 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4495 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4495 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4496 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4497 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4497 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo_ila | ila_input_fifo | 1484(0.43%) | 1274(0.37%) | 0(0.00%) | 210(0.12%) | 2142(0.31%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (clk_cross_fifo_ila) | ila_input_fifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_input_fifo_ila_v6_2_12_ila | 1484(0.43%) | 1274(0.37%) | 0(0.00%) | 210(0.12%) | 2142(0.31%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_input_fifo_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_input_fifo_ila_v6_2_12_ila_core | 1483(0.43%) | 1273(0.37%) | 0(0.00%) | 210(0.12%) | 2136(0.31%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_input_fifo_ila_v6_2_12_ila_core | 36(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.02%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_input_fifo_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_input_fifo_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_input_fifo_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_input_fifo_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_input_fifo_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_input_fifo_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_input_fifo_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_input_fifo_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_input_fifo_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_input_fifo_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_input_fifo_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_input_fifo_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_input_fifo_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_input_fifo_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_input_fifo_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_input_fifo_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_input_fifo_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_75 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_76 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_76 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_77 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_78 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_input_fifo_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_input_fifo_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_input_fifo_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_input_fifo_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_input_fifo_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_input_fifo_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_input_fifo_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_71 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_72 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_72 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_73 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_74 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_input_fifo_ila_v6_2_12_ila_register | 1131(0.33%) | 1130(0.33%) | 0(0.00%) | 1(0.01%) | 1572(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_input_fifo_ila_v6_2_12_ila_register | 362(0.10%) | 361(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[17].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[18].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized17 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized18 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_input_fifo_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized72 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized73 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized75 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_56 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized19 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_input_fifo_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_input_fifo_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_input_fifo_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_input_fifo_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_input_fifo_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_input_fifo_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_input_fifo_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_input_fifo_ila_v6_2_12_ila_trigger | 160(0.05%) | 36(0.01%) | 0(0.00%) | 124(0.07%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_input_fifo_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_input_fifo_ltlib_v1_0_0_match | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_input_fifo_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_51 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_52 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_53 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_input_fifo_ila_v6_2_12_ila_trig_match | 146(0.04%) | 35(0.01%) | 0(0.00%) | 111(0.06%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_input_fifo_ila_v6_2_12_ila_trig_match | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_50 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_17 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_18 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_14 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_15 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_12 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_6 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[17].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__14 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[17].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[18].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[18].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_43 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_44 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_44 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_41 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_38 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_39 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_39 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_35 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_36 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_36 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_32 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_33 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_33 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_30 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_input_fifo_ltlib_v1_0_0_generic_memrd | 69(0.02%) | 67(0.02%) | 0(0.00%) | 2(0.01%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo_timer | fifo_timer__2 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6067 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6068 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6069 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6069 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6070 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6071 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6072 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6073 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6077 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6078 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6079 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6079 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6080 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6083 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6084 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6084 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6085 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6086 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6087 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6088 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6103 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6103 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6104 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6105 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6105 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1514 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1515 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1 | channel_fifo__parameterized1 | 1302(0.38%) | 1294(0.37%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch1) | channel_fifo__parameterized1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1443 | 700(0.20%) | 700(0.20%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1443 | 208(0.06%) | 208(0.06%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1449 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1450 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1512 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1451 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1511 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1452 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1510 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1453 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1454 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1455 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1509 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1456 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1508 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1457 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1507 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1458 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1459 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1506 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1460 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1505 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1461 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1462 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1504 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1463 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1464 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1503 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1465 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1502 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1466 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1501 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1467 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1500 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1468 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1469 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1499 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1470 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1471 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1498 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1472 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1473 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1497 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1474 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1475 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1496 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1477 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1495 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1478 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1479 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1480 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1492 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1493 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1494 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1481 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1491 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1482 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1483 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1484 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1485 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1486 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1487 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1489 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1490 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized1 | 111(0.03%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized1 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1446 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1447 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__3 | 240(0.07%) | 236(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__3 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4535 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4536 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4537 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4538 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4539 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4540 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4540 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4541 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4542 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4543 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4544 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4549 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4550 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4552 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4552 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4554 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4555 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4556 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4557 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4558 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4559 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4560 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4561 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4561 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4562 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4563 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4563 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6151 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6152 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6153 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6153 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6154 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6155 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6156 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6157 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6159 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6161 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6162 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6163 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6163 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6164 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6166 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6167 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6168 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6168 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6169 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6170 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6171 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6172 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6187 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6187 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6188 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6189 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6189 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6191 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__2 | 225(0.06%) | 221(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__2 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4502 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4503 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4504 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4505 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4506 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4507 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4507 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4508 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4509 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4510 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4511 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4513 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4514 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4516 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4517 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4519 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4519 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4521 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4522 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4523 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4524 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4525 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4526 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4527 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4528 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4528 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4529 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4530 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4530 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6109 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6110 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6111 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6111 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6112 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6113 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6114 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6115 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6117 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6119 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6120 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6121 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6121 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6124 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6125 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6126 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6127 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6128 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6129 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6130 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6145 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6145 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6146 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6147 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6147 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6149 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1444 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1445 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch10 | channel_fifo__parameterized19 | 1283(0.37%) | 1275(0.37%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch10) | channel_fifo__parameterized19 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1373 | 702(0.20%) | 702(0.20%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1373 | 209(0.06%) | 209(0.06%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1379 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1380 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1442 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1381 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1441 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1382 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1440 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1383 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1384 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1385 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1439 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1386 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1438 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1387 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1437 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1388 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1389 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1436 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1390 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1435 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1391 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1392 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1434 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1393 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1394 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1433 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1395 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1432 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1396 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1431 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1397 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1430 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1398 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1399 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1429 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1400 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1401 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1428 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1402 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1403 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1427 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1404 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1405 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1426 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1407 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1425 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1408 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1409 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1410 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1422 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1423 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1424 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1411 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1421 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1412 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1413 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1414 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1415 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1416 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1417 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1419 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized19 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized19 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1376 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1377 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__21 | 217(0.06%) | 213(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__21 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4865 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4866 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4867 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4868 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4869 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4870 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4870 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4871 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4872 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4873 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4874 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4876 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4879 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4880 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4882 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4882 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4884 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4885 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4886 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4887 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4888 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4889 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4890 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4891 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4891 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4893 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4893 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6571 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6572 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6573 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6573 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6574 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6575 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6576 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6577 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6578 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6581 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6582 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6583 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6583 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6584 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6586 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6587 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6588 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6588 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6589 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6590 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6591 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6592 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6607 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6607 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6608 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6609 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6609 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6611 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__20 | 226(0.07%) | 222(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__20 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4832 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4833 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4834 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4835 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4836 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4837 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4837 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4838 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4839 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4840 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4841 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4843 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4846 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4847 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4849 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4849 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4851 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4852 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4853 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4854 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4855 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4856 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4857 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4858 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4858 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4859 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4860 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4860 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6529 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6530 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6531 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6531 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6532 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6533 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6534 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6535 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6536 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6537 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6539 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6540 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6541 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6541 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6542 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6545 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6546 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6546 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6547 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6548 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6549 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6550 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6565 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6565 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6566 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6567 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6567 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6569 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1374 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1375 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch11 | channel_fifo__parameterized21 | 1348(0.39%) | 1340(0.39%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch11) | channel_fifo__parameterized21 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1303 | 751(0.22%) | 751(0.22%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1303 | 256(0.07%) | 256(0.07%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1309 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1310 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1372 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1311 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1371 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1312 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1370 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1313 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1314 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1315 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1369 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1316 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1368 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1317 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1367 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1318 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1319 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1366 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1320 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1365 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1321 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1322 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1364 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1323 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1324 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1363 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1325 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1362 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1326 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1361 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1327 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1360 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1328 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1329 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1359 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1330 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1331 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1358 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1332 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1333 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1357 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1334 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1335 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1356 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1337 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1355 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1338 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1339 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1340 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1352 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1353 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1354 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1341 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1351 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1342 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1343 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1344 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1345 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1346 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1347 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1349 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1350 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized21 | 118(0.03%) | 118(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized21 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1306 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1307 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__23 | 224(0.06%) | 220(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__23 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4931 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4932 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4933 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4934 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4935 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4936 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4936 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4937 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4938 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4939 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4940 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4942 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4943 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4945 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4946 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4948 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4948 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4950 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4951 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4952 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4953 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4954 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4955 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4956 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4957 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4957 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4958 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4959 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4959 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6655 | 99(0.03%) | 98(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6656 | 99(0.03%) | 98(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6657 | 99(0.03%) | 98(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6657 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6658 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6659 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6660 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6661 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6662 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6665 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6666 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6667 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6667 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6670 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6671 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6672 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6672 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6673 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6674 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6675 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6676 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6691 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6691 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6692 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6693 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6693 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6695 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__22 | 227(0.07%) | 223(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__22 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4898 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4899 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4900 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4901 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4902 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4903 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4903 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4904 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4905 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4906 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4907 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4909 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4912 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4913 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4915 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4915 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4917 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4918 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4919 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4920 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4921 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4922 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4923 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4924 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4924 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4925 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4926 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4926 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6613 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6614 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6615 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6615 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6616 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6617 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6618 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6619 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6620 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6621 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6623 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6624 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6625 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6625 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6626 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6629 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6630 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6630 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6631 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6632 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6633 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6634 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6649 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6649 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6651 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6651 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6653 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1304 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1305 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2 | channel_fifo__parameterized3 | 1315(0.38%) | 1307(0.38%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch2) | channel_fifo__parameterized3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1233 | 716(0.21%) | 716(0.21%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1233 | 209(0.06%) | 209(0.06%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1239 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1240 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1302 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1241 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1301 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1242 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1300 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1243 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1244 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1245 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1299 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1246 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1298 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1247 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1297 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1248 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1249 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1296 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1250 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1295 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1251 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1252 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1294 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1253 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1254 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1293 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1255 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1292 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1256 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1291 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1257 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1290 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1258 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1259 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1289 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1260 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1261 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1288 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1262 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1263 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1287 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1264 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1265 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1286 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1267 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1285 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1268 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1269 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1270 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1282 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1283 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1284 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1271 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1281 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1272 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1273 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1274 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1275 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1276 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1277 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1279 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1280 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized3 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized3 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1236 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1237 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__5 | 233(0.07%) | 229(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__5 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5261 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5262 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5263 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5264 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5265 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5266 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5266 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5267 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5268 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5269 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5270 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5272 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5275 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5276 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5278 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5278 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5280 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5281 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5282 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5283 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5284 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5285 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5286 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5287 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5287 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5288 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5289 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5289 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7075 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7076 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7077 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7077 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7078 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7079 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7080 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7081 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7083 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7085 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7086 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7087 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7087 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7088 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7090 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7091 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7092 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7092 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7093 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7094 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7095 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7096 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7111 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7111 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7112 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7113 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7113 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7115 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__4 | 228(0.07%) | 224(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__4 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5228 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5229 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5230 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5231 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5232 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5233 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5233 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5234 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5235 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5236 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5237 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5239 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5240 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5242 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5243 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5245 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5245 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5248 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5249 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5250 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5251 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5252 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5253 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5254 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5254 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5256 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5256 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7033 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7034 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7035 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7035 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7036 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7037 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7038 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7039 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7040 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7041 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7043 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7044 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7045 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7045 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7048 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7049 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7050 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7050 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7051 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7052 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7053 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7054 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7069 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7069 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7071 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7071 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7073 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1234 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1235 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3 | channel_fifo__parameterized5 | 1340(0.39%) | 1332(0.38%) | 0(0.00%) | 8(0.01%) | 2871(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch3) | channel_fifo__parameterized5 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1163 | 760(0.22%) | 760(0.22%) | 0(0.00%) | 0(0.00%) | 1422(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1163 | 173(0.05%) | 173(0.05%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1168 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1169 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1170 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1232 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1171 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1231 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1172 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1230 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1173 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1174 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1175 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1229 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1176 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1228 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1177 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1227 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1178 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1179 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1226 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1180 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1225 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1181 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1182 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1224 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1183 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1184 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1223 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1185 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1222 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1186 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1221 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1187 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1220 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1188 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1189 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1219 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1190 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1191 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1218 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1192 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1193 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1217 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1194 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1195 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1216 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1196 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1197 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1197 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1215 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1198 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1199 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1200 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1212 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1213 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1214 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1201 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1211 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1202 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1203 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1204 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1205 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1206 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1207 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1208 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1209 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized5 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized5 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1166 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1167 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__7 | 226(0.07%) | 222(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__7 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5855 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5856 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5857 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5858 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5859 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5860 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5860 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5861 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5862 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5863 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5864 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5866 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5867 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5869 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5870 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5872 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5872 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5875 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5876 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5877 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5878 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5879 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5880 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5881 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5881 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5882 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5883 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5883 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7831 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7832 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7833 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7833 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7834 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7835 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7836 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7837 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7839 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7841 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7842 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7843 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7843 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7846 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7847 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7848 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7848 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7849 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7850 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7851 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7852 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7867 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7867 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7869 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7869 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7871 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__6 | 228(0.07%) | 224(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__6 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5822 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5823 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5824 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5825 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5826 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5827 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5827 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5828 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5829 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5830 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5831 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5833 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5834 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5836 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5837 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5839 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5839 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5841 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5842 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5843 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5844 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5845 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5846 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5847 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5848 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5848 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5849 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5850 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5850 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7789 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7790 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7791 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7791 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7792 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7793 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7794 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7795 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7796 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7797 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7799 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7800 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7801 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7801 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7802 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7805 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7806 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7806 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7807 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7808 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7809 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7810 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7825 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7825 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7827 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7827 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7829 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1164 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1165 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch4 | channel_fifo__parameterized7 | 1292(0.37%) | 1284(0.37%) | 0(0.00%) | 8(0.01%) | 2871(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch4) | channel_fifo__parameterized7 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1093 | 729(0.21%) | 729(0.21%) | 0(0.00%) | 0(0.00%) | 1422(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1093 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1098 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1099 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1100 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1162 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1101 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1161 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1102 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1160 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1103 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1104 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1105 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1159 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1106 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1158 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1107 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1157 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1108 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1109 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1156 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1110 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1155 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1111 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1112 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1154 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1113 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1114 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1153 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1115 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1152 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1116 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1151 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1117 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1150 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1118 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1119 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1149 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1120 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1121 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1148 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1122 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1123 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1147 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1124 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1125 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1146 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1126 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1127 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1127 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1145 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1128 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1129 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1130 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1142 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1143 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1144 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1131 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1141 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1132 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1133 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1134 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1135 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1136 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1137 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1138 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1139 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1140 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized7 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized7 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1096 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1097 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__9 | 212(0.06%) | 208(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__9 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5921 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5922 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5923 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5924 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5925 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5926 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5926 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5927 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5928 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5929 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5930 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5932 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5933 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5935 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5936 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5938 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5938 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5940 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5941 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5942 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5943 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5944 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5945 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5946 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5947 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5947 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5948 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5949 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5949 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7915 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7916 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7917 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7917 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7918 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7919 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7920 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7921 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7922 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7923 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7925 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7926 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7927 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7927 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7928 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7930 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7931 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7932 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7932 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7933 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7934 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7935 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7936 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7951 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7951 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7952 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7953 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7953 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7955 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__8 | 225(0.06%) | 221(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__8 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5888 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5889 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5890 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5891 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5892 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5893 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5893 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5894 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5895 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5896 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5897 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5899 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5900 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5902 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5903 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5905 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5905 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5907 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5908 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5909 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5910 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5911 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5912 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5913 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5914 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5914 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5915 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5916 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5916 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7873 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7874 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7875 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7875 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7876 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7877 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7878 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7879 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7880 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7881 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7883 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7884 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7885 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7885 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7886 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7888 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7889 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7890 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7890 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7891 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7892 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7893 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7894 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7909 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7909 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7911 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7911 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7913 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1094 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1095 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch5 | channel_fifo__parameterized9 | 1296(0.37%) | 1288(0.37%) | 0(0.00%) | 8(0.01%) | 2871(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch5) | channel_fifo__parameterized9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_1023 | 723(0.21%) | 723(0.21%) | 0(0.00%) | 0(0.00%) | 1422(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_1023 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1028 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1029 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1030 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1092 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1031 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1091 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1032 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1090 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1033 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1034 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1035 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1089 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1036 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1088 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1037 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1087 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1038 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1039 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1086 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1040 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1085 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1041 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1042 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1084 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1043 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1044 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1083 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1045 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1082 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1046 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1081 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1047 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1080 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1048 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1049 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1079 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1050 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1051 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1078 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1052 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1053 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1077 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1054 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1055 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1076 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1056 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1057 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1057 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1075 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1058 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1059 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1060 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1072 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1073 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1074 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1061 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1071 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1062 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1063 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1064 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1065 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1066 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1067 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1068 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1069 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized9 | 111(0.03%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized9 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1026 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1027 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__11 | 219(0.06%) | 215(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__11 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5987 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5988 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5989 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5990 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5991 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5992 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5992 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5993 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5994 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5995 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5996 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5998 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5999 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD6000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD6001 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD6002 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD6004 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD6004 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD6005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD6006 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD6007 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD6008 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD6008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD6009 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD6010 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD6011 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD6012 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD6013 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD6013 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD6014 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD6015 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD6015 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD6016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD6017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD6018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD6019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7999 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD8000 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD8001 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD8001 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD8002 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD8003 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD8004 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD8005 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD8006 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD8006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD8007 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD8008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD8009 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD8010 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD8011 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD8011 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD8012 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD8013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD8014 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD8015 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD8016 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD8016 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD8017 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD8018 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD8019 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD8020 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD8021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD8022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD8023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD8024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD8025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD8026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD8027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD8028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD8029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD8030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD8031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD8032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD8033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD8034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD8035 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD8035 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD8036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD8037 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD8037 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD8038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD8039 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__10 | 230(0.07%) | 226(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__10 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5954 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5955 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5956 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5957 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5958 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5959 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5959 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5960 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5961 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5962 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5963 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5965 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5966 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5968 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5969 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5971 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5971 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5973 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5974 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5975 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5976 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5977 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5978 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5979 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5980 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5980 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5981 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5982 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5982 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7957 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7958 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7959 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7959 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7960 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7961 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7962 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7963 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7964 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7965 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7967 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7968 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7969 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7969 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7970 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7972 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7973 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7974 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7974 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7975 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7976 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7977 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7978 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7993 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7993 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7994 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7995 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7995 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7997 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1024 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1025 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch6 | channel_fifo__parameterized11 | 1291(0.37%) | 1283(0.37%) | 0(0.00%) | 8(0.01%) | 2871(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch6) | channel_fifo__parameterized11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_953 | 721(0.21%) | 721(0.21%) | 0(0.00%) | 0(0.00%) | 1422(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_953 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_958 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_959 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_960 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1022 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_961 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1021 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_962 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1020 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_963 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_964 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_965 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1019 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_966 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1018 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_967 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1017 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_968 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_969 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1016 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_970 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1015 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_971 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_972 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1014 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_973 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_974 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1013 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_975 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1012 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_976 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1011 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_977 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1010 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_978 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_979 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1009 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_980 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_981 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1008 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_982 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_983 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1007 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_984 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_985 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1006 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_986 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_987 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_987 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1005 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_988 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_989 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_990 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1002 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1003 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1004 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_991 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1001 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_992 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_993 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_994 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_995 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_996 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_997 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_998 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_999 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1000 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized11 | 111(0.03%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized11 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_956 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_957 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__13 | 218(0.06%) | 214(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__13 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4601 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4602 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4603 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4604 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4605 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4606 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4606 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4607 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4608 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4609 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4610 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4612 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4613 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4615 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4616 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4618 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4618 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4620 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4621 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4622 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4623 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4624 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4625 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4626 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4627 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4627 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4629 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4629 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6235 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6236 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6237 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6237 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6238 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6239 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6240 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6241 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6245 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6246 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6247 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6247 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6250 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6251 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6252 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6252 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6253 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6254 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6255 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6256 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6271 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6271 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6272 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6273 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6273 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6275 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__12 | 228(0.07%) | 224(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__12 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4568 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4569 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4570 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4571 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4572 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4573 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4573 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4574 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4575 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4576 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4577 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4580 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4582 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4583 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4585 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4585 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4587 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4588 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4589 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4590 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4591 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4592 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4593 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4594 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4594 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4595 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4596 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4596 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6193 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6194 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6195 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6195 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6196 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6197 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6198 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6199 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6200 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6201 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6203 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6204 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6205 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6205 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6209 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6210 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6210 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6211 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6212 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6213 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6214 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6229 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6229 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6231 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6231 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6233 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_954 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_955 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch7 | channel_fifo__parameterized13 | 1300(0.38%) | 1292(0.37%) | 0(0.00%) | 8(0.01%) | 2871(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch7) | channel_fifo__parameterized13 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_883 | 714(0.21%) | 714(0.21%) | 0(0.00%) | 0(0.00%) | 1422(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_883 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_888 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_889 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_890 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_952 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_891 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_951 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_892 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_950 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_893 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_894 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_895 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_949 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_896 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_948 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_897 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_947 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_898 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_899 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_946 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_900 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_945 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_901 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_902 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_944 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_903 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_904 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_943 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_905 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_942 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_906 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_941 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_907 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_940 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_908 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_909 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_939 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_910 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_911 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_938 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_912 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_913 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_937 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_914 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_915 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_936 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_916 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_917 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_917 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_935 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_918 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_919 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_920 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_932 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_933 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_934 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_921 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_931 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_922 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_923 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_924 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_925 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_926 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_927 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_928 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_929 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_930 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized13 | 121(0.03%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized13 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_886 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_887 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__15 | 221(0.06%) | 217(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__15 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4667 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4668 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4669 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4670 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4671 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4672 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4672 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4673 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4674 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4675 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4676 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4681 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4682 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4684 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4684 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4686 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4687 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4688 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4689 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4690 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4691 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4692 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4693 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4693 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4695 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4695 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6319 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6320 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6321 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6321 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6322 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6323 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6324 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6325 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6326 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6327 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6329 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6330 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6331 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6331 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6332 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6335 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6336 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6336 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6337 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6338 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6339 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6340 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6355 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6355 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6356 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6357 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6357 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6359 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__14 | 228(0.07%) | 224(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__14 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4634 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4635 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4636 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4637 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4638 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4639 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4639 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4640 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4641 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4642 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4643 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4648 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4649 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4651 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4651 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4653 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4654 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4655 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4656 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4657 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4658 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4659 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4660 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4660 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4661 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4662 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4662 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6277 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6278 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6279 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6279 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6280 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6281 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6282 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6283 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6285 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6287 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6288 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6289 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6289 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6290 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6292 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6293 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6294 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6294 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6295 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6296 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6297 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6298 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6313 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6313 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6314 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6315 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6315 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6317 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_884 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_885 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch8 | channel_fifo__parameterized15 | 1283(0.37%) | 1275(0.37%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch8) | channel_fifo__parameterized15 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_813 | 703(0.20%) | 703(0.20%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_813 | 207(0.06%) | 207(0.06%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_819 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_820 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_882 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_821 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_881 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_822 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_880 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_823 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_824 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_825 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_879 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_826 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_878 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_827 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_877 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_828 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_829 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_876 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_830 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_875 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_831 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_832 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_874 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_833 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_834 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_873 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_835 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_872 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_836 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_871 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_837 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_870 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_839 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_869 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_840 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_841 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_868 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_842 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_843 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_867 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_844 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_845 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_866 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_847 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_865 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_848 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_849 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_850 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_862 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_863 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_864 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_851 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_861 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_852 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_853 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_854 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_855 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_856 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_857 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_859 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_860 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized15 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized15 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_816 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_817 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__17 | 214(0.06%) | 210(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__17 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4733 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4734 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4735 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4736 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4737 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4738 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4738 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4739 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4740 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4741 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4742 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4744 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4747 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4748 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4750 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4750 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4753 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4754 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4755 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4756 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4757 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4758 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4759 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4759 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4760 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4761 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4761 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6403 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6404 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6405 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6405 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6406 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6407 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6408 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6409 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6410 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6411 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6413 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6414 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6415 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6415 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6416 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6418 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6419 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6420 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6420 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6421 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6422 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6423 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6424 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6439 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6439 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6440 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6441 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6441 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6443 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__16 | 228(0.07%) | 224(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__16 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4700 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4701 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4702 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4703 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4704 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4705 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4705 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4706 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4707 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4708 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4709 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4711 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4714 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4715 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4717 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4717 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4720 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4721 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4722 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4723 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4724 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4725 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4726 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4726 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4728 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4728 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6361 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6362 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6363 | 98(0.03%) | 97(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6363 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6364 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6365 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6366 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6367 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6368 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6369 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6371 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6372 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6373 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6373 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6374 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6376 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6377 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6378 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6378 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6379 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6380 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6381 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6382 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6397 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6397 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6398 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6399 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6399 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6401 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_814 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_815 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch9 | channel_fifo__parameterized17 | 1300(0.38%) | 1292(0.37%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (ch9) | channel_fifo__parameterized17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__23 | 706(0.20%) | 706(0.20%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__23 | 211(0.06%) | 211(0.06%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_748 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_749 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_750 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_812 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_751 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_811 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_752 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_810 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_753 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_754 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_755 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_809 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_756 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_808 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_757 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_807 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_758 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_759 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_806 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_760 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_805 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_761 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_762 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_804 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_763 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_764 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_803 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_765 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_802 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_766 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_801 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_767 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_800 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_768 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_769 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_799 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_770 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_771 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_798 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_772 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_773 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_797 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_774 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_775 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_796 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_777 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_795 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_778 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_779 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_780 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_792 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_793 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_794 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_781 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_791 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_782 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_783 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_784 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_785 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_786 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_787 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_789 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_790 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized17 | 118(0.03%) | 118(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized17 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_746 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_747 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__19 | 221(0.06%) | 217(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__19 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4799 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4800 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4801 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4802 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4803 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4804 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4804 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4805 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4806 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4807 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4808 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4810 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4811 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4813 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4814 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4816 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4816 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4819 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4820 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4821 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4822 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4823 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4824 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4825 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4825 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4827 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4827 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6487 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6488 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6489 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6489 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6490 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6491 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6492 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6493 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6494 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6495 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6497 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6498 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6499 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6499 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6500 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6502 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6503 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6504 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6504 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6505 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6506 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6507 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6508 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6523 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6523 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6524 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6525 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6525 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6527 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__18 | 227(0.07%) | 223(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__18 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4766 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4767 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4768 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4769 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4770 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4771 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4771 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4772 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4773 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4774 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4775 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4777 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4780 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4781 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4783 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4783 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4785 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4786 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4787 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4788 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4789 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4790 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4791 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4792 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4792 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4794 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4794 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6445 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6446 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6447 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6447 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6448 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6449 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6450 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6451 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6452 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6455 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6456 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6457 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6457 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6460 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6461 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6462 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6462 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6463 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6464 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6465 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6466 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6481 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6481 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6482 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6483 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6483 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6485 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_745 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__24 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch12 | channel_fifo__parameterized23 | 6708(1.94%) | 5886(1.70%) | 0(0.00%) | 822(0.47%) | 11064(1.60%) | 28(2.37%) | 1(0.04%) | 0(0.00%) | | (gen_jfex_chan.ch12) | channel_fifo__parameterized23 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.calo_fifo_out_ila | aurora_fifo_out_ila | 1141(0.33%) | 948(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.calo_fifo_out_ila) | aurora_fifo_out_ila | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila | 1141(0.33%) | 948(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core | 1140(0.33%) | 947(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register | 795(0.23%) | 794(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.channel_fifo_vio | data_fifo_vio | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.channel_fifo_vio) | data_fifo_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | data_fifo_vio_vio_v3_0_22_vio | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | data_fifo_vio_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | data_fifo_vio_vio_v3_0_22_decoder | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | data_fifo_vio_vio_v3_0_22_probe_in_one | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | data_fifo_vio_vio_v3_0_22_probe_out_all | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | data_fifo_vio_vio_v3_0_22_probe_out_all | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | data_fifo_vio_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | data_fifo_vio_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_in_ila | aurora_fifo_in_ila | 1418(0.41%) | 1200(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (chan_dbg.tob_fifo_in_ila) | aurora_fifo_in_ila | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_in_ila_ila_v6_2_12_ila | 1418(0.41%) | 1200(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | aurora_fifo_in_ila_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_core | 1417(0.41%) | 1199(0.35%) | 0(0.00%) | 218(0.13%) | 2096(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_in_ila_ila_v6_2_12_ila_core | 42(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.02%) | 125(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_in_ila_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_77 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_78 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_73 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_74 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_in_ila_ila_v6_2_12_ila_register | 1057(0.31%) | 1056(0.30%) | 0(0.00%) | 1(0.01%) | 1486(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_in_ila_ila_v6_2_12_ila_register | 352(0.10%) | 351(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_in_ila_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_56 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized17 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger | 168(0.05%) | 42(0.01%) | 0(0.00%) | 126(0.07%) | 218(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_in_ila_ltlib_v1_0_0_match | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_in_ila_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_51 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_52 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_53 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match | 154(0.04%) | 41(0.01%) | 0(0.00%) | 113(0.06%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_50 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_in_ila_ltlib_v1_0_0_generic_memrd | 63(0.02%) | 61(0.02%) | 0(0.00%) | 2(0.01%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_out_ila | aurora_fifo_out_ila_HD8251 | 1142(0.33%) | 949(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.tob_fifo_out_ila) | aurora_fifo_out_ila_HD8251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8252 | 1142(0.33%) | 949(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8252 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8253 | 1141(0.33%) | 948(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8253 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory_HD8254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_HD8255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth_HD8256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD8257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD8258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD8259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD8260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD8261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD8262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD8263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD8264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8265 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8265 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD8266 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7_HD8267 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1_HD8268 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8269 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8269 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1_HD8270 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8271 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8271 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1_HD8272 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1_HD8273 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6_HD8274 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1_HD8275 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8276 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8277 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8277 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57_HD8278 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58_HD8279 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8280 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8280 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4_HD8281 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5_HD8282 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2_HD8283 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay_HD8284 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8285 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8286 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8286 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD8287 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD8288 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2_HD8289 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8290 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8291 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8291 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53_HD8292 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54_HD8293 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8294 | 796(0.23%) | 795(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8294 | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s_HD8295 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD8296 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD8297 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD8298 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD8299 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD8300 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD8301 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD8302 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD8303 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD8304 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD8305 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs_HD8306 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44_HD8307 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47_HD8308 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45_HD8309 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46_HD8310 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46_HD8311 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45_HD8312 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47_HD8313 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44_HD8314 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48_HD8315 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43_HD8316 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49_HD8317 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42_HD8318 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29_HD8319 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50_HD8320 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30_HD8321 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD8322 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31_HD8323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49_HD8324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50_HD8325 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41_HD8326 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51_HD8327 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40_HD8328 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52_HD8329 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD8330 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53_HD8331 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39_HD8332 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54_HD8333 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38_HD8334 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55_HD8335 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37_HD8336 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57_HD8337 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36_HD8338 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59_HD8339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35_HD8340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34_HD8342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32_HD8343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48_HD8344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD8345 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream_HD8346 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_HD8347 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8348 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8348 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_HD8349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8350 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8350 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection_HD8351 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2_HD8352 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3_HD8353 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1_HD8354 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer_HD8355 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1_HD8356 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8357 | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8357 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8358 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8359 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8360 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8360 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32_HD8361 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD8362 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8363 | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8363 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8364 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8365 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8366 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8366 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30_HD8367 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8368 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8369 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8370 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8370 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD8371 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8372 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8373 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8374 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8374 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24_HD8375 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8376 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8377 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8378 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8378 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14_HD8379 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15_HD8380 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16_HD8381 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17_HD8382 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18_HD8383 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19_HD8384 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20_HD8385 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21_HD8386 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8387 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8388 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8389 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8389 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD8390 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8391 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8392 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8393 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8393 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD8394 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8395 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8396 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8397 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8397 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD8398 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8399 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8400 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8401 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8401 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3_HD8402 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD8403 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8404 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8405 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8406 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8406 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_HD8407 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD8408 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8409 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8410 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8411 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8411 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD8412 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd_HD8413 | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__14 | 842(0.24%) | 842(0.24%) | 0(0.00%) | 0(0.00%) | 1437(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__14 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1784 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1785 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1786 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1848 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1787 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1847 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1788 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1846 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1789 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1790 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1791 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1845 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1792 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1844 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1793 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1843 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1794 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1795 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1842 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1796 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1841 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1797 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1798 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1840 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1799 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1800 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1839 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1801 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1838 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1802 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1837 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1803 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1836 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1805 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1835 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1806 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1807 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1834 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1808 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1809 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1833 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1810 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1811 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1832 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1812 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1813 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1831 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1814 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1815 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1816 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1828 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1829 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1830 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1817 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1827 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1818 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1819 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1820 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1821 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1822 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1823 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1824 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1825 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1826 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized23 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized23 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1782 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1783 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__24 | 184(0.05%) | 180(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4964 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4965 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4966 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4967 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4968 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4969 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4969 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4970 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4971 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4972 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4973 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4976 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4978 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4979 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4981 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4981 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4983 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4984 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4985 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4986 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4987 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4988 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4989 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4990 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4990 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4991 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4992 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4992 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6697 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6698 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6699 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6699 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6700 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6701 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6702 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6703 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6705 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6707 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6708 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6709 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6709 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6710 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6713 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6714 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6714 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6715 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6716 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6717 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6718 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6733 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6733 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6735 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6735 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6737 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.fifo_ila.clk_cross_tob_fifo | jfex_test_input_fifo | 1699(0.49%) | 1485(0.43%) | 0(0.00%) | 214(0.12%) | 2620(0.38%) | 11(0.93%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.fifo_ila.clk_cross_tob_fifo) | jfex_test_input_fifo | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4997 | 104(0.03%) | 101(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4998 | 104(0.03%) | 101(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4999 | 104(0.03%) | 101(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5000 | 104(0.03%) | 101(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5001 | 104(0.03%) | 101(0.03%) | 0(0.00%) | 3(0.01%) | 248(0.04%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5002 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5002 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5003 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5004 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5005 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5006 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5008 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5009 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5011 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5012 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc1.wdcext | aurora_in_fifo_wr_dc_fwft_ext_as_HD5013 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5014 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5014 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5016 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5017 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5018 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5019 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5020 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5021 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5022 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5023 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5023 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5024 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5025 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5025 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo_ila | ila_input_fifo_HD8042 | 1482(0.43%) | 1272(0.37%) | 0(0.00%) | 210(0.12%) | 2142(0.31%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (clk_cross_fifo_ila) | ila_input_fifo_HD8042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_input_fifo_ila_v6_2_12_ila_HD8043 | 1482(0.43%) | 1272(0.37%) | 0(0.00%) | 210(0.12%) | 2142(0.31%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_input_fifo_ila_v6_2_12_ila_HD8043 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_input_fifo_ila_v6_2_12_ila_core_HD8044 | 1481(0.43%) | 1271(0.37%) | 0(0.00%) | 210(0.12%) | 2136(0.31%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_input_fifo_ila_v6_2_12_ila_core_HD8044 | 36(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.02%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_input_fifo_ila_v6_2_12_ila_trace_memory_HD8045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_input_fifo_blk_mem_gen_v8_4_5_HD8046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_input_fifo_blk_mem_gen_v8_4_5_synth_HD8047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD8048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD8049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD8050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD8051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD8052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_input_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD8053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_input_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD8054 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_input_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD8054 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_input_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD8055 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_input_fifo_ltlib_v1_0_0_cfglut7_HD8056 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_input_fifo_ltlib_v1_0_0_cfglut7__1_HD8057 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_input_fifo_ila_v6_2_12_ila_cap_addrgen_HD8058 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_input_fifo_ila_v6_2_12_ila_cap_addrgen_HD8058 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_input_fifo_ltlib_v1_0_0_cfglut6__1_HD8059 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_input_fifo_ila_v6_2_12_ila_cap_sample_counter_HD8060 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_input_fifo_ila_v6_2_12_ila_cap_sample_counter_HD8060 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_input_fifo_ltlib_v1_0_0_cfglut4__1_HD8061 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_input_fifo_ltlib_v1_0_0_cfglut5__1_HD8062 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_input_fifo_ltlib_v1_0_0_cfglut6_HD8063 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_input_fifo_ltlib_v1_0_0_match_nodelay__1_HD8064 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_75_HD8065 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_75_HD8065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_76_HD8066 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_76_HD8066 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_77_HD8067 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_78_HD8068 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_input_fifo_ila_v6_2_12_ila_cap_window_counter_HD8069 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_input_fifo_ila_v6_2_12_ila_cap_window_counter_HD8069 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_input_fifo_ltlib_v1_0_0_cfglut4_HD8070 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_input_fifo_ltlib_v1_0_0_cfglut5_HD8071 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_input_fifo_ltlib_v1_0_0_cfglut5__2_HD8072 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_input_fifo_ltlib_v1_0_0_match_nodelay_HD8073 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD8074 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD8074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD8075 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD8075 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD8076 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD8077 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_input_fifo_ltlib_v1_0_0_match_nodelay__2_HD8078 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_71_HD8079 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA_nodelay_71_HD8079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_72_HD8080 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized3_72_HD8080 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_73_HD8081 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_74_HD8082 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_input_fifo_ila_v6_2_12_ila_register_HD8083 | 1129(0.33%) | 1128(0.33%) | 0(0.00%) | 1(0.01%) | 1572(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_input_fifo_ila_v6_2_12_ila_register_HD8083 | 362(0.10%) | 361(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s_HD8084 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD8085 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD8086 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD8087 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD8088 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD8089 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized14_HD8090 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized15_HD8091 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[17].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized16_HD8092 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[18].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized17_HD8093 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD8094 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD8095 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD8096 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD8097 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD8098 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD8099 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD8100 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD8101 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD8102 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized18_HD8103 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_input_fifo_xsdbs_v1_0_2_xsdbs_HD8104 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized62_HD8105 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_67_HD8106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized63_HD8107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_66_HD8108 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized64_HD8109 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_65_HD8110 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized65_HD8111 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_64_HD8112 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized66_HD8113 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_63_HD8114 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized67_HD8115 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_62_HD8116 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized47_HD8117 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_70_HD8118 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized48_HD8119 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD8120 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized49_HD8121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_69_HD8122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized68_HD8123 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_61_HD8124 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized69_HD8125 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_60_HD8126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized70_HD8127 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD8128 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized71_HD8129 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_59_HD8130 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized72_HD8131 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_58_HD8132 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized73_HD8133 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_57_HD8134 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized75_HD8135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_56_HD8136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized77_HD8137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_55_HD8138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized80_HD8139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized80_HD8139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_54_HD8140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_input_fifo_xsdbs_v1_0_2_reg__parameterized50_HD8141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_68_HD8142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_input_fifo_xsdbs_v1_0_2_reg_p2s__parameterized19_HD8143 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_input_fifo_xsdbs_v1_0_2_reg_stream_HD8144 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_input_fifo_xsdbs_v1_0_2_reg_ctl_HD8145 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_input_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD8146 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_input_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD8146 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_input_fifo_xsdbs_v1_0_2_reg_stat_HD8147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_input_fifo_ila_v6_2_12_ila_reset_ctrl_HD8148 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_input_fifo_ila_v6_2_12_ila_reset_ctrl_HD8148 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_input_fifo_ltlib_v1_0_0_rising_edge_detection_HD8149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD8150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD8151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD8152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_input_fifo_ltlib_v1_0_0_async_edge_xfer_HD8153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_input_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD8154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_input_fifo_ila_v6_2_12_ila_trigger_HD8155 | 160(0.05%) | 36(0.01%) | 0(0.00%) | 124(0.07%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_input_fifo_ila_v6_2_12_ila_trigger_HD8155 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_input_fifo_ltlib_v1_0_0_match_HD8156 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_input_fifo_ltlib_v1_0_0_match_HD8156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA_HD8157 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA_HD8157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA_HD8158 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA_HD8158 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_51_HD8159 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_52_HD8160 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_53_HD8161 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_input_fifo_ila_v6_2_12_ila_trig_match_HD8162 | 146(0.04%) | 35(0.01%) | 0(0.00%) | 111(0.06%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_input_fifo_ila_v6_2_12_ila_trig_match_HD8162 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized0_HD8163 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized0_HD8163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD8164 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD8164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD8165 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD8165 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD8166 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_48_HD8167 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_49_HD8168 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_50_HD8169 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__8_HD8170 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__8_HD8170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_20_HD8171 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_20_HD8171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_21_HD8172 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_21_HD8172 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD8173 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__9_HD8174 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__9_HD8174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_17_HD8175 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_17_HD8175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_18_HD8176 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_18_HD8176 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD8177 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__10_HD8178 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__10_HD8178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_14_HD8179 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_14_HD8179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_15_HD8180 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_15_HD8180 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD8181 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__11_HD8182 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__11_HD8182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_11_HD8183 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_11_HD8183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_12_HD8184 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_12_HD8184 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD8185 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__12_HD8186 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__12_HD8186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_8_HD8187 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_8_HD8187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_9_HD8188 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_9_HD8188 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD8189 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized4_HD8190 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized4_HD8190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized4_HD8191 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized4_HD8191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_6_HD8192 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_6_HD8192 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD8193 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__13_HD8194 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__13_HD8194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD8195 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD8195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_4_HD8196 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_4_HD8196 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD8197 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[17].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__14_HD8198 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[17].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__14_HD8198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD8199 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD8199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_1_HD8200 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_1_HD8200 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD8201 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[18].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2_HD8202 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[18].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2_HD8202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD8203 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD8203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD8204 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD8204 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD8205 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized1_HD8206 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized1_HD8206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD8207 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD8207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD8208 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD8208 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice_HD8209 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD8210 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__1_HD8211 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__1_HD8211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_43_HD8212 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_43_HD8212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_44_HD8213 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_44_HD8213 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_45_HD8214 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized3_HD8215 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized3_HD8215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized3_HD8216 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized3_HD8216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_41_HD8217 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_41_HD8217 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_42_HD8218 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__2_HD8219 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__2_HD8219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_38_HD8220 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_38_HD8220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_39_HD8221 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_39_HD8221 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD8222 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__3_HD8223 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__3_HD8223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_35_HD8224 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_35_HD8224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_36_HD8225 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_36_HD8225 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_37_HD8226 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__4_HD8227 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__4_HD8227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_32_HD8228 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_32_HD8228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_33_HD8229 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_33_HD8229 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD8230 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__5_HD8231 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__5_HD8231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_29_HD8232 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_29_HD8232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_30_HD8233 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_30_HD8233 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_31_HD8234 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__6_HD8235 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__6_HD8235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_26_HD8236 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_26_HD8236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_27_HD8237 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_27_HD8237 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD8238 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__7_HD8239 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_input_fifo_ltlib_v1_0_0_match__parameterized2__7_HD8239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_23_HD8240 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_input_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_23_HD8240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_24_HD8241 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_input_fifo_ltlib_v1_0_0_all_typeA__parameterized2_24_HD8241 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_input_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD8242 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_input_fifo_ltlib_v1_0_0_generic_memrd_HD8243 | 69(0.02%) | 67(0.02%) | 0(0.00%) | 2(0.01%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo_timer | fifo_timer | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6739 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6740 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6741 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6741 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6742 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6743 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6744 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6745 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6746 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6749 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6750 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6751 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6751 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6754 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6755 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6756 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6756 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6757 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6758 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6759 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6760 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6775 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6775 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6777 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6777 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6779 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__15 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__13 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch13 | channel_fifo__parameterized25 | 5191(1.50%) | 4579(1.32%) | 0(0.00%) | 612(0.35%) | 8868(1.28%) | 26(2.20%) | 1(0.04%) | 0(0.00%) | | (gen_jfex_chan.ch13) | channel_fifo__parameterized25 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.calo_fifo_out_ila | aurora_fifo_out_ila_HD8414 | 1140(0.33%) | 947(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.calo_fifo_out_ila) | aurora_fifo_out_ila_HD8414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8415 | 1140(0.33%) | 947(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8416 | 1139(0.33%) | 946(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8416 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory_HD8417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_HD8418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth_HD8419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD8420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD8421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD8422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD8423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD8424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD8425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD8426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD8427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8428 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8428 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD8429 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7_HD8430 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1_HD8431 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8432 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8432 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1_HD8433 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8434 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8434 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1_HD8435 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1_HD8436 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6_HD8437 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1_HD8438 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8439 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8440 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8440 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57_HD8441 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58_HD8442 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8443 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8443 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4_HD8444 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5_HD8445 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2_HD8446 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay_HD8447 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8448 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8449 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8449 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD8450 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD8451 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2_HD8452 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8453 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8454 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8454 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53_HD8455 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54_HD8456 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8457 | 794(0.23%) | 793(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8457 | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s_HD8458 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD8459 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD8460 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD8461 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD8462 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD8463 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD8464 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD8465 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD8466 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD8467 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD8468 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs_HD8469 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44_HD8470 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47_HD8471 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45_HD8472 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46_HD8473 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46_HD8474 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45_HD8475 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47_HD8476 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44_HD8477 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48_HD8478 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43_HD8479 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49_HD8480 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42_HD8481 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29_HD8482 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50_HD8483 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30_HD8484 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD8485 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31_HD8486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49_HD8487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50_HD8488 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41_HD8489 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51_HD8490 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40_HD8491 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52_HD8492 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD8493 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53_HD8494 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39_HD8495 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54_HD8496 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38_HD8497 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55_HD8498 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37_HD8499 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57_HD8500 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36_HD8501 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59_HD8502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35_HD8503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34_HD8505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32_HD8506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48_HD8507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD8508 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream_HD8509 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_HD8510 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8511 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8511 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_HD8512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8513 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8513 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection_HD8514 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2_HD8515 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3_HD8516 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1_HD8517 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer_HD8518 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1_HD8519 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8520 | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8520 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8521 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8522 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8523 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8523 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32_HD8524 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD8525 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8526 | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8526 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8527 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8528 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8529 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8529 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30_HD8530 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8531 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8532 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8533 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8533 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD8534 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8535 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8536 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8537 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8537 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24_HD8538 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8539 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8540 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8541 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8541 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14_HD8542 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15_HD8543 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16_HD8544 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17_HD8545 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18_HD8546 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19_HD8547 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20_HD8548 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21_HD8549 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8550 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8551 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8552 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8552 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD8553 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8554 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8555 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8556 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8556 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD8557 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8558 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8559 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8560 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8560 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD8561 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8562 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8563 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8564 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8564 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3_HD8565 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD8566 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8567 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8568 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8569 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8569 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_HD8570 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD8571 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8572 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8573 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8574 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8574 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD8575 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd_HD8576 | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.channel_fifo_vio | data_fifo_vio_HD9395 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.channel_fifo_vio) | data_fifo_vio_HD9395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | data_fifo_vio_vio_v3_0_22_vio_HD9396 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | data_fifo_vio_vio_v3_0_22_vio_HD9396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | data_fifo_vio_vio_v3_0_22_decoder_HD9397 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | data_fifo_vio_vio_v3_0_22_probe_in_one_HD9398 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | data_fifo_vio_vio_v3_0_22_probe_out_all_HD9399 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | data_fifo_vio_vio_v3_0_22_probe_out_all_HD9399 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | data_fifo_vio_vio_v3_0_22_probe_out_one_HD9400 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | data_fifo_vio_xsdbs_v1_0_2_xsdbs_HD9401 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_in_ila | aurora_fifo_in_ila_HD9419 | 1417(0.41%) | 1199(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (chan_dbg.tob_fifo_in_ila) | aurora_fifo_in_ila_HD9419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_in_ila_ila_v6_2_12_ila_HD9420 | 1417(0.41%) | 1199(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | aurora_fifo_in_ila_ila_v6_2_12_ila_HD9420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_core_HD9421 | 1416(0.41%) | 1198(0.35%) | 0(0.00%) | 218(0.13%) | 2096(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_in_ila_ila_v6_2_12_ila_core_HD9421 | 42(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.02%) | 125(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_trace_memory_HD9422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_HD9423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_synth_HD9424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD9425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD9426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD9427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD9428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD9429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD9430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD9431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD9432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9433 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9433 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD9434 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7_HD9435 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7__1_HD9436 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen_HD9437 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen_HD9437 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__1_HD9438 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter_HD9439 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter_HD9439 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4__1_HD9440 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__1_HD9441 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6_HD9442 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__1_HD9443 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75_HD9444 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75_HD9444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76_HD9445 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76_HD9445 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_77_HD9446 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_78_HD9447 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter_HD9448 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter_HD9448 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4_HD9449 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5_HD9450 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__2_HD9451 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay_HD9452 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9453 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9454 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9454 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD9455 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD9456 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__2_HD9457 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71_HD9458 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71_HD9458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72_HD9459 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72_HD9459 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_73_HD9460 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_74_HD9461 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_in_ila_ila_v6_2_12_ila_register_HD9462 | 1056(0.30%) | 1055(0.30%) | 0(0.00%) | 1(0.01%) | 1486(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_in_ila_ila_v6_2_12_ila_register_HD9462 | 351(0.10%) | 350(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s_HD9463 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD9464 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD9465 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD9466 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized12_HD9467 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized13_HD9468 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized14_HD9469 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized15_HD9470 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD9471 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD9472 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD9473 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD9474 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD9475 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD9476 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD9477 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD9478 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD9479 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized16_HD9480 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_in_ila_xsdbs_v1_0_2_xsdbs_HD9481 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized58_HD9482 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_67_HD9483 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized59_HD9484 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_66_HD9485 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized60_HD9486 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_65_HD9487 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized61_HD9488 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_64_HD9489 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized62_HD9490 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_63_HD9491 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized63_HD9492 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_62_HD9493 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized43_HD9494 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_70_HD9495 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized44_HD9496 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD9497 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized45_HD9498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_69_HD9499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized64_HD9500 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_61_HD9501 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized65_HD9502 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_60_HD9503 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized66_HD9504 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD9505 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized67_HD9506 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_59_HD9507 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized68_HD9508 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_58_HD9509 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized69_HD9510 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_57_HD9511 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized71_HD9512 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_56_HD9513 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized73_HD9514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_55_HD9515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76_HD9516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76_HD9516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_54_HD9517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized46_HD9518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_68_HD9519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized17_HD9520 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream_HD9521 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_HD9522 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9523 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9523 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_HD9524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl_HD9525 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl_HD9525 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection_HD9526 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__2_HD9527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__3_HD9528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__1_HD9529 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer_HD9530 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection__1_HD9531 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger_HD9532 | 168(0.05%) | 42(0.01%) | 0(0.00%) | 126(0.07%) | 218(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger_HD9532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_in_ila_ltlib_v1_0_0_match_HD9533 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_in_ila_ltlib_v1_0_0_match_HD9533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_HD9534 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_HD9534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_HD9535 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_HD9535 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_51_HD9536 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_52_HD9537 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_53_HD9538 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match_HD9539 | 154(0.04%) | 41(0.01%) | 0(0.00%) | 113(0.06%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match_HD9539 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1_HD9540 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1_HD9540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48_HD9541 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48_HD9541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49_HD9542 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49_HD9542 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_50_HD9543 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10_HD9544 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10_HD9544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14_HD9545 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14_HD9545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15_HD9546 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15_HD9546 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD9547 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11_HD9548 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11_HD9548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9549 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9550 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9550 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD9551 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12_HD9552 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12_HD9552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9553 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9554 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9554 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD9555 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13_HD9556 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13_HD9556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9557 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9558 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9558 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD9559 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14_HD9560 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14_HD9560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2_HD9561 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2_HD9561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3_HD9562 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3_HD9562 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD9563 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0_HD9564 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0_HD9564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9565 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0_HD9566 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0_HD9566 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD9567 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2_HD9568 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2_HD9568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9569 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9570 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9570 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD9571 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2_HD9572 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2_HD9572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45_HD9573 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45_HD9573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46_HD9574 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46_HD9574 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_47_HD9575 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3_HD9576 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3_HD9576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42_HD9577 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42_HD9577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43_HD9578 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43_HD9578 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_44_HD9579 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1_HD9580 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1_HD9580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9581 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9582 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9582 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_HD9583 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_35_HD9584 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_36_HD9585 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_37_HD9586 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_38_HD9587 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_39_HD9588 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_40_HD9589 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_41_HD9590 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4_HD9591 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4_HD9591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32_HD9592 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32_HD9592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33_HD9593 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33_HD9593 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD9594 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5_HD9595 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5_HD9595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD9596 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD9596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30_HD9597 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30_HD9597 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_31_HD9598 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6_HD9599 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6_HD9599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26_HD9600 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26_HD9600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27_HD9601 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27_HD9601 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD9602 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7_HD9603 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7_HD9603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23_HD9604 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23_HD9604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24_HD9605 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24_HD9605 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD9606 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8_HD9607 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8_HD9607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20_HD9608 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20_HD9608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21_HD9609 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21_HD9609 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD9610 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9_HD9611 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9_HD9611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17_HD9612 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17_HD9612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18_HD9613 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18_HD9613 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD9614 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_in_ila_ltlib_v1_0_0_generic_memrd_HD9615 | 63(0.02%) | 61(0.02%) | 0(0.00%) | 2(0.01%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_out_ila | aurora_fifo_out_ila_HD8577 | 1143(0.33%) | 950(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.tob_fifo_out_ila) | aurora_fifo_out_ila_HD8577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8578 | 1143(0.33%) | 950(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8578 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8579 | 1142(0.33%) | 949(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8579 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory_HD8580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_HD8581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth_HD8582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD8583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD8584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD8585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD8586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD8587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD8588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD8589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD8590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8591 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8591 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD8592 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7_HD8593 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1_HD8594 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8595 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8595 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1_HD8596 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8597 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8597 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1_HD8598 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1_HD8599 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6_HD8600 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1_HD8601 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8602 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8603 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8603 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57_HD8604 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58_HD8605 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8606 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8606 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4_HD8607 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5_HD8608 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2_HD8609 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay_HD8610 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8611 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8612 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8612 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD8613 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD8614 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2_HD8615 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8616 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8617 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8617 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53_HD8618 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54_HD8619 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8620 | 797(0.23%) | 796(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8620 | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s_HD8621 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD8622 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD8623 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD8624 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD8625 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD8626 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD8627 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD8628 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD8629 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD8630 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD8631 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs_HD8632 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44_HD8633 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47_HD8634 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45_HD8635 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46_HD8636 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46_HD8637 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45_HD8638 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47_HD8639 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44_HD8640 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48_HD8641 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43_HD8642 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49_HD8643 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42_HD8644 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29_HD8645 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50_HD8646 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30_HD8647 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD8648 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31_HD8649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49_HD8650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50_HD8651 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41_HD8652 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51_HD8653 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40_HD8654 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52_HD8655 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD8656 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53_HD8657 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39_HD8658 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54_HD8659 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38_HD8660 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55_HD8661 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37_HD8662 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57_HD8663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36_HD8664 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59_HD8665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35_HD8666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34_HD8668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32_HD8669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48_HD8670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD8671 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream_HD8672 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_HD8673 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8674 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8674 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_HD8675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8676 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8676 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection_HD8677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2_HD8678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3_HD8679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1_HD8680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer_HD8681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1_HD8682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8683 | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8684 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8685 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8686 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8686 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32_HD8687 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD8688 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8689 | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8689 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8690 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8691 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8692 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8692 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30_HD8693 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8694 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8695 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8696 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8696 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD8697 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8698 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8699 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8700 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8700 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24_HD8701 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8702 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8703 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8704 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8704 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14_HD8705 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15_HD8706 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16_HD8707 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17_HD8708 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18_HD8709 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19_HD8710 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20_HD8711 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21_HD8712 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8713 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8714 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8715 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8715 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD8716 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8717 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8718 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8719 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8719 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD8720 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8721 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8722 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8723 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8723 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD8724 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8725 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8726 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8727 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8727 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3_HD8728 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD8729 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8730 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8731 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8732 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8732 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_HD8733 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD8734 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8735 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8736 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8737 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8737 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD8738 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd_HD8739 | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__15 | 843(0.24%) | 843(0.24%) | 0(0.00%) | 0(0.00%) | 1437(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__15 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1718 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1719 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1781 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1720 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1780 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1721 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1779 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1722 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1723 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1724 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1778 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1725 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1777 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1726 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1776 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1727 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1728 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1775 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1729 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1774 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1730 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1731 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1773 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1732 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1733 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1772 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1734 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1771 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1735 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1770 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1736 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1769 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1737 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1738 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1768 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1739 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1740 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1767 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1741 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1742 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1766 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1743 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1744 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1765 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1745 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1746 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1764 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1747 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1748 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1749 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1761 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1762 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1763 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1750 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1760 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1751 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1752 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1753 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1754 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1755 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1756 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1757 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1758 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1759 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized25 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized25 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1715 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1716 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__26 | 184(0.05%) | 180(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5063 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5064 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5065 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5066 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5067 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5068 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5068 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5069 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5070 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5071 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5072 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5077 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5078 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5080 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5080 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5084 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5085 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5086 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5087 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5088 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5089 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5089 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5090 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5091 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5091 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6823 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6824 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6825 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6825 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6826 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6827 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6828 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6829 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6830 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6831 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6833 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6834 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6835 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6835 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6836 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6839 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6840 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6840 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6841 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6842 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6843 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6844 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6859 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6859 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6860 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6861 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6861 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6863 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__25 | 181(0.05%) | 177(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5030 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5031 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5032 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5033 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5034 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5035 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5035 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5036 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5037 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5038 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5039 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5041 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5044 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5045 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5047 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5047 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5049 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5050 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5051 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5052 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5053 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5054 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5055 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5056 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5056 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5057 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5058 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5058 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6781 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6782 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6783 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6783 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6784 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6785 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6786 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6787 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6788 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6789 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6791 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6792 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6793 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6793 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6794 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6796 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6797 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6798 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6798 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6799 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6800 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6801 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6802 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6817 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6817 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6819 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6819 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6821 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__16 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__14 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch14 | channel_fifo__parameterized27 | 5192(1.50%) | 4580(1.32%) | 0(0.00%) | 612(0.35%) | 8868(1.28%) | 26(2.20%) | 1(0.04%) | 0(0.00%) | | (gen_jfex_chan.ch14) | channel_fifo__parameterized27 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.calo_fifo_out_ila | aurora_fifo_out_ila_HD8740 | 1142(0.33%) | 949(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.calo_fifo_out_ila) | aurora_fifo_out_ila_HD8740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8741 | 1142(0.33%) | 949(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8741 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8742 | 1141(0.33%) | 948(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8742 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory_HD8743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_HD8744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth_HD8745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD8746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD8747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD8748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD8749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD8750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD8751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD8752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD8753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8754 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8754 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD8755 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7_HD8756 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1_HD8757 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8758 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8758 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1_HD8759 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8760 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8760 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1_HD8761 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1_HD8762 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6_HD8763 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1_HD8764 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8765 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8766 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8766 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57_HD8767 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58_HD8768 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8769 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8769 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4_HD8770 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5_HD8771 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2_HD8772 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay_HD8773 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8774 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8775 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8775 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD8776 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD8777 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2_HD8778 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8779 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8780 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8780 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53_HD8781 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54_HD8782 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8783 | 796(0.23%) | 795(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8783 | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s_HD8784 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD8785 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD8786 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD8787 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD8788 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD8789 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD8790 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD8791 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD8792 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD8793 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD8794 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs_HD8795 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44_HD8796 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47_HD8797 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45_HD8798 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46_HD8799 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46_HD8800 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45_HD8801 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47_HD8802 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44_HD8803 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48_HD8804 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43_HD8805 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49_HD8806 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42_HD8807 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29_HD8808 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50_HD8809 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30_HD8810 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD8811 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31_HD8812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49_HD8813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50_HD8814 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41_HD8815 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51_HD8816 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40_HD8817 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52_HD8818 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD8819 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53_HD8820 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39_HD8821 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54_HD8822 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38_HD8823 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55_HD8824 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37_HD8825 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57_HD8826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36_HD8827 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59_HD8828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35_HD8829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34_HD8831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32_HD8832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48_HD8833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD8834 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream_HD8835 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_HD8836 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8837 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD8837 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_HD8838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8839 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD8839 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection_HD8840 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2_HD8841 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3_HD8842 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1_HD8843 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer_HD8844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1_HD8845 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8846 | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD8846 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8847 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD8847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8848 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD8848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8849 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD8849 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32_HD8850 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD8851 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8852 | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD8852 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8853 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD8853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8854 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD8854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8855 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD8855 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30_HD8856 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8857 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD8857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8858 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD8858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8859 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD8859 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD8860 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8861 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD8861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8862 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD8862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8863 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD8863 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24_HD8864 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8865 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD8865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8866 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD8866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8867 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD8867 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14_HD8868 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15_HD8869 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16_HD8870 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17_HD8871 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18_HD8872 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19_HD8873 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20_HD8874 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21_HD8875 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8876 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD8876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8877 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD8877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8878 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD8878 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD8879 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8880 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD8880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8881 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD8881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8882 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD8882 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD8883 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8884 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD8884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8885 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD8885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8886 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD8886 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD8887 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8888 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD8888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8889 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD8889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8890 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD8890 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3_HD8891 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD8892 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8893 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD8893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8894 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD8894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8895 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD8895 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_HD8896 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD8897 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8898 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD8898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8899 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD8899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8900 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD8900 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD8901 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd_HD8902 | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.channel_fifo_vio | data_fifo_vio_HD9402 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.channel_fifo_vio) | data_fifo_vio_HD9402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | data_fifo_vio_vio_v3_0_22_vio_HD9403 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | data_fifo_vio_vio_v3_0_22_vio_HD9403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | data_fifo_vio_vio_v3_0_22_decoder_HD9404 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | data_fifo_vio_vio_v3_0_22_probe_in_one_HD9405 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | data_fifo_vio_vio_v3_0_22_probe_out_all_HD9406 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | data_fifo_vio_vio_v3_0_22_probe_out_all_HD9406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | data_fifo_vio_vio_v3_0_22_probe_out_one_HD9407 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | data_fifo_vio_xsdbs_v1_0_2_xsdbs_HD9408 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_in_ila | aurora_fifo_in_ila_HD9616 | 1422(0.41%) | 1204(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (chan_dbg.tob_fifo_in_ila) | aurora_fifo_in_ila_HD9616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_in_ila_ila_v6_2_12_ila_HD9617 | 1422(0.41%) | 1204(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | aurora_fifo_in_ila_ila_v6_2_12_ila_HD9617 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_core_HD9618 | 1421(0.41%) | 1203(0.35%) | 0(0.00%) | 218(0.13%) | 2096(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_in_ila_ila_v6_2_12_ila_core_HD9618 | 42(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.02%) | 125(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_trace_memory_HD9619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_HD9620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_synth_HD9621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD9622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD9623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD9624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD9625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD9626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD9627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD9628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD9629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9630 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9630 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD9631 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7_HD9632 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7__1_HD9633 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen_HD9634 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen_HD9634 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__1_HD9635 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter_HD9636 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter_HD9636 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4__1_HD9637 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__1_HD9638 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6_HD9639 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__1_HD9640 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75_HD9641 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75_HD9641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76_HD9642 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76_HD9642 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_77_HD9643 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_78_HD9644 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter_HD9645 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter_HD9645 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4_HD9646 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5_HD9647 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__2_HD9648 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay_HD9649 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9650 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9651 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9651 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD9652 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD9653 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__2_HD9654 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71_HD9655 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71_HD9655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72_HD9656 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72_HD9656 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_73_HD9657 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_74_HD9658 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_in_ila_ila_v6_2_12_ila_register_HD9659 | 1061(0.31%) | 1060(0.31%) | 0(0.00%) | 1(0.01%) | 1486(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_in_ila_ila_v6_2_12_ila_register_HD9659 | 351(0.10%) | 350(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s_HD9660 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD9661 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD9662 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD9663 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized12_HD9664 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized13_HD9665 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized14_HD9666 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized15_HD9667 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD9668 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD9669 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD9670 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD9671 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD9672 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD9673 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD9674 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD9675 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD9676 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized16_HD9677 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_in_ila_xsdbs_v1_0_2_xsdbs_HD9678 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized58_HD9679 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_67_HD9680 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized59_HD9681 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_66_HD9682 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized60_HD9683 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_65_HD9684 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized61_HD9685 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_64_HD9686 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized62_HD9687 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_63_HD9688 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized63_HD9689 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_62_HD9690 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized43_HD9691 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_70_HD9692 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized44_HD9693 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD9694 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized45_HD9695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_69_HD9696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized64_HD9697 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_61_HD9698 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized65_HD9699 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_60_HD9700 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized66_HD9701 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD9702 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized67_HD9703 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_59_HD9704 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized68_HD9705 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_58_HD9706 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized69_HD9707 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_57_HD9708 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized71_HD9709 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_56_HD9710 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized73_HD9711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_55_HD9712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76_HD9713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76_HD9713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_54_HD9714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized46_HD9715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_68_HD9716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized17_HD9717 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream_HD9718 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_HD9719 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9720 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9720 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_HD9721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl_HD9722 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl_HD9722 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection_HD9723 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__2_HD9724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__3_HD9725 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__1_HD9726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer_HD9727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection__1_HD9728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger_HD9729 | 168(0.05%) | 42(0.01%) | 0(0.00%) | 126(0.07%) | 218(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger_HD9729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_in_ila_ltlib_v1_0_0_match_HD9730 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_in_ila_ltlib_v1_0_0_match_HD9730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_HD9731 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_HD9731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_HD9732 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_HD9732 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_51_HD9733 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_52_HD9734 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_53_HD9735 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match_HD9736 | 154(0.04%) | 41(0.01%) | 0(0.00%) | 113(0.06%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match_HD9736 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1_HD9737 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1_HD9737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48_HD9738 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48_HD9738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49_HD9739 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49_HD9739 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_50_HD9740 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10_HD9741 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10_HD9741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14_HD9742 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14_HD9742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15_HD9743 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15_HD9743 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD9744 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11_HD9745 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11_HD9745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9746 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9747 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9747 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD9748 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12_HD9749 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12_HD9749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9750 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9751 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9751 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD9752 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13_HD9753 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13_HD9753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9754 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9755 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9755 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD9756 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14_HD9757 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14_HD9757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2_HD9758 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2_HD9758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3_HD9759 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3_HD9759 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD9760 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0_HD9761 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0_HD9761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9762 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0_HD9763 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0_HD9763 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD9764 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2_HD9765 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2_HD9765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9766 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9767 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9767 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD9768 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2_HD9769 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2_HD9769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45_HD9770 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45_HD9770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46_HD9771 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46_HD9771 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_47_HD9772 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3_HD9773 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3_HD9773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42_HD9774 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42_HD9774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43_HD9775 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43_HD9775 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_44_HD9776 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1_HD9777 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1_HD9777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9778 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9779 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9779 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_HD9780 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_35_HD9781 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_36_HD9782 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_37_HD9783 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_38_HD9784 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_39_HD9785 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_40_HD9786 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_41_HD9787 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4_HD9788 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4_HD9788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32_HD9789 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32_HD9789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33_HD9790 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33_HD9790 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD9791 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5_HD9792 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5_HD9792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD9793 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD9793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30_HD9794 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30_HD9794 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_31_HD9795 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6_HD9796 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6_HD9796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26_HD9797 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26_HD9797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27_HD9798 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27_HD9798 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD9799 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7_HD9800 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7_HD9800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23_HD9801 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23_HD9801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24_HD9802 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24_HD9802 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD9803 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8_HD9804 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8_HD9804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20_HD9805 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20_HD9805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21_HD9806 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21_HD9806 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD9807 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9_HD9808 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9_HD9808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17_HD9809 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17_HD9809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18_HD9810 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18_HD9810 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD9811 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_in_ila_ltlib_v1_0_0_generic_memrd_HD9812 | 63(0.02%) | 61(0.02%) | 0(0.00%) | 2(0.01%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_out_ila | aurora_fifo_out_ila_HD8903 | 1139(0.33%) | 946(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.tob_fifo_out_ila) | aurora_fifo_out_ila_HD8903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8904 | 1139(0.33%) | 946(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila_HD8904 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8905 | 1138(0.33%) | 945(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD8905 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory_HD8906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_HD8907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth_HD8908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD8909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD8910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD8911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD8912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD8913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD8914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD8915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD8916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8917 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD8917 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD8918 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7_HD8919 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1_HD8920 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8921 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD8921 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1_HD8922 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8923 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD8923 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1_HD8924 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1_HD8925 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6_HD8926 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1_HD8927 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8928 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD8928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8929 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD8929 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57_HD8930 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58_HD8931 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8932 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD8932 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4_HD8933 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5_HD8934 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2_HD8935 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay_HD8936 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8937 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD8937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8938 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD8938 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD8939 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD8940 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2_HD8941 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8942 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD8942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8943 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD8943 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53_HD8944 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54_HD8945 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8946 | 793(0.23%) | 792(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD8946 | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s_HD8947 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD8948 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD8949 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD8950 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD8951 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD8952 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD8953 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD8954 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD8955 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD8956 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD8957 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs_HD8958 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44_HD8959 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47_HD8960 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45_HD8961 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46_HD8962 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46_HD8963 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45_HD8964 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47_HD8965 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44_HD8966 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48_HD8967 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43_HD8968 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49_HD8969 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42_HD8970 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29_HD8971 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50_HD8972 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30_HD8973 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD8974 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31_HD8975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49_HD8976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50_HD8977 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41_HD8978 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51_HD8979 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40_HD8980 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52_HD8981 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD8982 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53_HD8983 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39_HD8984 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54_HD8985 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38_HD8986 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55_HD8987 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37_HD8988 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57_HD8989 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36_HD8990 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59_HD8991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35_HD8992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD8993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34_HD8994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32_HD8995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48_HD8996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD8997 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream_HD8998 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_HD8999 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9000 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9000 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_HD9001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD9002 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD9002 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection_HD9003 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2_HD9004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3_HD9005 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1_HD9006 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer_HD9007 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1_HD9008 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD9009 | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD9009 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD9010 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD9010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD9011 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD9011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD9012 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD9012 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32_HD9013 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD9014 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD9015 | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD9015 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD9016 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD9016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD9017 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD9017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD9018 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD9018 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30_HD9019 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD9020 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD9020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD9021 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD9021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD9022 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD9022 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD9023 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD9024 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD9024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD9025 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD9025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD9026 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD9026 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24_HD9027 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD9028 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD9028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9029 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9030 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9030 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14_HD9031 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15_HD9032 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16_HD9033 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17_HD9034 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18_HD9035 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19_HD9036 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20_HD9037 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21_HD9038 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD9039 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD9039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9040 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9041 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9041 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD9042 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD9043 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD9043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9044 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9045 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9045 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD9046 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD9047 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD9047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9048 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9049 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9049 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD9050 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD9051 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD9051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD9052 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD9052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD9053 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD9053 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3_HD9054 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD9055 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD9056 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD9056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9057 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD9058 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD9058 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_HD9059 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD9060 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD9061 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD9061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9062 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9063 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9063 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD9064 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd_HD9065 | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__parameterized2 | 842(0.24%) | 842(0.24%) | 0(0.00%) | 0(0.00%) | 1437(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__parameterized2 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1583 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1584 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1585 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1645 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1586 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1644 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1587 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1643 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1588 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1589 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1590 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1642 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1591 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1641 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1592 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1640 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1593 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1594 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1639 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1595 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1638 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1596 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1597 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1637 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1598 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1599 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1636 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1600 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1635 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1601 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1634 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1602 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1633 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1603 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1604 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1632 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1605 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1606 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1631 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1607 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1608 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1630 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1609 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1610 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1629 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1611 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1612 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1628 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1613 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1614 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init__parameterized1 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1626 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset__parameterized1 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1627 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1615 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1625 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1616 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1617 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1618 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1619 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1620 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1621 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1622 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1623 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1624 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized27 | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized27 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1646 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1647 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__28 | 181(0.05%) | 177(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5129 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5130 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5131 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5132 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5133 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5134 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5134 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5135 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5136 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5137 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5138 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5140 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5141 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5143 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5144 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5146 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5146 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5148 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5149 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5150 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5151 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5152 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5153 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5154 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5155 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5155 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5156 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5157 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5157 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6907 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6908 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6909 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6909 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6910 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6911 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6912 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6913 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6914 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6915 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6917 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6918 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6919 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6919 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6922 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6923 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6924 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6924 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6925 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6926 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6927 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6928 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6943 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6943 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6944 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6945 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6945 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6947 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__27 | 180(0.05%) | 176(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5096 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5097 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5098 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5099 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5100 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5101 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5101 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5102 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5103 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5104 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5105 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5107 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5108 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5110 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5111 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5113 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5113 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5115 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5116 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5117 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5118 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5119 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5120 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5121 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5122 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5122 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5123 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5124 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5124 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6865 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6866 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6867 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6867 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6868 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6869 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6870 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6871 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6872 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6873 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6875 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6876 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6877 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6877 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6878 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6880 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6881 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6882 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6882 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6883 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6884 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6885 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6886 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6901 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6901 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6902 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6903 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6903 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6905 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__26 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch15 | channel_fifo__parameterized29 | 5184(1.50%) | 4572(1.32%) | 0(0.00%) | 612(0.35%) | 8868(1.28%) | 26(2.20%) | 1(0.04%) | 0(0.00%) | | (gen_jfex_chan.ch15) | channel_fifo__parameterized29 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.calo_fifo_out_ila | aurora_fifo_out_ila_HD9066 | 1141(0.33%) | 948(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.calo_fifo_out_ila) | aurora_fifo_out_ila_HD9066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila_HD9067 | 1141(0.33%) | 948(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila_HD9067 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD9068 | 1140(0.33%) | 947(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD9068 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory_HD9069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_HD9070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth_HD9071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD9072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD9073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD9074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD9075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD9076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD9077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD9078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD9079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9080 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9080 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD9081 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7_HD9082 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1_HD9083 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD9084 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD9084 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1_HD9085 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD9086 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD9086 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1_HD9087 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1_HD9088 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6_HD9089 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1_HD9090 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD9091 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD9091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD9092 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD9092 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57_HD9093 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58_HD9094 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD9095 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD9095 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4_HD9096 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5_HD9097 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2_HD9098 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay_HD9099 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9100 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9101 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9101 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD9102 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD9103 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2_HD9104 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD9105 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD9105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD9106 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD9106 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53_HD9107 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54_HD9108 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD9109 | 795(0.23%) | 794(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD9109 | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s_HD9110 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD9111 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD9112 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD9113 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD9114 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD9115 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD9116 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD9117 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD9118 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD9119 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD9120 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs_HD9121 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44_HD9122 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47_HD9123 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45_HD9124 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46_HD9125 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46_HD9126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45_HD9127 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47_HD9128 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44_HD9129 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48_HD9130 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43_HD9131 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49_HD9132 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42_HD9133 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29_HD9134 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50_HD9135 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30_HD9136 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD9137 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31_HD9138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49_HD9139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50_HD9140 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41_HD9141 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51_HD9142 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40_HD9143 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52_HD9144 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD9145 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53_HD9146 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39_HD9147 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54_HD9148 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38_HD9149 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55_HD9150 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37_HD9151 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57_HD9152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36_HD9153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59_HD9154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35_HD9155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD9156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD9156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34_HD9157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32_HD9158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48_HD9159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD9160 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream_HD9161 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_HD9162 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9163 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9163 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_HD9164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD9165 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD9165 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection_HD9166 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2_HD9167 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3_HD9168 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1_HD9169 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer_HD9170 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1_HD9171 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD9172 | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD9172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD9173 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD9173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD9174 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD9174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD9175 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD9175 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32_HD9176 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD9177 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD9178 | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD9178 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD9179 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD9179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD9180 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD9180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD9181 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD9181 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30_HD9182 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD9183 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD9183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD9184 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD9184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD9185 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD9185 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD9186 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD9187 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD9187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD9188 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD9188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD9189 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD9189 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24_HD9190 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD9191 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD9191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9192 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9193 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9193 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14_HD9194 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15_HD9195 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16_HD9196 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17_HD9197 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18_HD9198 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19_HD9199 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20_HD9200 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21_HD9201 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD9202 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD9202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9203 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9204 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9204 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD9205 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD9206 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD9206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9207 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9208 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9208 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD9209 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD9210 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD9210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9211 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9212 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9212 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD9213 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD9214 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD9214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD9215 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD9215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD9216 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD9216 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3_HD9217 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD9218 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD9219 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD9219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9220 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD9221 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD9221 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_HD9222 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD9223 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD9224 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD9224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9225 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9226 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9226 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD9227 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd_HD9228 | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.channel_fifo_vio | data_fifo_vio_HD9409 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.channel_fifo_vio) | data_fifo_vio_HD9409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | data_fifo_vio_vio_v3_0_22_vio_HD9410 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | data_fifo_vio_vio_v3_0_22_vio_HD9410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | data_fifo_vio_vio_v3_0_22_decoder_HD9411 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | data_fifo_vio_vio_v3_0_22_probe_in_one_HD9412 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | data_fifo_vio_vio_v3_0_22_probe_out_all_HD9413 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | data_fifo_vio_vio_v3_0_22_probe_out_all_HD9413 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | data_fifo_vio_vio_v3_0_22_probe_out_one_HD9414 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | data_fifo_vio_xsdbs_v1_0_2_xsdbs_HD9415 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_in_ila | aurora_fifo_in_ila_HD9813 | 1422(0.41%) | 1204(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (chan_dbg.tob_fifo_in_ila) | aurora_fifo_in_ila_HD9813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_in_ila_ila_v6_2_12_ila_HD9814 | 1422(0.41%) | 1204(0.35%) | 0(0.00%) | 218(0.13%) | 2102(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | aurora_fifo_in_ila_ila_v6_2_12_ila_HD9814 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_core_HD9815 | 1421(0.41%) | 1203(0.35%) | 0(0.00%) | 218(0.13%) | 2096(0.30%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_in_ila_ila_v6_2_12_ila_core_HD9815 | 42(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.02%) | 125(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_in_ila_ila_v6_2_12_ila_trace_memory_HD9816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_HD9817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_synth_HD9818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD9819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD9820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD9821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD9822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD9823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD9824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD9825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_in_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD9826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9827 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9827 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD9828 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7_HD9829 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut7__1_HD9830 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen_HD9831 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_addrgen_HD9831 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6__1_HD9832 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter_HD9833 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_sample_counter_HD9833 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4__1_HD9834 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__1_HD9835 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut6_HD9836 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__1_HD9837 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75_HD9838 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_75_HD9838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76_HD9839 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_76_HD9839 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_77_HD9840 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_78_HD9841 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter_HD9842 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_in_ila_ila_v6_2_12_ila_cap_window_counter_HD9842 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut4_HD9843 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5_HD9844 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_in_ila_ltlib_v1_0_0_cfglut5__2_HD9845 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay_HD9846 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9847 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9848 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9848 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD9849 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD9850 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_in_ila_ltlib_v1_0_0_match_nodelay__2_HD9851 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71_HD9852 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_nodelay_71_HD9852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72_HD9853 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized2_72_HD9853 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_73_HD9854 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_74_HD9855 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_in_ila_ila_v6_2_12_ila_register_HD9856 | 1061(0.31%) | 1060(0.31%) | 0(0.00%) | 1(0.01%) | 1486(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_in_ila_ila_v6_2_12_ila_register_HD9856 | 352(0.10%) | 351(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s_HD9857 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD9858 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD9859 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD9860 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized12_HD9861 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized13_HD9862 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized14_HD9863 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized15_HD9864 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD9865 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD9866 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD9867 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD9868 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD9869 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD9870 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD9871 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD9872 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD9873 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized16_HD9874 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_in_ila_xsdbs_v1_0_2_xsdbs_HD9875 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized58_HD9876 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_67_HD9877 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized59_HD9878 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_66_HD9879 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized60_HD9880 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_65_HD9881 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized61_HD9882 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_64_HD9883 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized62_HD9884 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_63_HD9885 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized63_HD9886 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_62_HD9887 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized43_HD9888 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_70_HD9889 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized44_HD9890 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD9891 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized45_HD9892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_69_HD9893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized64_HD9894 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_61_HD9895 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized65_HD9896 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_60_HD9897 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized66_HD9898 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD9899 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized67_HD9900 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_59_HD9901 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized68_HD9902 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_58_HD9903 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized69_HD9904 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_57_HD9905 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized71_HD9906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_56_HD9907 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized73_HD9908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_55_HD9909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76_HD9910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized76_HD9910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_54_HD9911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_in_ila_xsdbs_v1_0_2_reg__parameterized46_HD9912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_68_HD9913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_p2s__parameterized17_HD9914 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream_HD9915 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_ctl_HD9916 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9917 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9917 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_in_ila_xsdbs_v1_0_2_reg_stat_HD9918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl_HD9919 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_in_ila_ila_v6_2_12_ila_reset_ctrl_HD9919 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection_HD9920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__2_HD9921 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__3_HD9922 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer__1_HD9923 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_in_ila_ltlib_v1_0_0_async_edge_xfer_HD9924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_in_ila_ltlib_v1_0_0_rising_edge_detection__1_HD9925 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger_HD9926 | 168(0.05%) | 42(0.01%) | 0(0.00%) | 126(0.07%) | 218(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_in_ila_ila_v6_2_12_ila_trigger_HD9926 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_in_ila_ltlib_v1_0_0_match_HD9927 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_in_ila_ltlib_v1_0_0_match_HD9927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_HD9928 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA_HD9928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_HD9929 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_HD9929 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_51_HD9930 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_52_HD9931 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_53_HD9932 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match_HD9933 | 154(0.04%) | 41(0.01%) | 0(0.00%) | 113(0.06%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_in_ila_ila_v6_2_12_ila_trig_match_HD9933 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1_HD9934 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__1_HD9934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48_HD9935 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_48_HD9935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49_HD9936 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_49_HD9936 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_50_HD9937 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10_HD9938 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__10_HD9938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14_HD9939 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_14_HD9939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15_HD9940 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_15_HD9940 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD9941 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11_HD9942 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__11_HD9942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9943 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9944 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9944 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD9945 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12_HD9946 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__12_HD9946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9947 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9948 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9948 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD9949 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13_HD9950 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__13_HD9950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9951 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9952 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9952 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD9953 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14_HD9954 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__14_HD9954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2_HD9955 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_2_HD9955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3_HD9956 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_3_HD9956 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD9957 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0_HD9958 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0_HD9958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9959 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0_HD9960 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_0_HD9960 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD9961 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2_HD9962 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized2_HD9962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9963 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9964 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9964 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD9965 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2_HD9966 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__2_HD9966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45_HD9967 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_45_HD9967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46_HD9968 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_46_HD9968 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_47_HD9969 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3_HD9970 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__3_HD9970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42_HD9971 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_42_HD9971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43_HD9972 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_43_HD9972 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_44_HD9973 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1_HD9974 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized1_HD9974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9975 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9976 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9976 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_HD9977 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_35_HD9978 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_36_HD9979 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_37_HD9980 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_38_HD9981 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_39_HD9982 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice_40_HD9983 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_41_HD9984 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4_HD9985 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__4_HD9985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32_HD9986 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_32_HD9986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33_HD9987 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_33_HD9987 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD9988 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5_HD9989 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__5_HD9989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD9990 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD9990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30_HD9991 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_30_HD9991 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_31_HD9992 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6_HD9993 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__6_HD9993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26_HD9994 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_26_HD9994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27_HD9995 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_27_HD9995 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD9996 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7_HD9997 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__7_HD9997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23_HD9998 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_23_HD9998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24_HD9999 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_24_HD9999 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD10000 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8_HD10001 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__8_HD10001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20_HD10002 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_20_HD10002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21_HD10003 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_21_HD10003 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD10004 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9_HD10005 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_in_ila_ltlib_v1_0_0_match__parameterized0__9_HD10005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17_HD10006 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_in_ila_ltlib_v1_0_0_allx_typeA__parameterized0_17_HD10006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18_HD10007 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA__parameterized0_18_HD10007 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_in_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD10008 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_in_ila_ltlib_v1_0_0_generic_memrd_HD10009 | 63(0.02%) | 61(0.02%) | 0(0.00%) | 2(0.01%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_dbg.tob_fifo_out_ila | aurora_fifo_out_ila_HD9229 | 1139(0.33%) | 946(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (chan_dbg.tob_fifo_out_ila) | aurora_fifo_out_ila_HD9229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_fifo_out_ila_ila_v6_2_12_ila_HD9230 | 1139(0.33%) | 946(0.27%) | 0(0.00%) | 193(0.11%) | 1819(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_fifo_out_ila_ila_v6_2_12_ila_HD9230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD9231 | 1138(0.33%) | 945(0.27%) | 0(0.00%) | 193(0.11%) | 1813(0.26%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | aurora_fifo_out_ila_ila_v6_2_12_ila_core_HD9231 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 136(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | aurora_fifo_out_ila_ila_v6_2_12_ila_trace_memory_HD9232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_HD9233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_synth_HD9234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD9235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD9236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD9237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD9238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD9239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD9240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD9241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_fifo_out_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD9242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9243 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD9243 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD9244 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7_HD9245 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut7__1_HD9246 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD9247 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_addrgen_HD9247 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6__1_HD9248 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD9249 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_sample_counter_HD9249 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4__1_HD9250 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__1_HD9251 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut6_HD9252 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__1_HD9253 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD9254 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_55_HD9254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD9255 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_56_HD9255 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_57_HD9256 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_58_HD9257 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD9258 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | aurora_fifo_out_ila_ila_v6_2_12_ila_cap_window_counter_HD9258 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut4_HD9259 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5_HD9260 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | aurora_fifo_out_ila_ltlib_v1_0_0_cfglut5__2_HD9261 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay_HD9262 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9263 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD9263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9264 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD9264 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD9265 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD9266 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | aurora_fifo_out_ila_ltlib_v1_0_0_match_nodelay__2_HD9267 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD9268 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_nodelay_51_HD9268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD9269 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized2_52_HD9269 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_53_HD9270 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_54_HD9271 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD9272 | 793(0.23%) | 792(0.23%) | 0(0.00%) | 1(0.01%) | 1180(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | aurora_fifo_out_ila_ila_v6_2_12_ila_register_HD9272 | 303(0.09%) | 302(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s_HD9273 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD9274 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD9275 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD9276 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD9277 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD9278 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD9279 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD9280 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD9281 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD9282 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD9283 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | aurora_fifo_out_ila_xsdbs_v1_0_2_xsdbs_HD9284 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized44_HD9285 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_47_HD9286 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized45_HD9287 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_46_HD9288 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized46_HD9289 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_45_HD9290 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized47_HD9291 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_44_HD9292 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized48_HD9293 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_43_HD9294 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized49_HD9295 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_42_HD9296 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized29_HD9297 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_50_HD9298 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized30_HD9299 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD9300 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized31_HD9301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_49_HD9302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized50_HD9303 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_41_HD9304 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized51_HD9305 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_40_HD9306 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized52_HD9307 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD9308 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized53_HD9309 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_39_HD9310 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized54_HD9311 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_38_HD9312 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized55_HD9313 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_37_HD9314 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized57_HD9315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_36_HD9316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized59_HD9317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_35_HD9318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD9319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized62_HD9319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_34_HD9320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | aurora_fifo_out_ila_xsdbs_v1_0_2_reg__parameterized32_HD9321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_48_HD9322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD9323 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream_HD9324 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_ctl_HD9325 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9326 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD9326 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | aurora_fifo_out_ila_xsdbs_v1_0_2_reg_stat_HD9327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD9328 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | aurora_fifo_out_ila_ila_v6_2_12_ila_reset_ctrl_HD9328 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection_HD9329 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__2_HD9330 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__3_HD9331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer__1_HD9332 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | aurora_fifo_out_ila_ltlib_v1_0_0_async_edge_xfer_HD9333 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | aurora_fifo_out_ila_ltlib_v1_0_0_rising_edge_detection__1_HD9334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD9335 | 143(0.04%) | 48(0.01%) | 0(0.00%) | 95(0.05%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | aurora_fifo_out_ila_ila_v6_2_12_ila_trigger_HD9335 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD9336 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | aurora_fifo_out_ila_ltlib_v1_0_0_match_HD9336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD9337 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA_HD9337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD9338 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_31_HD9338 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_32_HD9339 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD9340 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD9341 | 133(0.04%) | 47(0.01%) | 0(0.00%) | 86(0.05%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | aurora_fifo_out_ila_ila_v6_2_12_ila_trig_match_HD9341 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD9342 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__1_HD9342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD9343 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD9343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD9344 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_29_HD9344 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_30_HD9345 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD9346 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__2_HD9346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD9347 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_25_HD9347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD9348 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_26_HD9348 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD9349 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD9350 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__3_HD9350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD9351 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_22_HD9351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD9352 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_23_HD9352 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24_HD9353 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD9354 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized1_HD9354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9355 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD9355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9356 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD9356 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_14_HD9357 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_15_HD9358 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_16_HD9359 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_17_HD9360 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_18_HD9361 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_19_HD9362 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_20_HD9363 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_21_HD9364 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD9365 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__4_HD9365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9366 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD9366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9367 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_12_HD9367 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_13_HD9368 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD9369 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__5_HD9369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9370 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_8_HD9370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9371 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_9_HD9371 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD9372 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD9373 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0__6_HD9373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9374 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_5_HD9374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9375 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_6_HD9375 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD9376 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD9377 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2__1_HD9377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD9378 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_1_HD9378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD9379 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_2_HD9379 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_3_HD9380 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD9381 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD9382 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized2_HD9382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9383 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized2_HD9383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD9384 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_HD9384 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice_HD9385 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD9386 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD9387 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | aurora_fifo_out_ila_ltlib_v1_0_0_match__parameterized0_HD9387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9388 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | aurora_fifo_out_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD9388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9389 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD9389 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | aurora_fifo_out_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD9390 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | aurora_fifo_out_ila_ltlib_v1_0_0_generic_memrd_HD9391 | 67(0.02%) | 65(0.02%) | 0(0.00%) | 2(0.01%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__2 | 839(0.24%) | 839(0.24%) | 0(0.00%) | 0(0.00%) | 1437(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__2 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1651 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1652 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1714 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1653 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1713 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1654 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1712 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1655 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1656 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1657 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1711 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1658 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1710 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1659 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1709 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1660 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1661 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1708 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1662 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1707 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1663 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1664 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1706 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1665 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1666 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1705 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1667 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1704 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1668 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1703 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1669 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1702 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1670 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1671 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1701 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1672 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1673 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1700 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1674 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1675 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1699 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1676 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1677 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1698 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1678 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1679 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1697 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1680 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1681 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1682 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1694 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1695 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1696 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1683 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1693 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1684 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1685 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_1686 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1687 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1688 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1689 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1690 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1691 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1692 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized29 | 105(0.03%) | 105(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized29 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1648 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1649 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__30 | 179(0.05%) | 175(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5195 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5196 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5197 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5198 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5199 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5200 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5200 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5201 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5202 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5203 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5204 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5209 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5210 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5212 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5212 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5215 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5216 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5217 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5218 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5219 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5220 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5221 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5221 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5222 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5223 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5223 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6991 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6992 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6993 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6993 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6994 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6995 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6996 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6997 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6998 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6999 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7001 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7002 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7003 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7003 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7006 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7007 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7008 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7008 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7009 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7010 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7011 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7012 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7027 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7027 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7028 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7029 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7029 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7031 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__29 | 181(0.05%) | 177(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5162 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5163 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5164 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5165 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5166 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5167 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5167 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5168 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5169 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5170 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5171 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5173 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5174 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5176 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5177 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5179 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5179 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5182 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5183 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5184 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5185 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5186 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5187 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5188 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5188 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5189 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5190 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5190 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6949 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6950 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6951 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6951 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6952 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6953 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6954 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6955 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6956 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6957 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6959 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6960 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6961 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6961 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6962 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6964 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6965 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6966 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6966 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6967 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6968 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6969 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6970 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6985 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6985 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6986 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6987 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6987 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6989 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__17 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__15 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch16 | channel_fifo__parameterized31 | 1409(0.41%) | 1401(0.40%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch16) | channel_fifo__parameterized31 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__16 | 838(0.24%) | 838(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__16 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_681 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_682 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_744 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_683 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_743 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_684 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_742 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_685 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_686 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_687 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_741 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_688 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_740 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_689 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_739 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_690 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_691 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_738 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_692 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_737 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_693 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_694 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_736 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_695 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_696 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_735 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_697 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_734 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_698 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_733 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_699 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_732 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_700 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_701 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_731 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_702 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_703 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_730 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_704 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_705 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_729 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_706 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_707 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_728 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_708 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_709 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_727 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_710 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_711 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_712 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_724 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_725 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_726 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_713 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_723 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_714 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_715 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_716 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_717 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_718 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_719 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_720 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_721 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_722 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized31 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized31 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_678 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_679 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__32 | 182(0.05%) | 178(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5327 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5328 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5329 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5330 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5331 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5332 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5332 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5333 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5334 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5335 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5336 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5338 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5339 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5341 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5342 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5344 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5344 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5347 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5348 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5349 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5350 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5351 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5352 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5353 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5353 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5354 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5355 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5355 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7159 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7160 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7161 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7161 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7162 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7163 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7164 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7165 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7166 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7167 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7169 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7170 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7171 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7171 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7174 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7175 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7176 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7176 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7177 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7178 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7179 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7180 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7195 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7195 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7196 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7197 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7197 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7199 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__31 | 183(0.05%) | 179(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5294 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5295 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5296 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5297 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5298 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5299 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5299 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5300 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5301 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5302 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5303 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5305 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5306 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5308 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5309 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5311 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5311 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5313 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5314 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5315 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5316 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5317 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5318 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5319 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5320 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5320 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5321 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5322 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5322 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7117 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7118 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7119 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7119 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7120 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7121 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7122 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7123 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7124 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7125 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7127 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7128 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7129 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7129 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7130 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7132 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7133 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7134 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7134 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7135 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7136 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7137 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7138 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7153 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7153 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7155 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7155 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7157 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__18 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__16 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch17 | channel_fifo__parameterized33 | 1383(0.40%) | 1375(0.40%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch17) | channel_fifo__parameterized33 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__17 | 838(0.24%) | 838(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__17 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_613 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_614 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_615 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_677 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_616 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_676 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_617 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_675 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_618 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_619 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_620 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_674 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_621 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_673 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_622 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_672 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_623 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_624 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_671 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_625 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_670 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_626 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_627 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_669 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_628 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_629 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_668 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_630 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_667 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_631 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_666 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_632 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_665 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_634 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_664 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_635 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_636 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_663 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_637 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_638 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_662 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_639 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_640 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_661 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_641 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_642 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_660 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_643 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_644 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_645 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_657 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_658 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_659 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_646 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_656 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_647 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_648 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_649 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_650 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_651 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_652 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_653 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_654 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_655 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized33 | 111(0.03%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized33 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_611 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_612 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__34 | 182(0.05%) | 178(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5393 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5394 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5395 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5396 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5397 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5398 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5398 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5399 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5400 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5401 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5402 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5404 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5405 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5407 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5408 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5410 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5410 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5412 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5413 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5414 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5415 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5416 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5417 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5418 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5419 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5419 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5421 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5421 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7243 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7244 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7245 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7245 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7246 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7247 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7248 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7249 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7250 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7251 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7253 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7254 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7255 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7255 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7256 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7258 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7259 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7260 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7260 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7261 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7262 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7263 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7264 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7279 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7279 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7280 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7281 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7281 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7283 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__33 | 182(0.05%) | 178(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5360 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5361 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5362 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5363 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5364 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5365 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5365 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5366 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5367 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5368 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5369 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5372 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5374 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5375 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5377 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5377 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5379 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5380 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5381 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5382 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5383 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5384 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5385 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5386 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5386 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5387 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5388 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5388 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7201 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7202 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7203 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7203 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7204 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7205 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7206 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7207 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7211 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7212 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7213 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7213 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7216 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7217 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7218 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7218 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7219 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7220 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7221 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7222 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7237 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7237 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7239 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7239 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7241 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__19 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__17 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch18 | channel_fifo__parameterized35 | 1368(0.39%) | 1360(0.39%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch18) | channel_fifo__parameterized35 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__18 | 835(0.24%) | 835(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__18 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_547 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_548 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_610 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_549 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_609 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_550 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_608 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_551 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_552 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_553 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_607 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_554 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_606 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_555 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_605 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_556 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_557 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_604 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_558 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_603 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_559 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_560 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_602 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_561 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_562 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_601 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_563 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_600 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_564 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_599 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_565 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_598 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_566 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_567 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_597 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_568 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_569 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_596 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_570 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_571 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_595 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_572 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_573 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_594 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_574 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_575 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_593 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_576 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_577 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_578 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_590 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_591 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_592 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_579 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_589 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_580 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_581 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_582 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_583 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_584 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_585 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_586 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_587 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_588 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized35 | 111(0.03%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized35 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_544 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_545 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__36 | 183(0.05%) | 179(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5459 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5460 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5461 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5462 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5463 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5464 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5464 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5465 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5466 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5467 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5468 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5470 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5471 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5473 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5474 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5476 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5476 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5478 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5479 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5480 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5481 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5482 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5483 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5484 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5485 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5485 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5486 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5487 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5487 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7327 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7328 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7329 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7329 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7330 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7331 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7332 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7333 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7335 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7337 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7338 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7339 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7339 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7340 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7342 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7343 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7344 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7344 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7345 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7346 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7347 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7348 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7363 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7363 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7365 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7365 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7367 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__35 | 184(0.05%) | 180(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5426 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5427 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5428 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5429 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5430 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5431 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5431 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5432 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5433 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5434 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5435 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5437 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5438 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5440 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5441 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5443 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5443 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5445 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5446 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5447 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5448 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5449 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5450 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5451 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5452 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5452 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5454 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5454 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7285 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7286 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7287 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7287 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7288 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7289 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7290 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7291 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7292 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7293 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7295 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7296 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7297 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7297 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7300 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7301 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7302 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7302 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7303 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7304 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7305 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7306 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7321 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7321 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7323 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7323 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7325 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__20 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__18 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch19 | channel_fifo__parameterized37 | 1384(0.40%) | 1376(0.40%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch19) | channel_fifo__parameterized37 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__19 | 837(0.24%) | 837(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__19 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_479 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_480 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_481 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_543 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_482 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_542 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_483 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_541 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_484 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_485 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_486 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_540 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_487 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_539 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_488 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_538 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_489 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_490 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_537 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_491 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_536 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_492 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_493 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_535 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_494 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_495 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_534 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_496 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_533 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_497 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_532 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_498 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_531 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_500 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_530 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_501 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_502 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_529 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_503 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_504 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_528 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_505 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_506 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_527 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_507 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_508 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_526 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_509 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_510 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_511 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_523 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_524 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_525 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_512 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_522 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_513 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_514 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_515 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_516 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_517 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_518 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_519 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_520 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_521 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized37 | 111(0.03%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized37 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_477 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_478 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__38 | 182(0.05%) | 178(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5525 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5526 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5527 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5528 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5529 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5530 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5530 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5531 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5532 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5533 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5534 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5536 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5537 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5539 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5540 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5542 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5542 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5545 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5546 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5547 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5548 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5549 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5550 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5551 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5551 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5553 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5553 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7411 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7412 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7413 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7413 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7414 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7415 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7416 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7417 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7418 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7419 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7421 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7422 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7423 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7423 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7426 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7427 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7428 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7428 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7429 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7430 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7431 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7432 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7447 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7447 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7448 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7449 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7449 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7451 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__37 | 182(0.05%) | 178(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5492 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5493 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5494 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5495 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5496 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5497 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5497 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5498 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5499 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5500 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5501 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5503 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5504 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5506 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5507 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5509 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5509 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5511 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5512 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5513 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5514 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5515 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5516 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5517 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5518 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5518 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5519 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5520 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5520 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7369 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7370 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7371 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7371 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7372 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7373 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7374 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7375 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7376 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7377 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7379 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7380 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7381 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7381 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7382 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7384 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7385 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7386 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7386 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7387 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7388 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7389 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7390 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7405 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7405 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7407 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7407 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7409 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__21 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__19 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch20 | channel_fifo__parameterized39 | 1388(0.40%) | 1380(0.40%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch20) | channel_fifo__parameterized39 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__20 | 833(0.24%) | 833(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__20 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_412 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_413 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_414 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_476 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_415 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_475 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_416 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_474 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_417 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_418 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_419 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_473 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_420 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_472 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_421 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_471 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_422 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_423 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_470 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_424 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_469 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_425 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_426 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_468 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_427 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_428 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_467 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_429 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_466 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_430 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_465 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_431 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_464 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_433 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_463 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_434 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_435 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_462 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_436 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_437 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_461 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_438 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_439 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_460 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_440 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_441 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_459 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_442 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_443 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_444 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_456 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_457 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_458 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_445 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_455 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_446 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_447 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_448 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_449 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_450 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_451 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_452 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_453 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_454 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized39 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized39 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_410 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_411 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__40 | 182(0.05%) | 178(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5591 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5592 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5593 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5594 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5595 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5596 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5596 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5597 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5598 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5599 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5600 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5602 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5603 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5605 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5606 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5608 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5608 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5610 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5611 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5612 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5613 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5614 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5615 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5616 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5617 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5617 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5618 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5619 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5619 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7495 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7496 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7497 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7497 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7498 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7499 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7500 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7501 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7502 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7503 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7505 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7506 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7507 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7507 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7508 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7510 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7511 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7512 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7512 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7513 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7514 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7515 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7516 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7531 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7531 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7533 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7533 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7535 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__39 | 180(0.05%) | 176(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5558 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5559 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5560 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5561 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5562 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5563 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5563 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5564 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5565 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5566 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5567 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5569 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5572 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5573 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5575 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5575 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5577 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5578 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5579 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5580 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5581 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5582 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5583 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5584 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5584 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5585 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5586 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5586 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7453 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7454 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7455 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7455 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7456 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7457 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7458 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7459 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7460 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7461 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7463 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7464 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7465 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7465 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7466 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7468 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7469 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7470 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7470 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7471 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7472 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7473 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7474 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7489 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7489 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7490 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7491 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7491 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7493 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__22 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__20 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch21 | channel_fifo__parameterized41 | 1375(0.40%) | 1367(0.39%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch21) | channel_fifo__parameterized41 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__21 | 833(0.24%) | 833(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__21 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_346 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_347 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_409 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_348 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_408 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_349 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_407 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_350 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_351 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_352 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_406 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_353 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_405 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_354 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_404 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_355 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_356 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_403 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_357 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_402 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_358 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_359 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_401 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_360 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_361 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_400 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_362 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_399 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_363 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_398 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_364 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_397 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_365 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_366 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_396 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_367 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_368 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_395 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_369 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_370 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_394 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_371 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_372 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_393 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_373 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_374 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_392 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_375 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_376 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_377 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_389 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_390 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_391 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_378 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_388 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_379 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_380 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_381 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_382 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_383 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_384 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_385 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_386 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_387 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized41 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized41 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_343 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_344 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__42 | 183(0.05%) | 179(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5657 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5658 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5659 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5660 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5661 | 88(0.03%) | 85(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5662 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5662 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5663 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5664 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5665 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5666 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5671 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5672 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5674 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5674 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5677 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5678 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5679 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5680 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5681 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5682 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5683 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5683 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5684 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5685 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5685 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7579 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7580 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7581 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7581 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7582 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7583 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7584 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7585 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7586 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7587 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7589 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7590 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7591 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7591 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7594 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7595 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7596 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7596 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7597 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7598 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7599 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7600 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7615 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7615 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7616 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7617 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7617 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7619 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__41 | 182(0.05%) | 178(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5624 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5625 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5626 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5627 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5628 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5629 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5629 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5630 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5631 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5632 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5633 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5635 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5636 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5638 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5639 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5641 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5641 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5643 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5644 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5645 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5646 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5647 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5648 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5649 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5650 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5650 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5651 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5652 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5652 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7537 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7538 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7539 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7539 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7540 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7541 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7542 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7543 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7545 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7547 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7548 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7549 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7549 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7550 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7553 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7554 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7554 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7555 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7556 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7557 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7558 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7573 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7573 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7574 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7575 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7575 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7577 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__23 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__21 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch22 | channel_fifo__parameterized43 | 1357(0.39%) | 1349(0.39%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch22) | channel_fifo__parameterized43 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs__22 | 834(0.24%) | 834(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs__22 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_278 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_279 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_280 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_342 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_281 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_341 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_282 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_340 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_283 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_284 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_285 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_339 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_286 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_338 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_287 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_337 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_288 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_289 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_336 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_290 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_335 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_291 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_292 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_334 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_293 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_294 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_333 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_295 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_332 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_296 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_331 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_297 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_330 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_299 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_329 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_300 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_301 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_328 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_302 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_303 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_327 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_304 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_305 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_326 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_306 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_307 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_325 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_308 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_309 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_310 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_322 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_323 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_324 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_311 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_321 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_312 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_313 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_314 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_315 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_316 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_317 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_318 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_319 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_320 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized43 | 111(0.03%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized43 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_276 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_277 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__44 | 181(0.05%) | 177(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5723 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5724 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5725 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5726 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5727 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5728 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5728 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5729 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5730 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5731 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5732 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5737 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5738 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5740 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5740 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5743 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5744 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5745 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5746 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5747 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5748 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5749 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5749 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5750 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5751 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5751 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7663 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7664 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7665 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7665 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7666 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7667 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7668 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7669 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7670 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7673 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7674 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7675 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7675 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7679 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7680 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7680 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7681 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7682 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7683 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7684 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7699 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7699 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7700 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7701 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7701 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7703 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__43 | 181(0.05%) | 177(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5690 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5691 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5692 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5693 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5694 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5695 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5695 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5696 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5697 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5698 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5699 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5702 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5704 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5705 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5707 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5707 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5709 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5710 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5711 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5712 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5713 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5714 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5715 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5716 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5716 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5718 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5718 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7621 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7622 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7623 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7623 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7624 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7625 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7626 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7627 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7631 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7632 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7633 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7633 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7636 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7637 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7638 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7638 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7639 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7640 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7641 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7642 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7657 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7657 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7658 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7659 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7659 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7661 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__24 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__22 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_jfex_chan.ch23 | channel_fifo__parameterized45 | 1373(0.40%) | 1365(0.39%) | 0(0.00%) | 8(0.01%) | 2868(0.41%) | 18(1.53%) | 0(0.00%) | 0(0.00%) | | (gen_jfex_chan.ch23) | channel_fifo__parameterized45 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs | 836(0.24%) | 836(0.24%) | 0(0.00%) | 0(0.00%) | 1419(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_218 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_219 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_220 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_275 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_221 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_274 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_222 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_273 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_223 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_224 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_225 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_272 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_226 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_271 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_227 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_270 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_228 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_269 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_229 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_268 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_230 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_231 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_267 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_232 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_233 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_266 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_234 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_265 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_235 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_264 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_236 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_263 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_237 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_238 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_262 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_239 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_261 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_240 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_241 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_260 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_242 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_243 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_259 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_244 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_245 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_258 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_246 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_257 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_247 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_256 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_248 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_249 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_250 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_251 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_252 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_253 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_254 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_255 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe__parameterized45 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 413(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe__parameterized45 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_216 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_217 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k | 181(0.05%) | 177(0.05%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5756 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5757 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5758 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5759 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5760 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5761 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5761 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5762 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5763 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5764 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5765 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5767 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5768 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5770 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5771 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5773 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5773 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5775 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5776 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5777 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5778 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5779 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5780 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5781 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5782 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5782 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5783 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5784 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5784 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7705 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7706 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7707 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7707 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7708 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7709 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7710 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7711 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7715 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7716 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7717 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7717 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7718 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7721 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7722 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7722 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7723 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7724 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7725 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7726 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7741 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7741 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7743 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7743 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7745 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__45 | 181(0.05%) | 177(0.05%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD5789 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD5790 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD5791 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD5792 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD5793 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD5794 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD5794 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD5795 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD5796 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD5797 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD5798 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD5799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD5800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD5800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD5801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD5802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD5803 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD5804 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD5806 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD5806 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD5807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD5808 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD5809 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD5810 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD5810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD5811 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD5812 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD5813 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD5814 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD5815 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD5815 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD5816 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD5817 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD5817 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD5818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD5819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD5820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD5821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD7747 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD7748 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7749 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD7749 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD7750 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD7751 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD7752 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD7753 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD7754 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD7754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD7755 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD7756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD7757 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD7758 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD7759 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD7759 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD7760 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD7761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD7762 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD7763 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD7764 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD7764 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD7765 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD7766 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD7767 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD7768 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD7769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD7770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD7771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD7772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD7773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD7774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD7775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD7776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD7777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD7778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD7779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD7780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD7781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD7782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7783 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD7783 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD7784 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7785 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD7785 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD7786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD7787 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1__25 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx__23 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.registers | backplane_regs | 1242(0.36%) | 1242(0.36%) | 0(0.00%) | 0(0.00%) | 595(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.registers) | backplane_regs | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Backplane_control_reg_2_reg | ipbus_reg_v_197 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_busy_threshold_reg | ipbus_reg_v_198 | 216(0.06%) | 216(0.06%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_xoff_threshold_reg | ipbus_reg_v_199 | 216(0.06%) | 216(0.06%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Time_count_value | ipbus_syncreg_v_200 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Time_count_value) | ipbus_syncreg_v_200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_215 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_threshold_reg | ipbus_reg_v_201 | 217(0.06%) | 217(0.06%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_threshold_reg | ipbus_reg_v_202 | 263(0.08%) | 263(0.08%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | backplane_control_reg | ipbus_reg_v_203 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_active_time_reg | ipbus_syncreg_v_204 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (busy_active_time_reg) | ipbus_syncreg_v_204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_214 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_disable | ipbus_reg_v_205 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_map | ipbus_syncreg_v_206 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (channel_map) | ipbus_syncreg_v_206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_213 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_tester | clock_test_ipbus | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_status | ipbus_syncreg_v_207 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clock_status) | ipbus_syncreg_v_207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_212 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | first_last_chan | ipbus_syncreg_v_208 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (first_last_chan) | ipbus_syncreg_v_208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_211 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | first_last_encode | priority_encoder | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ro_ctrl_status | ipbus_syncreg_v_209 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ro_ctrl_status) | ipbus_syncreg_v_209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_210 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.ttc_regs | ttc_chan_regs | 516(0.15%) | 516(0.15%) | 0(0.00%) | 0(0.00%) | 888(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.ttc_regs) | ttc_chan_regs | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BCN_reg | ipbus_syncreg_v_153 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (BCN_reg) | ipbus_syncreg_v_153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_196 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CTTC_link_stat_reg | ipbus_syncreg_v_154 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (CTTC_link_stat_reg) | ipbus_syncreg_v_154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_195 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Duplicate_L1ID_Count_reg | ipbus_syncreg_v_155 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Duplicate_L1ID_Count_reg) | ipbus_syncreg_v_155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_194 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_Value_reg | ipbus_syncreg_v_156 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (L1ID_Value_reg) | ipbus_syncreg_v_156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_193 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1id_Capture_Status_reg | ipbus_syncreg_v_157 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (L1id_Capture_Status_reg) | ipbus_syncreg_v_157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_192 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1id_Continuity_Capture_Control | ipbus_reg_v_158 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Local_Counter_Miss_reg | ipbus_syncreg_v_159 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Local_Counter_Miss_reg) | ipbus_syncreg_v_159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_191 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Mismatch_err_reg | ipbus_syncreg_v_160 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Mismatch_err_reg) | ipbus_syncreg_v_160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_190 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_Miss_reg | ipbus_syncreg_v_161 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_Miss_reg) | ipbus_syncreg_v_161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_189 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_control_reg | ipbus_reg_v_162 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_busy_Count_reg | ipbus_syncreg_v_163 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_fifo_busy_Count_reg) | ipbus_syncreg_v_163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_188 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_busy_threshold_reg | ipbus_reg_v_164 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_control_reg | ipbus_reg_v_165 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_fill_level_reg | ipbus_syncreg_v_166 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_fifo_fill_level_reg) | ipbus_syncreg_v_166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_187 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_status_reg | ipbus_syncreg_v_167 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_fifo_status_reg) | ipbus_syncreg_v_167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_186 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_reset_register | ipbus_reg_v_168 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Timeout_threshold_reg | ipbus_reg_v_169 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_adjust_reg | ipbus_reg_v_170 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_err_counter | error_counter | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | disperity_err_counter | error_counter_171 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_count_reg | ipbus_syncreg_v_172 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_count_reg) | ipbus_syncreg_v_172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_185 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | felix_backpressure_reg | ipbus_syncreg_v_173 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (felix_backpressure_reg) | ipbus_syncreg_v_173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_184 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_reg | ipbus_syncreg_v_174 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (orbit_reg) | ipbus_syncreg_v_174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_183 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_header_info | ipbus_reg_v_175 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | table_err_counter | error_counter_176 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | total_event_count_msb | ipbus_syncreg_v_177 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (total_event_count_msb) | ipbus_syncreg_v_177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_182 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | total_event_count_reg | ipbus_syncreg_v_178 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (total_event_count_reg) | ipbus_syncreg_v_178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_181 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_busy_counter | threshold_counter_179 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_watermark | watermark_180 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | readout_controller | ro_controller | 1327(0.38%) | 1093(0.32%) | 0(0.00%) | 234(0.13%) | 2140(0.31%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (readout_controller) | ro_controller | 98(0.03%) | 98(0.03%) | 0(0.00%) | 0(0.00%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | readout_ctrl_ila2 | rod_ROctrl_mux_ila | 1136(0.33%) | 902(0.26%) | 0(0.00%) | 234(0.13%) | 1973(0.28%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (readout_ctrl_ila2) | rod_ROctrl_mux_ila | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | rod_ROctrl_mux_ila_ila_v6_2_12_ila | 1136(0.33%) | 902(0.26%) | 0(0.00%) | 234(0.13%) | 1973(0.28%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | rod_ROctrl_mux_ila_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | rod_ROctrl_mux_ila_ila_v6_2_12_ila_core | 1135(0.33%) | 901(0.26%) | 0(0.00%) | 234(0.13%) | 1967(0.28%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_core | 84(0.02%) | 0(0.00%) | 0(0.00%) | 84(0.05%) | 209(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | rod_ROctrl_mux_ila_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_52 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_53 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_53 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_54 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | rod_ROctrl_mux_ila_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | rod_ROctrl_mux_ila_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_48 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_49 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_49 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_50 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_51 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | rod_ROctrl_mux_ila_ila_v6_2_12_ila_register | 685(0.20%) | 684(0.20%) | 0(0.00%) | 1(0.01%) | 1050(0.15%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_register | 284(0.08%) | 283(0.08%) | 0(0.00%) | 1(0.01%) | 160(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | rod_ROctrl_mux_ila_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized23 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized24 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized51 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_33 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | rod_ROctrl_mux_ila_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trigger | 184(0.05%) | 84(0.02%) | 0(0.00%) | 100(0.06%) | 356(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | rod_ROctrl_mux_ila_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trig_match | 178(0.05%) | 83(0.02%) | 0(0.00%) | 95(0.05%) | 346(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trig_match | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_21 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_14 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_15 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_15 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_8 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_generic_memrd | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 191(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ro_crc | CRC__parameterized1 | 93(0.03%) | 93(0.03%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_processor_0 | tob_processor | 6906(1.99%) | 6517(1.88%) | 0(0.00%) | 389(0.22%) | 7923(1.14%) | 17(1.44%) | 1(0.04%) | 0(0.00%) | | (tob_processor_0) | tob_processor | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_in_gen | dummy_chan_in | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_builder_0 | ev_builder | 3993(1.15%) | 3604(1.04%) | 0(0.00%) | 389(0.22%) | 4397(0.63%) | 14(1.19%) | 1(0.04%) | 0(0.00%) | | (event_builder_0) | ev_builder | 508(0.15%) | 508(0.15%) | 0(0.00%) | 0(0.00%) | 547(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | State_machine_ILA | ila_ev_builder | 2159(0.62%) | 1770(0.51%) | 0(0.00%) | 389(0.22%) | 3238(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (State_machine_ILA) | ila_ev_builder | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ev_builder_ila_v6_2_12_ila | 2159(0.62%) | 1770(0.51%) | 0(0.00%) | 389(0.22%) | 3238(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_ev_builder_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ev_builder_ila_v6_2_12_ila_core | 2158(0.62%) | 1769(0.51%) | 0(0.00%) | 389(0.22%) | 3232(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_ev_builder_ila_v6_2_12_ila_core | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 259(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ev_builder_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ev_builder_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_ev_builder_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ev_builder_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ev_builder_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ev_builder_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ev_builder_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ev_builder_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ev_builder_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ev_builder_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ev_builder_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ev_builder_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ev_builder_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ev_builder_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ev_builder_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_117 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_118 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_118 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1_119 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2_120 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ev_builder_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ev_builder_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ev_builder_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_113 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_114 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_114 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1_115 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2_116 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ev_builder_ila_v6_2_12_ila_register | 1520(0.44%) | 1519(0.44%) | 0(0.00%) | 1(0.01%) | 2046(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ev_builder_ila_v6_2_12_ila_register | 416(0.12%) | 415(0.12%) | 0(0.00%) | 1(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[17].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[18].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized17 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[19].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized18 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[20].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized19 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[21].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized20 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[22].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized21 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[23].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized22 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[24].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized23 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[25].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized24 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[26].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized25 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[27].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized26 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[28].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized27 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[29].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized28 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized29 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ev_builder_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized84 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_109 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized85 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_108 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized86 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized87 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized88 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_105 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized89 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1_104 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_112 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized90 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1_103 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized91 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_102 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized92 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized93 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_101 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized94 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_100 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized95 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_99 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized97 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_98 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized30 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ev_builder_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ev_builder_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_ev_builder_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ev_builder_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ev_builder_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ev_builder_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ev_builder_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ev_builder_ila_v6_2_12_ila_trigger | 340(0.10%) | 109(0.03%) | 0(0.00%) | 231(0.13%) | 525(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ev_builder_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ev_builder_ltlib_v1_0_0_match | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ev_builder_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA_91 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA_91 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_92 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_93 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_94 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_95 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ev_builder_ila_v6_2_12_ila_trig_match | 322(0.09%) | 108(0.03%) | 0(0.00%) | 214(0.12%) | 492(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_ev_builder_ila_v6_2_12_ila_trig_match | 108(0.03%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_89 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_89 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_90 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_60 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_61 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_61 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_62 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_57 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_58 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_58 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_54 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_55 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_55 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_56 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_51 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_52 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_52 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_53 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized3 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized3 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized1 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_50 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_45 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_46 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_46 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_42 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_42 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[17].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[17].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_39 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_40 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_40 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[18].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__14 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[18].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_36 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_37 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_37 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[19].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[19].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_32 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_33 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_33 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_86 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_86 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_87 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_87 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_88 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[20].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[20].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_30 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[21].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[21].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[22].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__17 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[22].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[23].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[23].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[24].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[24].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_16 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_17 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_17 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[25].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized6 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[25].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized6 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized3 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[26].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[26].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_6 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[27].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[27].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[28].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[28].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[29].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized7 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[29].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized7 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_84 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_84 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_85 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_81 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_82 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_82 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_83 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_78 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_79 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_79 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_80 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_75 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_76 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_76 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_77 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_72 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_73 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_73 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_74 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_69 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_70 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_70 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_71 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_66 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_67 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_67 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_68 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_63 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_64 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_64 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_65 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ev_builder_ltlib_v1_0_0_generic_memrd | 103(0.03%) | 101(0.03%) | 0(0.00%) | 2(0.01%) | 241(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_trailer_crc | event_trailer_CRC20 | 197(0.06%) | 197(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_block | flx_CRC_151 | 197(0.06%) | 197(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_header_crc | hdr_in_crc9 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (channel_header_crc) | hdr_in_crc9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_152 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_crc20_gen | CRC_149 | 252(0.07%) | 252(0.07%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_crc9_gen | CRC__parameterized1_150 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_trailer_err_map | trailer_map | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | debug_fifo | event_builder_fifo | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | event_builder_fifo_axis_data_fifo_v2_0_8_top | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | event_builder_fifo_xpm_fifo_axis | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | event_builder_fifo_xpm_fifo_axis | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | event_builder_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | event_builder_fifo_xpm_fifo_base | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | event_builder_fifo_xpm_fifo_base | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | event_builder_fifo_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | event_builder_fifo_xpm_counter_updn__parameterized2 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | event_builder_fifo_xpm_fifo_reg_bit | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | event_builder_fifo_xpm_counter_updn__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | event_builder_fifo_xpm_fifo_rst | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_fifo | event_builder_fifo_HD10011 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | event_builder_fifo_axis_data_fifo_v2_0_8_top_HD10012 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | event_builder_fifo_xpm_fifo_axis_HD10013 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | event_builder_fifo_xpm_fifo_axis_HD10013 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | event_builder_fifo_xpm_cdc_sync_rst_HD10014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | event_builder_fifo_xpm_fifo_base_HD10015 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | event_builder_fifo_xpm_fifo_base_HD10015 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized1_HD10016 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | event_builder_fifo_xpm_memory_base_HD10017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_HD10018 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_HD10019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | event_builder_fifo_xpm_fifo_reg_bit_HD10020 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_0_HD10021 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_1_HD10022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | event_builder_fifo_xpm_counter_updn__parameterized0_HD10023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | event_builder_fifo_xpm_fifo_rst_HD10024 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9__3 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9__3 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32__15 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_trailer_crc | event_trailer_CRC20__2 | 371(0.11%) | 371(0.11%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_block | flx_CRC | 371(0.11%) | 371(0.11%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | evnt_trailer_err_map | trailer_map__1 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | timeout | tob_timeout | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wdog_timer | watchdog | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | tob_proc_regs | 1672(0.48%) | 1672(0.48%) | 0(0.00%) | 0(0.00%) | 3441(0.50%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | tob_proc_regs | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_capt | l1id_capture | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 426(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (l1id_capt) | l1id_capture | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.L1ID_Capture_Control_reg | ipbus_reg_v_138 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.L1ID_Capture_status_reg | ipbus_syncreg_v_139 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.L1ID_Capture_status_reg) | ipbus_syncreg_v_139 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_148 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_miss_reg | ipbus_syncreg_v_140 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_miss_reg) | ipbus_syncreg_v_140 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_147 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_last_reg | ipbus_syncreg_v_141 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_last_reg) | ipbus_syncreg_v_141 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_146 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_miss_reg | ipbus_syncreg_v_142 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_miss_reg) | ipbus_syncreg_v_142 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_145 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_penultimate_reg | ipbus_syncreg_v_143 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_penultimate_reg) | ipbus_syncreg_v_143 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_144 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Event_fifo_control_reg | ipbus_reg_v | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Event_fifo_reset_reg | ipbus_reg_v_40 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Full_mode_control_reg | ipbus_reg_v_41 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_busy_Count_reg | ipbus_syncreg_v | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_busy_Count_reg) | ipbus_syncreg_v | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_137 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_fifo_status_reg | ipbus_syncreg_v_42 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_fifo_status_reg) | ipbus_syncreg_v_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_136 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_xoff_Count_reg | ipbus_syncreg_v_43 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_xoff_Count_reg) | ipbus_syncreg_v_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_135 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_staging_fifo_resets_reg | ipbus_reg_v_44 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_timeout_reg | ipbus_ctrlreg_v__parameterized0 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.avg_event_time_reg | ipbus_syncreg_v_45 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.avg_event_time_reg) | ipbus_syncreg_v_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_134 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.bcn_mismatch_map_reg | ipbus_syncreg_v_46 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.bcn_mismatch_map_reg) | ipbus_syncreg_v_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_133 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.chan_error_mapper | chan_err_map | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.crc20_error_map_reg | ipbus_syncreg_v_47 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.crc20_error_map_reg) | ipbus_syncreg_v_47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_132 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.crc9_error_map_reg | ipbus_syncreg_v_48 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.crc9_error_map_reg) | ipbus_syncreg_v_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_131 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.dbg_pkt_count_reg | ipbus_syncreg_v_49 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.dbg_pkt_count_reg) | ipbus_syncreg_v_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_130 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.debug_fifo_fill_level_reg | ipbus_syncreg_v_50 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.debug_fifo_fill_level_reg) | ipbus_syncreg_v_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_129 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.debug_fifo_watermark | watermark | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.error_count_register | ipbus_syncreg_v_51 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.error_count_register) | ipbus_syncreg_v_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_128 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_52 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_127 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_fifo_watermark | watermark_53 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_proc_timer | event_timer | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_time_reg | ipbus_syncreg_v_54 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.event_time_reg) | ipbus_syncreg_v_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_126 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.flx_bp_time_reg | ipbus_syncreg_v_55 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.flx_bp_time_reg) | ipbus_syncreg_v_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_125 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fm_L1id_reg | ipbus_syncreg_v_56 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.fm_L1id_reg) | ipbus_syncreg_v_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_124 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fm_fifo_watermark | watermark_57 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.full_mode_status_reg | ipbus_syncreg_v_58 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.full_mode_status_reg) | ipbus_syncreg_v_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_123 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_59 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_122 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.input_capture | input_capture_regs | 318(0.09%) | 318(0.09%) | 0(0.00%) | 0(0.00%) | 650(0.09%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | Capture_Control_reg | ipbus_reg_v_107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Capture_status_reg | ipbus_syncreg_v_108 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Capture_status_reg) | ipbus_syncreg_v_108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_121 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Header_0_reg | ipbus_syncreg_v_109 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Header_0_reg) | ipbus_syncreg_v_109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_120 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Header_1_reg | ipbus_syncreg_v_110 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Header_1_reg) | ipbus_syncreg_v_110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_119 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Input_channel_select_reg | ipbus_reg_v_111 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | capture_lsw | ipbus_dpram | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | capture_msw | ipbus_dpram_112 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | input_capture_mech | input_capture | 142(0.04%) | 142(0.04%) | 0(0.00%) | 0(0.00%) | 350(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_capture_mech) | input_capture | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 177(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | packet_crc | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | packet_crc | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1__32 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pkt_count_reg | ipbus_syncreg_v_113 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (pkt_count_reg) | ipbus_syncreg_v_113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_118 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trailer_0_reg | ipbus_syncreg_v_114 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trailer_0_reg) | ipbus_syncreg_v_114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_117 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trailer_1_reg | ipbus_syncreg_v_115 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trailer_1_reg) | ipbus_syncreg_v_115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_116 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.l1id_mismatch_map_reg | ipbus_syncreg_v_60 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.l1id_mismatch_map_reg) | ipbus_syncreg_v_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_106 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.max_timeout_reg | ipbus_syncreg_v_61 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.max_timeout_reg) | ipbus_syncreg_v_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_105 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.packet_capture | pkt_capture_regs | 190(0.05%) | 190(0.05%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.packet_capture) | pkt_capture_regs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_90 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_91 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_91 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_104 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_92 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_92 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_103 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_93 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_93 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_102 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_94 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_94 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_101 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_95 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_95 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_100 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_96 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_99 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_97 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_98 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_max_wait_time_L1id_reg | ipbus_syncreg_v_62 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_max_wait_time_L1id_reg) | ipbus_syncreg_v_62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_89 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_wait_time_last_reg | ipbus_syncreg_v_63 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_wait_time_last_reg) | ipbus_syncreg_v_63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_88 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_wait_time_max_reg | ipbus_syncreg_v_64 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_wait_time_max_reg) | ipbus_syncreg_v_64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_87 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_65 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_86 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.stage_fifo_watermark | watermark_66 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.timeout_error_map_reg | ipbus_syncreg_v_67 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.timeout_error_map_reg) | ipbus_syncreg_v_67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_85 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_proc_reset_reg | ipbus_reg_v_68 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_proc_status | ipbus_syncreg_v_69 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.tob_proc_status) | ipbus_syncreg_v_69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_84 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_staging_control_reg | ipbus_reg_v_70 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_staging_thresholds_reg | ipbus_reg_v_71 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trace_module | Processor_trace_module | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 144(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | Trace_Control_reg | ipbus_reg_v_76 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Trigger_pattern_reg | ipbus_reg_v_77 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | proc_trace | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trace_mem | ipbus_dpram__parameterized2 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | trace_words_reg | ipbus_syncreg_v_78 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trace_words_reg) | ipbus_syncreg_v_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_83 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trigger_pointer_reg | ipbus_syncreg_v_79 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trigger_pointer_reg) | ipbus_syncreg_v_79 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_82 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trigger_status_reg | ipbus_syncreg_v_80 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trigger_status_reg) | ipbus_syncreg_v_80 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_81 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.watchdog_control_reg | ipbus_reg_v_72 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.watchdog_overflow_count_reg | ipbus_syncreg_v_73 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.watchdog_overflow_count_reg) | ipbus_syncreg_v_73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.wdog_overflow_counter | edge_error_counter__parameterized2 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.wdog_threshold_reg | ipbus_ctrlreg_v__parameterized1 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_busy_counter | threshold_counter | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_busy_flag | threshold_counter__parameterized0 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_xoff_counter | threshold_counter_74 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_xoff_flag | threshold_counter__parameterized0_75 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | channel_mux | 1217(0.35%) | 1217(0.35%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_input | ttc_info | 7422(2.14%) | 5135(1.48%) | 1328(0.76%) | 959(0.55%) | 9634(1.39%) | 15(1.27%) | 2(0.08%) | 0(0.00%) | | (ttc_input) | ttc_info | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_ttc_fifo | ttc_header_fifo | 850(0.25%) | 210(0.06%) | 640(0.37%) | 0(0.00%) | 310(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ttc_header_fifo_fifo_generator_v13_2_7 | 850(0.25%) | 210(0.06%) | 640(0.37%) | 0(0.00%) | 310(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | ttc_header_fifo_fifo_generator_v13_2_7_synth | 850(0.25%) | 210(0.06%) | 640(0.37%) | 0(0.00%) | 310(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | ttc_header_fifo_fifo_generator_top | 850(0.25%) | 210(0.06%) | 640(0.37%) | 0(0.00%) | 310(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | ttc_header_fifo_fifo_generator_ramfifo | 850(0.25%) | 210(0.06%) | 640(0.37%) | 0(0.00%) | 310(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | ttc_header_fifo_clk_x_pntrs | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | ttc_header_fifo_clk_x_pntrs | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | ttc_header_fifo_rd_logic | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | ttc_header_fifo_rd_fwft | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | ttc_header_fifo_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | ttc_header_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | ttc_header_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | ttc_header_fifo_compare_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | ttc_header_fifo_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | ttc_header_fifo_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | ttc_header_fifo_wr_logic | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | ttc_header_fifo_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | ttc_header_fifo_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | ttc_header_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | ttc_header_fifo_compare_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | ttc_header_fifo_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | ttc_header_fifo_memory | 760(0.22%) | 120(0.03%) | 640(0.37%) | 0(0.00%) | 120(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | ttc_header_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | ttc_header_fifo_dmem | 760(0.22%) | 120(0.03%) | 640(0.37%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | ttc_header_fifo_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | ttc_header_fifo_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | ttc_header_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | ttc_header_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cttc_crc | osum_crc9d32 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_bulk_ttc_fifo | ila_bulk_ttc | 1233(0.36%) | 1068(0.31%) | 0(0.00%) | 165(0.09%) | 1814(0.26%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_bulk_ttc_fifo) | ila_bulk_ttc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_bulk_ttc_ila_v6_2_12_ila | 1233(0.36%) | 1068(0.31%) | 0(0.00%) | 165(0.09%) | 1814(0.26%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_bulk_ttc_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_bulk_ttc_ila_v6_2_12_ila_core | 1232(0.36%) | 1067(0.31%) | 0(0.00%) | 165(0.09%) | 1808(0.26%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_bulk_ttc_ila_v6_2_12_ila_core | 24(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 89(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_bulk_ttc_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_bulk_ttc_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_bulk_ttc_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_bulk_ttc_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_bulk_ttc_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_bulk_ttc_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_bulk_ttc_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_bulk_ttc_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_bulk_ttc_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_bulk_ttc_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_bulk_ttc_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_bulk_ttc_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_bulk_ttc_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_bulk_ttc_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_bulk_ttc_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_bulk_ttc_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_bulk_ttc_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_bulk_ttc_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_bulk_ttc_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_bulk_ttc_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_bulk_ttc_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_bulk_ttc_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_bulk_ttc_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA_nodelay_60 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA_nodelay_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized2_61 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized2_61 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized1_62 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized2_63 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_bulk_ttc_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_bulk_ttc_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_bulk_ttc_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_bulk_ttc_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_bulk_ttc_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_bulk_ttc_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_bulk_ttc_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA_nodelay_56 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA_nodelay_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized2_57 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized2_57 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized1_58 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized2_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_bulk_ttc_ila_v6_2_12_ila_register | 958(0.28%) | 957(0.28%) | 0(0.00%) | 1(0.01%) | 1352(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_bulk_ttc_ila_v6_2_12_ila_register | 341(0.10%) | 340(0.10%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_bulk_ttc_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl__parameterized1_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_bulk_ttc_xsdbs_v1_0_2_reg_stat_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl__parameterized1_46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl_42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_bulk_ttc_xsdbs_v1_0_2_reg_stat_41 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_bulk_ttc_xsdbs_v1_0_2_reg_stat_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_bulk_ttc_xsdbs_v1_0_2_reg_stat_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_bulk_ttc_xsdbs_v1_0_2_reg__parameterized40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_bulk_ttc_xsdbs_v1_0_2_reg_stat_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_bulk_ttc_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_bulk_ttc_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_bulk_ttc_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_bulk_ttc_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_bulk_ttc_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_bulk_ttc_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_bulk_ttc_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_bulk_ttc_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_bulk_ttc_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_bulk_ttc_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_bulk_ttc_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_bulk_ttc_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_bulk_ttc_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_bulk_ttc_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_bulk_ttc_ila_v6_2_12_ila_trigger | 115(0.03%) | 24(0.01%) | 0(0.00%) | 91(0.05%) | 137(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_bulk_ttc_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_bulk_ttc_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_bulk_ttc_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_36 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_36 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_bulk_ttc_ila_v6_2_12_ila_trig_match | 105(0.03%) | 23(0.01%) | 0(0.00%) | 82(0.05%) | 120(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_bulk_ttc_ila_v6_2_12_ila_trig_match | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_34 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_34 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized3 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized3 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized1 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_32 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_25 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_22 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_20 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_20 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_21 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_17 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_17 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_14 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_14 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_11 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_bulk_ttc_ltlib_v1_0_0_match__parameterized1__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_bulk_ttc_ltlib_v1_0_0_allx_typeA__parameterized1_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_bulk_ttc_ltlib_v1_0_0_all_typeA__parameterized0_8 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_bulk_ttc_ltlib_v1_0_0_all_typeA_slice__parameterized0_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_bulk_ttc_ltlib_v1_0_0_generic_memrd | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_ttc_fifo_in | ila_ttc_in | 1670(0.48%) | 1314(0.38%) | 0(0.00%) | 356(0.20%) | 2755(0.40%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | (ila_ttc_fifo_in) | ila_ttc_in | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ttc_in_ila_v6_2_12_ila | 1670(0.48%) | 1314(0.38%) | 0(0.00%) | 356(0.20%) | 2755(0.40%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_ttc_in_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ttc_in_ila_v6_2_12_ila_core | 1669(0.48%) | 1313(0.38%) | 0(0.00%) | 356(0.20%) | 2749(0.40%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_ttc_in_ila_v6_2_12_ila_core | 124(0.04%) | 0(0.00%) | 0(0.00%) | 124(0.07%) | 288(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ttc_in_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ttc_in_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_ttc_in_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ttc_in_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ttc_in_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ttc_in_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ttc_in_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ttc_in_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ttc_in_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ttc_in_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ttc_in_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ttc_in_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ttc_in_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ttc_in_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ttc_in_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ttc_in_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ttc_in_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_83 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_84 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_84 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized1_85 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized2_86 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ttc_in_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ttc_in_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ttc_in_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ttc_in_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ttc_in_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ttc_in_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ttc_in_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_79 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_80 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_80 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized1_81 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized2_82 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ttc_in_ila_v6_2_12_ila_register | 1057(0.31%) | 1056(0.30%) | 0(0.00%) | 1(0.01%) | 1486(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ttc_in_ila_v6_2_12_ila_register | 352(0.10%) | 351(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ttc_in_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_75 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_74 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_73 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_72 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized1_70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_78 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized1_69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized17 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ttc_in_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ttc_in_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_ttc_in_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ttc_in_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ttc_in_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ttc_in_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ttc_in_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ttc_in_ila_v6_2_12_ila_trigger | 306(0.09%) | 124(0.04%) | 0(0.00%) | 182(0.10%) | 544(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ttc_in_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ttc_in_ltlib_v1_0_0_match | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ttc_in_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA_58 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA_58 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_60 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_61 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ttc_in_ila_v6_2_12_ila_trig_match | 292(0.08%) | 123(0.04%) | 0(0.00%) | 169(0.10%) | 524(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_ttc_in_ila_v6_2_12_ila_trig_match | 123(0.04%) | 123(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_56 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_56 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_57 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_15 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_16 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized7__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized7__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7_4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized7 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_53 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_54 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_54 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_50 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_51 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_51 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_52 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_44 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_44 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_42 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_42 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_39 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_39 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_33 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_34 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_34 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_27 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_28 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_21 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_22 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ttc_in_ltlib_v1_0_0_generic_memrd | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_ttc_fifo_out | ila_ttc_out | 1024(0.30%) | 857(0.25%) | 0(0.00%) | 167(0.10%) | 1675(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_ttc_fifo_out) | ila_ttc_out | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ttc_out_ila_v6_2_12_ila | 1024(0.30%) | 857(0.25%) | 0(0.00%) | 167(0.10%) | 1675(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_ttc_out_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ttc_out_ila_v6_2_12_ila_core | 1023(0.30%) | 856(0.25%) | 0(0.00%) | 167(0.10%) | 1669(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_ttc_out_ila_v6_2_12_ila_core | 40(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.02%) | 123(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ttc_out_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ttc_out_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_ttc_out_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ttc_out_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ttc_out_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ttc_out_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ttc_out_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ttc_out_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ttc_out_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ttc_out_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ttc_out_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ttc_out_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ttc_out_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ttc_out_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ttc_out_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ttc_out_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ttc_out_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_46 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_47 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_47 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized1_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized2_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ttc_out_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ttc_out_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ttc_out_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ttc_out_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ttc_out_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ttc_out_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ttc_out_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_42 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_43 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_43 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized1_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized2_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ttc_out_ila_v6_2_12_ila_register | 714(0.21%) | 713(0.21%) | 0(0.00%) | 1(0.01%) | 1094(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ttc_out_ila_v6_2_12_ila_register | 284(0.08%) | 283(0.08%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ttc_out_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized1_33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized1_32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized53 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ttc_out_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ttc_out_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_ttc_out_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ttc_out_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ttc_out_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ttc_out_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ttc_out_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ttc_out_ila_v6_2_12_ila_trigger | 118(0.03%) | 41(0.01%) | 0(0.00%) | 77(0.04%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ttc_out_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ttc_out_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ttc_out_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ttc_out_ila_v6_2_12_ila_trig_match | 112(0.03%) | 40(0.01%) | 0(0.00%) | 72(0.04%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_ttc_out_ila_v6_2_12_ila_trig_match | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized0 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_8 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized3 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized3 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ttc_out_ltlib_v1_0_0_generic_memrd | 64(0.02%) | 62(0.02%) | 0(0.00%) | 2(0.01%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_continuity_checker | l1id_cont_check | 1617(0.47%) | 1346(0.39%) | 0(0.00%) | 271(0.16%) | 2623(0.38%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (l1id_continuity_checker) | l1id_cont_check | 140(0.04%) | 140(0.04%) | 0(0.00%) | 0(0.00%) | 268(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_l1id_cont_check | ila_l1id_cont | 1477(0.43%) | 1206(0.35%) | 0(0.00%) | 271(0.16%) | 2355(0.34%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_l1id_cont_check) | ila_l1id_cont | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_l1id_cont_ila_v6_2_12_ila | 1477(0.43%) | 1206(0.35%) | 0(0.00%) | 271(0.16%) | 2355(0.34%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_l1id_cont_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_l1id_cont_ila_v6_2_12_ila_core | 1476(0.43%) | 1205(0.35%) | 0(0.00%) | 271(0.16%) | 2349(0.34%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_l1id_cont_ila_v6_2_12_ila_core | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_l1id_cont_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_l1id_cont_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_l1id_cont_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_l1id_cont_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_l1id_cont_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_l1id_cont_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_l1id_cont_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_l1id_cont_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_l1id_cont_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_l1id_cont_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_l1id_cont_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_l1id_cont_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_l1id_cont_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_l1id_cont_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_l1id_cont_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_l1id_cont_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_l1id_cont_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_71 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_72 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_72 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized1_73 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized2_74 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_l1id_cont_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_l1id_cont_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_l1id_cont_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_l1id_cont_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_l1id_cont_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_l1id_cont_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_l1id_cont_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_67 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_68 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_68 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized1_69 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized2_70 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_l1id_cont_ila_v6_2_12_ila_register | 990(0.29%) | 989(0.29%) | 0(0.00%) | 1(0.01%) | 1396(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_l1id_cont_ila_v6_2_12_ila_register | 345(0.10%) | 344(0.10%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_l1id_cont_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized1_58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized1_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_52 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_l1id_cont_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_l1id_cont_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_l1id_cont_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_l1id_cont_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_l1id_cont_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_l1id_cont_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_l1id_cont_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_l1id_cont_ila_v6_2_12_ila_trigger | 222(0.06%) | 86(0.02%) | 0(0.00%) | 136(0.08%) | 386(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_l1id_cont_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_l1id_cont_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_l1id_cont_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_l1id_cont_ila_v6_2_12_ila_trig_match | 212(0.06%) | 85(0.02%) | 0(0.00%) | 127(0.07%) | 368(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_l1id_cont_ila_v6_2_12_ila_trig_match | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_46 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_46 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_8 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_9 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_43 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_44 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_44 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_40 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_41 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_37 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_38 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_38 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_34 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_35 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_35 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_32 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2__1 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1_22 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_l1id_cont_ltlib_v1_0_0_generic_memrd | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo | ttc_header_fifo_HD10026 | 905(0.26%) | 217(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ttc_header_fifo_fifo_generator_v13_2_7_HD10027 | 905(0.26%) | 217(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | ttc_header_fifo_fifo_generator_v13_2_7_synth_HD10028 | 905(0.26%) | 217(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | ttc_header_fifo_fifo_generator_top_HD10029 | 905(0.26%) | 217(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | ttc_header_fifo_fifo_generator_ramfifo_HD10030 | 905(0.26%) | 217(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | ttc_header_fifo_clk_x_pntrs_HD10031 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | ttc_header_fifo_clk_x_pntrs_HD10031 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray_HD10032 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray__2_HD10033 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | ttc_header_fifo_rd_logic_HD10034 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | ttc_header_fifo_rd_fwft_HD10035 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | ttc_header_fifo_rd_dc_as_HD10036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | ttc_header_fifo_rd_status_flags_as_HD10037 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | ttc_header_fifo_rd_status_flags_as_HD10037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | ttc_header_fifo_compare_2_HD10038 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_3_HD10039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | ttc_header_fifo_rd_bin_cntr_HD10041 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | ttc_header_fifo_wr_logic_HD10042 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | ttc_header_fifo_wr_status_flags_as_HD10043 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | ttc_header_fifo_wr_status_flags_as_HD10043 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_HD10044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | ttc_header_fifo_compare_0_HD10045 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | ttc_header_fifo_compare_1_HD10046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | ttc_header_fifo_wr_bin_cntr_HD10047 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | ttc_header_fifo_memory_HD10048 | 816(0.24%) | 128(0.04%) | 688(0.39%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | ttc_header_fifo_memory_HD10048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | ttc_header_fifo_dmem_HD10049 | 816(0.24%) | 128(0.04%) | 688(0.39%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | ttc_header_fifo_reset_blk_ramfifo_HD10050 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | ttc_header_fifo_reset_blk_ramfifo_HD10050 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst_HD10051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | ttc_header_fifo_xpm_cdc_single_HD10052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | ttc_header_fifo_xpm_cdc_single__2_HD10053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst__1_HD10054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fm_interface_1 | Full_Mode_Tx | 4808(1.39%) | 4288(1.24%) | 64(0.04%) | 456(0.26%) | 7379(1.07%) | 4(0.34%) | 5(0.21%) | 0(0.00%) | | (fm_interface_1) | Full_Mode_Tx | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_stretcher | pulse_stretch__parameterized7_8 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_0 | FM_channel__xdcDup__1 | 1814(0.52%) | 1607(0.46%) | 32(0.02%) | 175(0.10%) | 2787(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_0) | FM_channel__xdcDup__1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD2230 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD2231 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD2232 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD2233 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD2234 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD2235 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD2235 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD2236 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD2237 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD2238 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD2240 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD2241 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD2242 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD2243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD2244 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory_HD2245 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem_HD2246 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD2247 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD2247 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD2248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD2249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD2250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD2251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi_35 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux_36 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD2451 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD2451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD2452 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD2452 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD2453 | 1191(0.34%) | 1019(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD2453 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD2454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD2455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD2456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD2457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD2458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD2459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD2461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD2462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2463 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2463 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD2464 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD2465 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD2466 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2467 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2467 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD2468 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2469 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2469 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD2470 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD2471 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD2472 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD2473 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2474 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2475 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2475 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD2476 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD2477 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2478 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2478 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD2479 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD2480 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD2481 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD2482 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2483 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2484 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2484 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD2485 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD2486 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD2487 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2488 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2489 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2489 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD2490 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD2491 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD2492 | 913(0.26%) | 912(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD2492 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD2493 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD2494 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD2495 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD2496 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD2497 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD2498 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD2499 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD2500 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD2501 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD2502 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD2503 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD2504 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD2505 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD2506 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD2507 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD2508 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD2509 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD2510 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD2511 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD2512 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD2513 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD2514 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD2515 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD2516 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD2517 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD2518 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD2519 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD2520 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD2521 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD2522 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD2523 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD2526 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD2527 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD2528 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD2529 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD2530 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD2531 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD2532 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD2533 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD2534 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD2535 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD2536 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD2537 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD2538 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD2539 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD2546 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD2547 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD2548 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2549 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2549 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2551 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2551 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD2552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD2553 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD2554 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD2555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD2556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD2557 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD2558 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD2558 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD2559 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2560 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2561 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2561 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD2562 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD2563 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD2564 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD2564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2565 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2566 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2566 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD2567 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD2568 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2569 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2569 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2570 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2571 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2572 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2572 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD2573 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD2574 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD2575 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD2576 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2577 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2578 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2579 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2579 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD2580 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2581 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2582 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2583 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2583 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD2584 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2585 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2586 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2587 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2587 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD2588 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD2589 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD2590 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD2591 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2592 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2593 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2594 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2594 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD2595 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2596 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2597 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2598 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2598 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD2599 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2600 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2601 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2602 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2602 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD2603 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2604 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2605 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2606 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2606 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD2607 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2608 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2609 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2610 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2610 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD2611 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2612 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2613 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2614 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2614 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD2615 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2616 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2617 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2618 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2618 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD2619 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2620 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2621 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2622 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2622 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD2623 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD2624 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__1 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__1 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl | 170(0.05%) | 170(0.05%) | 0(0.00%) | 0(0.00%) | 168(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_37 | 153(0.04%) | 153(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_39 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__1 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2887 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2888 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2889 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2890 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2891 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2892 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2892 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2893 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2894 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2895 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2896 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2897 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2898 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2899 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as_HD2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2901 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2902 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2903 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2904 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2905 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2906 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2907 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2908 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2908 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2909 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2910 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2910 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2812 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2813 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2814 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2815 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2816 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2816 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2817 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2818 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2819 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2820 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2821 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_1 | FM_channel__xdcDup__2 | 1825(0.53%) | 1618(0.47%) | 32(0.02%) | 175(0.10%) | 2793(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_1) | FM_channel__xdcDup__2 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD2252 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD2253 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD2254 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD2255 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD2256 | 70(0.02%) | 38(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD2257 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD2257 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD2258 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD2259 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD2260 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD2262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD2263 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD2264 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD2265 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD2266 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory_HD2267 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem_HD2268 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD2269 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD2269 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD2270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD2271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD2272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD2273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi_28 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__6 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux_29 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD2625 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD2625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD2626 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD2626 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD2627 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD2627 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD2628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD2629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD2630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD2631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD2632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD2633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD2634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD2635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD2636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2637 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2637 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD2638 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD2639 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD2640 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2641 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2641 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD2642 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2643 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2643 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD2644 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD2645 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD2646 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD2647 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2648 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2649 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2649 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD2650 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD2651 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2652 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2652 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD2653 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD2654 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD2655 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD2656 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2657 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2658 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2658 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD2659 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD2660 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD2661 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2662 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2663 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2663 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD2664 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD2665 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD2666 | 914(0.26%) | 913(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD2666 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD2667 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD2668 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD2669 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD2670 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD2671 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD2672 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD2673 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD2674 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD2675 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD2676 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD2677 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD2678 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD2679 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD2680 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD2681 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD2682 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD2683 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD2684 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD2685 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD2686 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD2687 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD2688 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD2689 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD2690 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD2691 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD2692 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD2693 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD2694 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD2695 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD2696 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD2697 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD2699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD2700 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD2701 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD2702 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD2703 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD2704 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD2705 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD2706 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD2707 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD2708 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD2709 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD2710 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD2711 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD2712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD2713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD2714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD2715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD2717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD2718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD2719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD2720 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD2721 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD2722 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2723 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2723 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD2724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2725 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2725 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD2726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD2727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD2728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD2729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD2730 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD2731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD2732 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD2732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD2733 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD2733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2734 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2735 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2735 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD2736 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD2737 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD2738 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2739 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2740 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2740 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD2741 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD2742 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2743 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2743 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2744 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2745 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2746 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2746 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD2747 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD2748 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD2749 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD2750 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2751 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2752 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2753 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2753 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD2754 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2755 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2756 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2757 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2757 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD2758 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2759 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2760 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2761 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2761 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD2762 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD2763 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD2764 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD2765 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2766 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2767 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2768 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2768 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD2769 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2770 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2771 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2772 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2772 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD2773 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2774 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2775 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2776 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2776 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD2777 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2778 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2779 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2780 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2780 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD2781 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2782 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2783 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2784 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2784 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD2785 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2786 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2787 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2788 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2788 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD2789 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2790 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2791 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2792 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2792 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD2793 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2794 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2795 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2796 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2796 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD2797 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD2798 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__2 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__2 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__6 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__6 | 178(0.05%) | 178(0.05%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_30 | 154(0.04%) | 154(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eob_space_trig | pulse_pdxx_pwxx_31 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sob_space_trig | pulse_pdxx_pwxx_33 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_34 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__2 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2915 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2916 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2917 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2918 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2919 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2920 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2920 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2921 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2922 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2923 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2925 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2926 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2927 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as_HD2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2929 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2930 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2931 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2932 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2933 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2934 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2935 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2936 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2936 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2937 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2938 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2938 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2822 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2823 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2824 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2825 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2826 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2826 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2827 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2828 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2830 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2831 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_blk | clk_wiz_240_HD1761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_240_clk_wiz_HD1762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u0 | FullModeTransceiver | 1166(0.34%) | 1060(0.31%) | 0(0.00%) | 106(0.06%) | 1793(0.26%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (u0) | FullModeTransceiver | 40(0.01%) | 33(0.01%) | 0(0.00%) | 7(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | g_gt_channel[0].rxresetfsm_i | FullModeTransceiver_RX_STARTUP_FSM__1 | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (g_gt_channel[0].rxresetfsm_i) | FullModeTransceiver_RX_STARTUP_FSM__1 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullModeTransceiver_sync_block_21 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullModeTransceiver_sync_block_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullModeTransceiver_sync_block_23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_24 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullModeTransceiver_sync_block_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | g_gt_channel[1].rxresetfsm_i | FullModeTransceiver_RX_STARTUP_FSM | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (g_gt_channel[1].rxresetfsm_i) | FullModeTransceiver_RX_STARTUP_FSM | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullModeTransceiver_sync_block_14 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullModeTransceiver_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullModeTransceiver_sync_block_16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullModeTransceiver_sync_block_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_resetfsm | ila_mgtfsm | 876(0.25%) | 777(0.22%) | 0(0.00%) | 99(0.06%) | 1358(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_resetfsm) | ila_mgtfsm | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_mgtfsm_ila_v6_2_12_ila | 876(0.25%) | 777(0.22%) | 0(0.00%) | 99(0.06%) | 1358(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_mgtfsm_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_mgtfsm_ila_v6_2_12_ila_core | 875(0.25%) | 776(0.22%) | 0(0.00%) | 99(0.06%) | 1352(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_mgtfsm_ila_v6_2_12_ila_core | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_mgtfsm_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_mgtfsm_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_mgtfsm_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | u_ila_cap_ctrl | ila_mgtfsm_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_mgtfsm_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_mgtfsm_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_mgtfsm_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_mgtfsm_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_mgtfsm_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_mgtfsm_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_mgtfsm_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_mgtfsm_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_mgtfsm_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_mgtfsm_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_mgtfsm_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_44 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_45 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_45 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_mgtfsm_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_mgtfsm_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_mgtfsm_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_40 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_41 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_mgtfsm_ila_v6_2_12_ila_register | 708(0.20%) | 707(0.20%) | 0(0.00%) | 1(0.01%) | 1085(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_mgtfsm_ila_v6_2_12_ila_register | 279(0.08%) | 278(0.08%) | 0(0.00%) | 1(0.01%) | 159(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_mgtfsm_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1_31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1_30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized53 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_mgtfsm_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_mgtfsm_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_mgtfsm_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_mgtfsm_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_mgtfsm_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_mgtfsm_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_mgtfsm_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_mgtfsm_ila_v6_2_12_ila_trigger | 50(0.01%) | 5(0.01%) | 0(0.00%) | 45(0.03%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_mgtfsm_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_mgtfsm_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_mgtfsm_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_mgtfsm_ila_v6_2_12_ila_trig_match | 44(0.01%) | 4(0.01%) | 0(0.00%) | 40(0.02%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_mgtfsm_ila_v6_2_12_ila_trig_match | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_10 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_mgtfsm_ltlib_v1_0_0_generic_memrd | 26(0.01%) | 24(0.01%) | 0(0.00%) | 2(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txresetfsm_i | FullModeTransceiver_TX_STARTUP_FSM | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txresetfsm_i) | FullModeTransceiver_TX_STARTUP_FSM | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | FullModeTransceiver_sync_block | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | FullModeTransceiver_sync_block_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_10 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | FullModeTransceiver_sync_block_13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_blk | ROD_system | 12195(3.52%) | 11480(3.31%) | 345(0.20%) | 370(0.21%) | 15876(2.29%) | 19(1.61%) | 4(0.17%) | 0(0.00%) | | (ipbus_blk) | ROD_system | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi4_subsys | axi4_subsys_wrapper | 6764(1.95%) | 6215(1.79%) | 220(0.13%) | 329(0.19%) | 8263(1.19%) | 2(0.17%) | 3(0.13%) | 0(0.00%) | | (axi4_subsys) | axi4_subsys_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi4_subsys_i | axi4_subsys | 6764(1.95%) | 6215(1.79%) | 220(0.13%) | 329(0.19%) | 8263(1.19%) | 2(0.17%) | 3(0.13%) | 0(0.00%) | | axi_emc_0 | axi4_subsys_axi_emc_0_0 | 448(0.13%) | 312(0.09%) | 0(0.00%) | 136(0.08%) | 266(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_emc | 448(0.13%) | 312(0.09%) | 0(0.00%) | 136(0.08%) | 266(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_emc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_EMC_NATIVE_INTERFACE_I | axi_emc_native_interface | 356(0.10%) | 220(0.06%) | 0(0.00%) | 136(0.08%) | 123(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (AXI_EMC_NATIVE_INTERFACE_I) | axi_emc_native_interface | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 81(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_EMC_ADDRESS_DECODE_INSTANCE_I | axi_emc_address_decode | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_EMC_ADDR_GEN_INSTANCE_I | axi_emc_addr_gen | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RDATA_FIFO_I | srl_fifo_rbu_f | 163(0.05%) | 27(0.01%) | 0(0.00%) | 136(0.08%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RDATA_FIFO_I) | srl_fifo_rbu_f | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CNTR_INCR_DECR_ADDN_F_I | cntr_incr_decr_addn_f | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DYNSHREG_F_I | dynshreg_f | 145(0.04%) | 9(0.01%) | 0(0.00%) | 136(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EMC_CTRL_I | EMC | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 142(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDR_COUNTER_MUX_I | addr_counter_mux | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | COUNTERS_I | counters | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | THZCNT_I | ld_arith_reg__parameterized1 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TLZCNT_I | ld_arith_reg__parameterized1_2363 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TRDCNT_I | ld_arith_reg__parameterized0 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TWPHCNT_I | ld_arith_reg__parameterized1_2364 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TWRCNT_I | ld_arith_reg__parameterized0_2365 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IO_REGISTERS_I | io_registers | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPIC_IF_I | emc_common_v3_0_5_ipic_if | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IPIC_IF_I) | emc_common_v3_0_5_ipic_if | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BURST_CNT | ld_arith_reg | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_STATE_MACHINE_I | mem_state_machine | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_STEER_I | mem_steer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_gpio_0 | axi4_subsys_axi_gpio_0_0 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 295(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_gpio | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 295(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_gpio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi_lite_ipif | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_DECODER) | address_decoder | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gpio_core_1 | GPIO_Core | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 202(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gpio_core_1) | GPIO_Core | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Dual.INPUT_DOUBLE_REGS5 | cdc_sync__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_hwicap_0 | axi4_subsys_axi_hwicap_0_0 | 488(0.14%) | 488(0.14%) | 0(0.00%) | 0(0.00%) | 1126(0.16%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | U0 | axi_hwicap | 488(0.14%) | 488(0.14%) | 0(0.00%) | 0(0.00%) | 1126(0.16%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | (U0) | axi_hwicap | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP_SHARED.HWICAP_CTRL_I | hwicap_shared | 365(0.11%) | 365(0.11%) | 0(0.00%) | 0(0.00%) | 997(0.14%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | (ICAP_SHARED.HWICAP_CTRL_I) | hwicap_shared | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_BUS2ICAP_RESET | cdc_sync__parameterized3_2340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPIC_IF_I | axi_hwicap_v3_0_30_ipic_if | 283(0.08%) | 283(0.08%) | 0(0.00%) | 0(0.00%) | 813(0.12%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | (IPIC_IF_I) | axi_hwicap_v3_0_30_ipic_if | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BUS2ICAP_SIZE_REGISTER_PROCESS | cdc_sync__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_RST_CDC_PROCESS | cdc_sync__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2BUS_STATUS_REGISTER_PROCESS | cdc_sync__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH1 | cdc_sync__parameterized3_2341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH2 | cdc_sync__parameterized3_2342 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH3 | cdc_sync__parameterized3_2343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH4 | cdc_sync__parameterized3_2344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH5 | cdc_sync__parameterized1_2345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLB2ICAP_SYNCH1 | cdc_sync__parameterized3_2346 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLB2ICAP_SYNCH2 | cdc_sync__parameterized3_2347 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLB2ICAP_SYNCH3 | cdc_sync__parameterized3_2348 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD_FIFO.RDDATA_FIFO_I | async_fifo_fg__parameterized0 | 156(0.05%) | 156(0.05%) | 0(0.00%) | 0(0.00%) | 259(0.04%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (RD_FIFO.RDDATA_FIFO_I) | async_fifo_fg__parameterized0 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_instance.xpm_fifo_async_inst | xpm_fifo_async__parameterized1 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 259(0.04%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base__parameterized0 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 259(0.04%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized1 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray__parameterized0__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec__parameterized0_2356 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | xpm_fifo_reg_vec__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec__parameterized0_2357 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | xpm_fifo_reg_vec__parameterized1_2358 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized1__1 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__parameterized0__1 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized5 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit_2359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized5_2360 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized6_2361 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized4_2362 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD_FIFO.RDFULL_SYNCH | cdc_sync__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRFIFO.WRDATA_FIFO_I | async_fifo_fg | 115(0.03%) | 115(0.03%) | 0(0.00%) | 0(0.00%) | 179(0.03%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (WRFIFO.WRDATA_FIFO_I) | async_fifo_fg | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_instance.xpm_fifo_async_inst | xpm_fifo_async | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 179(0.03%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 179(0.03%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized0 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | xpm_fifo_reg_vec__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec_2350 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized2 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit_2352 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized1_2353 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized2_2354 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized0_2355 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst__xdcDup__1 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst__xdcDup__1 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRFIFO.WREMPTY_SYNCH | cdc_sync__parameterized3_2349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | icap_statemachine_I1 | icap_statemachine_shared | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INTERRUPT_CONTROL_I | interrupt_control | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | XI4_LITE_I | axi_lite_ipif__parameterized0 | 120(0.03%) | 120(0.03%) | 0(0.00%) | 0(0.00%) | 82(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized0 | 120(0.03%) | 120(0.03%) | 0(0.00%) | 0(0.00%) | 82(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized0 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 57(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized0 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_iic_0 | axi4_subsys_axi_iic_0_0 | 416(0.12%) | 406(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_iic__1 | 416(0.12%) | 406(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_IIC | iic | 416(0.12%) | 406(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_IIC) | iic | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DYN_MASTER_I | dynamic_master | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FILTER_I | filter | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SCL_DEBOUNCE | debounce | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3_2095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SDA_DEBOUNCE | debounce_2094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IIC_CONTROL_I | iic_control | 174(0.05%) | 174(0.05%) | 0(0.00%) | 0(0.00%) | 119(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IIC_CONTROL_I) | iic_control | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BITCNT | upcnt_n__parameterized0 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CLKCNT | upcnt_n | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CDATA_REG | shift8 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CHEADER_REG | shift8_2092 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SETUP_CNT | upcnt_n_2093 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READ_FIFO_I | SRL_FIFO | 12(0.01%) | 8(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | REG_INTERFACE_I | reg_interface | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 126(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_CTRL_I | SRL_FIFO__parameterized0 | 9(0.01%) | 7(0.01%) | 0(0.00%) | 2(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_I | SRL_FIFO_2091 | 16(0.01%) | 12(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_AXI_IPIF_SSP1 | axi_ipif_ssp1 | 151(0.04%) | 151(0.04%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_AXI_IPIF_SSP1) | axi_ipif_ssp1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi_lite_ipif__parameterized1 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized1 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized1 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized1 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_INTERRUPT_CONTROL | interrupt_control__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_SOFT_RESET | axi_iic_v2_1_2_soft_reset | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_iic_1 | axi4_subsys_axi_iic_1_0 | 415(0.12%) | 405(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_iic | 415(0.12%) | 405(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_IIC | iic_2117 | 415(0.12%) | 405(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_IIC) | iic_2117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DYN_MASTER_I | dynamic_master_2118 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FILTER_I | filter_2119 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SCL_DEBOUNCE | debounce_2136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3_2139 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SDA_DEBOUNCE | debounce_2137 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3_2138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IIC_CONTROL_I | iic_control_2120 | 174(0.05%) | 174(0.05%) | 0(0.00%) | 0(0.00%) | 119(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IIC_CONTROL_I) | iic_control_2120 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BITCNT | upcnt_n__parameterized0_2131 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CLKCNT | upcnt_n_2132 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CDATA_REG | shift8_2133 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CHEADER_REG | shift8_2134 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SETUP_CNT | upcnt_n_2135 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READ_FIFO_I | SRL_FIFO_2121 | 12(0.01%) | 8(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | REG_INTERFACE_I | reg_interface_2122 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 126(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_CTRL_I | SRL_FIFO__parameterized0_2123 | 9(0.01%) | 7(0.01%) | 0(0.00%) | 2(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_I | SRL_FIFO_2124 | 16(0.01%) | 12(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_AXI_IPIF_SSP1 | axi_ipif_ssp1_2125 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_AXI_IPIF_SSP1) | axi_ipif_ssp1_2125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi_lite_ipif__parameterized1_2126 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized1_2129 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized1_2129 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized1_2130 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_INTERRUPT_CONTROL | interrupt_control__parameterized0_2127 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_SOFT_RESET | axi_iic_v2_1_2_soft_reset_2128 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interconnect_0 | axi4_subsys_axi_interconnect_0_0 | 3410(0.98%) | 3237(0.93%) | 0(0.00%) | 173(0.10%) | 3099(0.45%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m01_couplers | m01_couplers_imp_FF3AZQ | 390(0.11%) | 355(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_0 | 390(0.11%) | 355(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_2236 | 390(0.11%) | 355(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_2237 | 390(0.11%) | 355(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_2237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_2238 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_2238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_2255 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2256 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2256 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2257 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2258 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_2239 | 53(0.02%) | 18(0.01%) | 0(0.00%) | 35(0.02%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_2239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_2253 | 43(0.01%) | 11(0.01%) | 0(0.00%) | 32(0.02%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_2254 | 10(0.01%) | 7(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_2240 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 182(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_2249 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_2250 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_2251 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_2252 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_2241 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_2241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_2245 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2246 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2246 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2247 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2248 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_2242 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_2242 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_2243 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_2244 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m02_couplers | m02_couplers_imp_L8N2BP | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_1 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_2213 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_2214 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_2214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_2215 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_2215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_2232 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2233 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2233 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2234 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2235 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_2216 | 35(0.01%) | 20(0.01%) | 0(0.00%) | 15(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_2216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_2230 | 21(0.01%) | 9(0.01%) | 0(0.00%) | 12(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_2231 | 15(0.01%) | 12(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_2217 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_2226 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_2227 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_2228 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_2229 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_2218 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_2218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_2222 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2223 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2223 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2224 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2225 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_2219 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_2219 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_2220 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_2221 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m03_couplers | m03_couplers_imp_1MMZOD7 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_2 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_2190 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_2191 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_2191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_2192 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_2192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_2209 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2210 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2210 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2211 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2212 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_2193 | 35(0.01%) | 20(0.01%) | 0(0.00%) | 15(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_2193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_2207 | 21(0.01%) | 9(0.01%) | 0(0.00%) | 12(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_2208 | 15(0.01%) | 12(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_2194 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_2203 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_2204 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_2205 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_2206 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_2195 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_2195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_2199 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2200 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2200 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2201 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2202 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_2196 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_2196 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_2197 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_2198 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m04_couplers | m04_couplers_imp_1FSUCEB | 392(0.11%) | 356(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_3 | 392(0.11%) | 356(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_2167 | 392(0.11%) | 356(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_2168 | 392(0.11%) | 356(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_2168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_2169 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_2169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_2186 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2187 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2187 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2188 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2189 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_2170 | 54(0.02%) | 18(0.01%) | 0(0.00%) | 36(0.02%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_2170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_2184 | 44(0.01%) | 11(0.01%) | 0(0.00%) | 33(0.02%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_2185 | 10(0.01%) | 7(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_2171 | 164(0.05%) | 164(0.05%) | 0(0.00%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_2180 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_2181 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_2182 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_2183 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_2172 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_2172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_2176 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2177 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2177 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2178 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2179 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_2173 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_2173 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_2174 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_2175 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m05_couplers | m05_couplers_imp_ADRT99 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_4 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_2144 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_2145 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_2145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_2146 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_2146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_2163 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2164 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2164 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2165 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2166 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_2147 | 54(0.02%) | 19(0.01%) | 0(0.00%) | 35(0.02%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_2147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_2161 | 41(0.01%) | 9(0.01%) | 0(0.00%) | 32(0.02%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_2162 | 14(0.01%) | 11(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_2148 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 182(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_2157 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_2158 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_2159 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_2160 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_2149 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_2149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_2153 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2154 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2154 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2155 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2156 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_2150 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_2150 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_2151 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_2152 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m06_couplers | m06_couplers_imp_Q7JFB2 | 388(0.11%) | 365(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_5 | 388(0.11%) | 365(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter | 388(0.11%) | 365(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s | 388(0.11%) | 365(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2141 | 74(0.02%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_2141 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_2142 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_2143 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel | 43(0.01%) | 20(0.01%) | 0(0.00%) | 23(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1 | 29(0.01%) | 9(0.01%) | 0(0.00%) | 20(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2 | 15(0.01%) | 12(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 168(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_2140 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | s00_couplers | s00_couplers_imp_IY3DNS | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xbar | axi4_subsys_xbar_0 | 1120(0.32%) | 1106(0.32%) | 0(0.00%) | 14(0.01%) | 823(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_crossbar_v2_1_27_axi_crossbar | 1120(0.32%) | 1106(0.32%) | 0(0.00%) | 14(0.01%) | 823(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_samd.crossbar_samd | axi_crossbar_v2_1_27_crossbar | 1120(0.32%) | 1106(0.32%) | 0(0.00%) | 14(0.01%) | 823(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_samd.crossbar_samd) | axi_crossbar_v2_1_27_crossbar | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_arbiter_ar | axi_crossbar_v2_1_27_addr_arbiter | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (addr_arbiter_ar) | axi_crossbar_v2_1_27_addr_arbiter | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_arbiter.mux_mesg | generic_baseblocks_v2_1_0_mux_enc__parameterized2_2315 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_arbiter_aw | axi_crossbar_v2_1_27_addr_arbiter_2259 | 174(0.05%) | 174(0.05%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (addr_arbiter_aw) | axi_crossbar_v2_1_27_addr_arbiter_2259 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_arbiter.mux_mesg | generic_baseblocks_v2_1_0_mux_enc__parameterized2 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_decerr_slave.decerr_slave_inst | axi_crossbar_v2_1_27_decerr_slave | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[0].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux | 26(0.01%) | 25(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[0].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2313 | 25(0.01%) | 24(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2313 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2314 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[0].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_2311 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_2312 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[1].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_2260 | 30(0.01%) | 29(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[1].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_2260 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2309 | 28(0.01%) | 27(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2309 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2310 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[1].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_2261 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_2307 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_2308 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[2].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_2262 | 17(0.01%) | 16(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[2].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_2262 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2305 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2305 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2306 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[2].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_2263 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_2303 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_2304 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[3].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_2264 | 17(0.01%) | 16(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[3].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_2264 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2301 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2301 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2302 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[3].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_2265 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_2299 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_2300 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[4].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_2266 | 31(0.01%) | 30(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[4].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_2266 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2297 | 29(0.01%) | 28(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2297 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2298 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[4].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_2267 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_2295 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_2296 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[5].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_2268 | 26(0.01%) | 25(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[5].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_2268 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2293 | 24(0.01%) | 23(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_2293 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2294 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[5].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_2269 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_2291 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_2292 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[6].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_2270 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[6].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_2270 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0 | 20(0.01%) | 19(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2290 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[6].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_2271 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 57(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_2288 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_2289 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[7].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux__parameterized0 | 9(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[7].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized1 | 8(0.01%) | 7(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized1 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2287 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[7].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_2272 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_read.si_transactor_ar | axi_crossbar_v2_1_27_si_transactor | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_slave_slots[0].gen_si_read.si_transactor_ar) | axi_crossbar_v2_1_27_si_transactor | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_single_thread.mux_resp_single_thread | generic_baseblocks_v2_1_0_mux_enc_2286 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_write.si_transactor_aw | axi_crossbar_v2_1_27_si_transactor__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_write.splitter_aw_si | axi_crossbar_v2_1_27_splitter | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_write.wdata_router_w | axi_crossbar_v2_1_27_wdata_router | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrouter_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo_2280 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (wrouter_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo_2280 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2281 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[1].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2282 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[2].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2283 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[3].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2284 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_read.si_transactor_ar | axi_crossbar_v2_1_27_si_transactor__parameterized1 | 115(0.03%) | 115(0.03%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_slave_slots[1].gen_si_read.si_transactor_ar) | axi_crossbar_v2_1_27_si_transactor__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.arbiter_resp_inst | axi_crossbar_v2_1_27_arbiter_resp_2279 | 101(0.03%) | 101(0.03%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.mux_resp_multi_thread | generic_baseblocks_v2_1_0_mux_enc | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_write.si_transactor_aw | axi_crossbar_v2_1_27_si_transactor__parameterized2 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_slave_slots[1].gen_si_write.si_transactor_aw) | axi_crossbar_v2_1_27_si_transactor__parameterized2 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.arbiter_resp_inst | axi_crossbar_v2_1_27_arbiter_resp | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.mux_resp_multi_thread | generic_baseblocks_v2_1_0_mux_enc__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_write.splitter_aw_si | axi_crossbar_v2_1_27_splitter_2273 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_write.wdata_router_w | axi_crossbar_v2_1_27_wdata_router_2274 | 27(0.01%) | 24(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrouter_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo | 27(0.01%) | 24(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (wrouter_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[1].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2276 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[2].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2277 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[3].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_2278 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | splitter_aw_mi | axi_crossbar_v2_1_27_splitter_2275 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_quad_spi_0 | axi4_subsys_axi_quad_spi_0_0 | 547(0.16%) | 503(0.15%) | 44(0.03%) | 0(0.00%) | 793(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_quad_spi | 547(0.16%) | 503(0.15%) | 44(0.03%) | 0(0.00%) | 793(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | NO_DUAL_QUAD_MODE.QSPI_NORMAL | axi_quad_spi_top | 547(0.16%) | 503(0.15%) | 44(0.03%) | 0(0.00%) | 793(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (NO_DUAL_QUAD_MODE.QSPI_NORMAL) | axi_quad_spi_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I | axi_lite_ipif__parameterized2 | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 91(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized2 | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 91(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized2 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized2 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_DECODER) | address_decoder__parameterized2 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[10].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized14 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[11].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized15 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[12].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[13].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[14].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[15].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[1].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[8].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[9].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized24 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized21_2113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized23_2114 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized24_2115 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized27_2116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I | qspi_core_interface | 440(0.13%) | 396(0.11%) | 44(0.03%) | 0(0.00%) | 701(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I) | qspi_core_interface | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONTROL_REG_I | qspi_cntrl_reg | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.CLK_CROSS_I | cross_clk_sync_fifo_1 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.FIFO_IF_MODULE_I | qspi_fifo_ifmodule | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC | cdc_sync__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC | cdc_sync__parameterized6_2096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.RX_FIFO_II | xpm_fifo_async__parameterized3 | 116(0.03%) | 94(0.03%) | 22(0.01%) | 0(0.00%) | 188(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base__parameterized1 | 116(0.03%) | 94(0.03%) | 22(0.01%) | 0(0.00%) | 188(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf_wptr_p3.wrpp3_inst | xpm_counter_updn__parameterized7_2101 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray__parameterized2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec__parameterized2_2102 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec__parameterized2_2104 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | xpm_fifo_reg_vec__parameterized3_2105 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__parameterized2__3 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | xpm_counter_updn__parameterized9_2106 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base__parameterized1 | 22(0.01%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized10_2107 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized11_2108 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit_2109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized10_2110 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized11_2111 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized8_2112 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst__parameterized0__xdcDup__1 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst__parameterized0__xdcDup__1 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__parameterized0__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I | axi_quad_spi_v3_2_25_counter_f | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.TX_FIFO_II | async_fifo_fg__parameterized1 | 128(0.04%) | 106(0.03%) | 22(0.01%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (FIFO_EXISTS.TX_FIFO_II) | async_fifo_fg__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_instance.xpm_fifo_async_inst | xpm_fifo_async__parameterized5 | 119(0.03%) | 97(0.03%) | 22(0.01%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base__parameterized2 | 119(0.03%) | 97(0.03%) | 22(0.01%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base__parameterized2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf_wptr_p3.wrpp3_inst | xpm_counter_updn__parameterized7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized4__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray__parameterized2__2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec__parameterized2 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | xpm_fifo_reg_vec__parameterized3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec__parameterized2_2097 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__parameterized2__1 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | xpm_counter_updn__parameterized9 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base__parameterized1__1 | 22(0.01%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized10 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized11 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized10_2099 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized11_2100 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst__parameterized0 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst__parameterized0 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INTERRUPT_CONTROL_I | interrupt_control__parameterized1 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LOGIC_FOR_MD_0_GEN.SPI_MODULE_I | qspi_mode_0_module | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RESET_SYNC_AXI_SPI_CLK_INST | reset_sync_module | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SOFT_RESET_I | axi_quad_spi_v3_2_25_soft_reset | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I | qspi_status_slave_sel_reg | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | jtag_axi_0 | axi4_subsys_jtag_axi_0_0 | 754(0.22%) | 578(0.17%) | 176(0.10%) | 0(0.00%) | 1680(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | U0 | jtag_axi_v1_2_15_jtag_axi | 754(0.22%) | 578(0.17%) | 176(0.10%) | 0(0.00%) | 1680(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | axi_bridge_u | jtag_axi_v1_2_15_axi_bridge | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | read_axi_full_u | jtag_axi_v1_2_15_read_axi | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 87(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | write_axi_full_u | jtag_axi_v1_2_15_write_axi | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | jtag_axi_engine_u | jtag_axi_v1_2_15_jtag_axi_engine | 697(0.20%) | 521(0.15%) | 176(0.10%) | 0(0.00%) | 1519(0.22%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (jtag_axi_engine_u) | jtag_axi_v1_2_15_jtag_axi_engine | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_decode_rd_channel | jtag_axi_v1_2_15_cmd_decode | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_decode_wr_channel | jtag_axi_v1_2_15_cmd_decode_2316 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_cmd_fifo_i | fifo_generator_v13_2_7__parameterized1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth__parameterized1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top__parameterized1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo__parameterized1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs__parameterized0 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized8__5 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized8__4 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic__parameterized0_2326 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft_2337 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as__parameterized0_2338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr__parameterized0_2339 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic__parameterized0_2327 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as__parameterized0_2335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr__parameterized0_2336 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory__parameterized1_2328 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory__parameterized1_2328 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | blk_mem_gen_v8_4_5__parameterized1_2329 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | blk_mem_gen_v8_4_5_synth__parameterized0_2330 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | blk_mem_gen_top__parameterized0_2331 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | blk_mem_gen_generic_cstr__parameterized0_2332 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | blk_mem_gen_prim_width__parameterized0_2333 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | blk_mem_gen_prim_width__parameterized0_2333 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | blk_mem_gen_prim_wrapper__parameterized0_2334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rx_fifo_i | fifo_generator_v13_2_7__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized6__5 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized6__4 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic_2319 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft_2323 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as_2324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr_2325 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic_2320 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as_2321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr_2322 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | blk_mem_gen_v8_4_5 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | blk_mem_gen_v8_4_5_synth | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | blk_mem_gen_top | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | blk_mem_gen_generic_cstr | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | blk_mem_gen_prim_width | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | blk_mem_gen_prim_width | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | tx_fifo_i | fifo_generator_v13_2_7 | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs__xdcDup__1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs__xdcDup__1 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized6 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized6__6 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft_2318 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory | 208(0.06%) | 32(0.01%) | 176(0.10%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dmem | 208(0.06%) | 32(0.01%) | 176(0.10%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_xsdb_fifo_interface | jtag_axi_v1_2_15_xsdb_fifo_interface | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 474(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_xsdb_fifo_interface) | jtag_axi_v1_2_15_xsdb_fifo_interface | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rxfifo2xsdb_i | jtag_axi_v1_2_15_rxfifo2xsdb | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb2read_cmdfifo | jtag_axi_v1_2_15_xsdb2txfifo__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb2txfifo_i | jtag_axi_v1_2_15_xsdb2txfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb2write_cmdfifo | jtag_axi_v1_2_15_xsdb2txfifo__parameterized0_2317 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_cmd_fifo_i | fifo_generator_v13_2_7__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs__parameterized0__xdcDup__1 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs__parameterized0__xdcDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized8 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized8__6 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic__parameterized0 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | blk_mem_gen_v8_4_5__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | blk_mem_gen_v8_4_5_synth__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | blk_mem_gen_top__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | blk_mem_gen_generic_cstr__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | blk_mem_gen_prim_width__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | blk_mem_gen_prim_width__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | blk_mem_gen_prim_wrapper__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | xadc_wiz_0 | axi4_subsys_xadc_wiz_0_0 | 191(0.06%) | 191(0.06%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi4_subsys_xadc_wiz_0_0_axi_xadc | 191(0.06%) | 191(0.06%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | axi4_subsys_xadc_wiz_0_0_axi_xadc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi4_subsys_xadc_wiz_0_0_axi_lite_ipif | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | axi4_subsys_xadc_wiz_0_0_slave_attachment | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | axi4_subsys_xadc_wiz_0_0_slave_attachment | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | axi4_subsys_xadc_wiz_0_0_address_decoder | 122(0.04%) | 122(0.04%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_XADC_CORE_I | axi4_subsys_xadc_wiz_0_0_xadc_core_drp | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I | axi4_subsys_xadc_wiz_0_0_interrupt_control | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SOFT_RESET_I | axi4_subsys_xadc_wiz_0_0_soft_reset | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_regs | common_IdVersion_regs | 237(0.07%) | 237(0.07%) | 0(0.00%) | 0(0.00%) | 210(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (common_regs) | common_IdVersion_regs | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Xmlversion | ipbus_syncreg_v__parameterized0 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Xmlversion) | ipbus_syncreg_v__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2376 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | buildversion | ipbus_syncreg_v__parameterized0_2368 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (buildversion) | ipbus_syncreg_v__parameterized0_2368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2375 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dna_regs | ipbus_syncreg_v__parameterized0_2369 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dna_regs) | ipbus_syncreg_v__parameterized0_2369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2374 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fpga_dna | dna_reader | 160(0.05%) | 160(0.05%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_id_reg | ipbus_syncreg_v_2370 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (module_id_reg) | ipbus_syncreg_v_2370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2373 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | serial_num_reg | ipbus_syncreg_v_2371 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (serial_num_reg) | ipbus_syncreg_v_2371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_2372 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ip_addr_probe | vio_ip_address | 399(0.12%) | 399(0.12%) | 0(0.00%) | 0(0.00%) | 733(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ip_addr_probe) | vio_ip_address | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ip_address_vio_v3_0_22_vio | 399(0.12%) | 399(0.12%) | 0(0.00%) | 0(0.00%) | 733(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ip_address_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ip_address_vio_v3_0_22_decoder | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ip_address_vio_v3_0_22_probe_in_one | 294(0.08%) | 294(0.08%) | 0(0.00%) | 0(0.00%) | 504(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_WIDTH_INST | vio_ip_address_vio_v3_0_22_probe_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ip_address_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus | ipbus_rod | 4728(1.36%) | 4562(1.32%) | 125(0.07%) | 41(0.02%) | 6670(0.96%) | 17(1.44%) | 1(0.04%) | 0(0.00%) | | clocks | clocks_7s_extphy | 23(0.01%) | 21(0.01%) | 0(0.00%) | 2(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretch | led_stretcher | 17(0.01%) | 16(0.01%) | 0(0.00%) | 1(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stretch) | led_stretcher | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div_2367 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | example_clocks | ethernet_mac_rgmii_example_design_clocks | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (example_clocks) | ethernet_mac_rgmii_example_design_clocks | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_generator | ethernet_mac_rgmii_clk_wiz | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | lock_sync | ethernet_mac_rgmii_sync_block | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mmcm_reset_gen | ethernet_mac_rgmii_reset_sync | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | example_resets | ethernet_mac_rgmii_example_design_resets | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (example_resets) | ethernet_mac_rgmii_example_design_resets | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_lite_reset_gen | ethernet_mac_rgmii_reset_sync__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chk_reset_gen | ethernet_mac_rgmii_reset_sync__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dcm_sync | ethernet_mac_rgmii_sync_block__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | glbl_reset_gen | ethernet_mac_rgmii_reset_sync__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtx_reset_gen | ethernet_mac_rgmii_reset_sync__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus | ipbus_ctrl | 3093(0.89%) | 3069(0.89%) | 0(0.00%) | 24(0.01%) | 3942(0.57%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (ipbus) | ipbus_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 397(0.11%) | 397(0.11%) | 0(0.00%) | 0(0.00%) | 319(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cfg | transactor_cfg | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 189(0.05%) | 189(0.05%) | 0(0.00%) | 0(0.00%) | 135(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 209(0.06%) | 209(0.06%) | 0(0.00%) | 0(0.00%) | 183(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 2694(0.78%) | 2670(0.77%) | 0(0.00%) | 24(0.01%) | 3623(0.52%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 246(0.07%) | 245(0.07%) | 0(0.00%) | 1(0.01%) | 336(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 236(0.07%) | 236(0.07%) | 0(0.00%) | 0(0.00%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ARP | udp_build_arp | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.IPAM_block | udp_ipam_block | 213(0.06%) | 211(0.06%) | 0(0.00%) | 2(0.01%) | 199(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ping | udp_build_ping | 164(0.05%) | 164(0.05%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 52(0.02%) | 50(0.01%) | 0(0.00%) | 2(0.01%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 317(0.09%) | 298(0.09%) | 0(0.00%) | 19(0.01%) | 564(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 372(0.11%) | 372(0.11%) | 0(0.00%) | 0(0.00%) | 470(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_2366 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 391(0.11%) | 391(0.11%) | 0(0.00%) | 0(0.00%) | 393(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 123(0.04%) | 123(0.04%) | 0(0.00%) | 0(0.00%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slaves | ipbus_example | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slave3 | ipbus_axi4_bridge | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trimac_fifo_block | eth_7s_rgmii | 1598(0.46%) | 1458(0.42%) | 125(0.07%) | 15(0.01%) | 2615(0.38%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (trimac_fifo_block) | eth_7s_rgmii | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_lite_controller | ethernet_mac_rgmii_axi_lite_sm | 141(0.04%) | 140(0.04%) | 0(0.00%) | 1(0.01%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (axi_lite_controller) | ethernet_mac_rgmii_axi_lite_sm | 141(0.04%) | 140(0.04%) | 0(0.00%) | 1(0.01%) | 169(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | update_speed_sync_inst | ethernet_mac_rgmii_sync_block__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_mac_reset_gen | ethernet_mac_rgmii_reset_sync__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trimac_read_fifo_2 | rgmii_rx_fifo_2 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 158(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst | rgmii_rx_fifo_2_axis_data_fifo_v2_0_8_top | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 158(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | rgmii_rx_fifo_2_xpm_fifo_axis | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 158(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | rgmii_rx_fifo_2_xpm_fifo_axis | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | rgmii_rx_fifo_2_xpm_cdc_sync_rst__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | rgmii_rx_fifo_2_xpm_fifo_base | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 156(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | rgmii_rx_fifo_2_xpm_fifo_base | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | rgmii_rx_fifo_2_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | rgmii_rx_fifo_2_xpm_fifo_reg_vec | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | rgmii_rx_fifo_2_xpm_fifo_reg_vec_0 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | rgmii_rx_fifo_2_xpm_cdc_gray__2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | rgmii_rx_fifo_2_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rdp_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized1 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | rgmii_rx_fifo_2_xpm_fifo_reg_bit | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized0_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized1_3 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | rgmii_rx_fifo_2_xpm_fifo_rst | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | rgmii_rx_fifo_2_xpm_fifo_rst | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | rgmii_rx_fifo_2_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | rgmii_rx_fifo_2_xpm_cdc_sync_rst__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trimac_sup_block | ethernet_mac_rgmii_support | 1363(0.39%) | 1224(0.35%) | 125(0.07%) | 14(0.01%) | 2273(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trimac_sup_block) | ethernet_mac_rgmii_support | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tri_mode_ethernet_mac_i | ethernet_mac_rgmii | 1358(0.39%) | 1219(0.35%) | 125(0.07%) | 14(0.01%) | 2253(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ethernet_mac_rgmii_block | 1358(0.39%) | 1219(0.35%) | 125(0.07%) | 14(0.01%) | 2253(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi4_lite_ipif | ethernet_mac_rgmii_axi4_lite_ipif_wrapper | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (axi4_lite_ipif) | ethernet_mac_rgmii_axi4_lite_ipif_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_lite_top | ethernet_mac_rgmii_axi_lite_ipif | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | ethernet_mac_rgmii_slave_attachment | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | ethernet_mac_rgmii_slave_attachment | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | ethernet_mac_rgmii_address_decoder | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ethernet_mac_rgmii_core | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22 | 1274(0.37%) | 1135(0.33%) | 125(0.07%) | 14(0.01%) | 2110(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ethernet_mac_rgmii_core) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_filter_top | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap | 54(0.02%) | 37(0.01%) | 16(0.01%) | 1(0.01%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (addr_filter_top) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | address_filter_inst | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter | 54(0.02%) | 37(0.01%) | 16(0.01%) | 1(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (address_filter_inst) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter | 52(0.02%) | 35(0.01%) | 16(0.01%) | 1(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resync_promiscuous_mode | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_80 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_update | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_81 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | flow | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_control | 170(0.05%) | 170(0.05%) | 0(0.00%) | 0(0.00%) | 207(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (flow) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_control | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pfc_tx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_pfc_tx_cntl | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx_cntl | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_pause | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx_sync_req | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_enable | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_enable | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_cntl | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 84(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_pause | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_pause | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_pause) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_pause | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_good_rx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_79 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_rx_gen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_gmii_mii_rx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_tx_gen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_gmii_mii_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | intc_control.intc | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_int_ctrl | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (intc_control.intc) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_int_ctrl | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sync[0].sync_request | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipic_mux_inst | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_ipic_mux | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 57(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | man_block.managen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_management | 189(0.05%) | 189(0.05%) | 0(0.00%) | 0(0.00%) | 239(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (man_block.managen) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_management | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | conf | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_config | 144(0.04%) | 144(0.04%) | 0(0.00%) | 0(0.00%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mdio_enabled.phy | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_miim | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | man_reset.sync_bus2ip_reset_bus2ip_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | man_reset.sync_glbl_rstn_bus2ip_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_avb_tx_axi_intf.tx_axi_shim | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_axi_intf | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_axi_shim | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx_axi_intf | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rxgen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx | 168(0.05%) | 159(0.05%) | 0(0.00%) | 9(0.01%) | 250(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rxgen) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx | 30(0.01%) | 21(0.01%) | 0(0.00%) | 9(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FCS_CHECK | ethernet_mac_rgmii_CRC32_8 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_CHECKER | ethernet_mac_rgmii_PARAM_CHECK | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_DECODER | ethernet_mac_rgmii_DECODE_FRAME | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX_SM | ethernet_mac_rgmii_STATE_MACHINES | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stats_block.statistics_counters | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_statistics_core | 398(0.11%) | 285(0.08%) | 109(0.06%) | 4(0.01%) | 828(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stats_block.statistics_counters) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_statistics_core | 292(0.08%) | 179(0.05%) | 109(0.06%) | 4(0.01%) | 296(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[0].fast_statistics | ethernet_mac_rgmii_increment_controller__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[0].fast_statistics) | ethernet_mac_rgmii_increment_controller__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_41 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[1].fast_statistics | ethernet_mac_rgmii_increment_controller__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[1].fast_statistics) | ethernet_mac_rgmii_increment_controller__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_40 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[2].fast_statistics | ethernet_mac_rgmii_increment_controller__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[2].fast_statistics) | ethernet_mac_rgmii_increment_controller__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_39 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[3].fast_statistics | ethernet_mac_rgmii_increment_controller__4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[3].fast_statistics) | ethernet_mac_rgmii_increment_controller__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_38 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[10].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[10].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_31 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[4].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[4].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_37 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[5].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[5].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_36 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[6].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[6].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[7].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[7].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_34 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[8].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[8].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_33 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[9].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[9].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_32 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[11].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[11].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_30 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[12].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[12].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_29 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[13].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__14 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[13].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[14].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__15 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[14].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[15].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[15].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_26 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[16].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[16].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[17].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[17].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_24 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[18].general_statisics | ethernet_mac_rgmii_increment_controller__19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[18].general_statisics) | ethernet_mac_rgmii_increment_controller__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[19].general_statisics | ethernet_mac_rgmii_increment_controller__20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[19].general_statisics) | ethernet_mac_rgmii_increment_controller__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_22 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[20].general_statisics | ethernet_mac_rgmii_increment_controller__21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[20].general_statisics) | ethernet_mac_rgmii_increment_controller__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[21].general_statisics | ethernet_mac_rgmii_increment_controller__22 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[21].general_statisics) | ethernet_mac_rgmii_increment_controller__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[22].general_statisics | ethernet_mac_rgmii_increment_controller__23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[22].general_statisics) | ethernet_mac_rgmii_increment_controller__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[23].general_statisics | ethernet_mac_rgmii_increment_controller__24 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[23].general_statisics) | ethernet_mac_rgmii_increment_controller__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[24].general_statisics | ethernet_mac_rgmii_increment_controller__25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[24].general_statisics) | ethernet_mac_rgmii_increment_controller__25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[25].general_statisics | ethernet_mac_rgmii_increment_controller__26 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[25].general_statisics) | ethernet_mac_rgmii_increment_controller__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[26].general_statisics | ethernet_mac_rgmii_increment_controller__27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[26].general_statisics) | ethernet_mac_rgmii_increment_controller__27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_15 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[27].general_statisics | ethernet_mac_rgmii_increment_controller__28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[27].general_statisics) | ethernet_mac_rgmii_increment_controller__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_14 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[28].general_statisics | ethernet_mac_rgmii_increment_controller__29 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[28].general_statisics) | ethernet_mac_rgmii_increment_controller__29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[29].general_statisics | ethernet_mac_rgmii_increment_controller__30 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[29].general_statisics) | ethernet_mac_rgmii_increment_controller__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[30].general_statisics | ethernet_mac_rgmii_increment_controller__31 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[30].general_statisics) | ethernet_mac_rgmii_increment_controller__31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[31].general_statisics | ethernet_mac_rgmii_increment_controller__32 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[31].general_statisics) | ethernet_mac_rgmii_increment_controller__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[32].general_statisics | ethernet_mac_rgmii_increment_controller__33 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[32].general_statisics) | ethernet_mac_rgmii_increment_controller__33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[33].general_statisics | ethernet_mac_rgmii_increment_controller | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[33].general_statisics) | ethernet_mac_rgmii_increment_controller | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_counter | ethernet_mac_rgmii_pre_accumulator__1 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_byte_counter) | ethernet_mac_rgmii_pre_accumulator__1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2_68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_69 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_72 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_73 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_74 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_75 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_fragment_counter | ethernet_mac_rgmii_pre_accumulator | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_fragment_counter) | ethernet_mac_rgmii_pre_accumulator | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_42 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_44 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_45 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_46 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_47 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_48 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_undersized_counter | ethernet_mac_rgmii_pre_accumulator__3 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_undersized_counter) | ethernet_mac_rgmii_pre_accumulator__3 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_51 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_52 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_53 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_54 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_55 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_56 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_57 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_request | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_response | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_7 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_counter | ethernet_mac_rgmii_pre_accumulator__2 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_byte_counter) | ethernet_mac_rgmii_pre_accumulator__2 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_60 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_61 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_63 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_66 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_axi_rx_rstn_rx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_rx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_tx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_rx_rst_mgmt_rx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_tx_rst_mgmt_tx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_stats_reset | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_axi_rstn_tx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txgen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx | 160(0.05%) | 159(0.05%) | 0(0.00%) | 1(0.01%) | 243(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txgen) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TX_SM1 | ethernet_mac_rgmii_TX_STATE_MACH | 158(0.05%) | 158(0.05%) | 0(0.00%) | 0(0.00%) | 236(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TX_SM1) | ethernet_mac_rgmii_TX_STATE_MACH | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 204(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CRCGEN | ethernet_mac_rgmii_CRC32_8__1 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rgmii_interface | ethernet_mac_rgmii_rgmii_v2_0_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vector_decode_inst | ethernet_mac_rgmii_vector_decode | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 89(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tri_mode_ethernet_mac_support_resets_i | ethernet_mac_rgmii_support_resets | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tri_mode_ethernet_mac_support_resets_i) | ethernet_mac_rgmii_support_resets | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | idelayctrl_reset_gen | ethernet_mac_rgmii_reset_sync__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_mac_reset_gen | ethernet_mac_rgmii_reset_sync__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shelf_addr_sel | ip_dual_decode | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | phy_reset | system_top_reset__parameterized1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pp_out_fifo_6432 | packet_fifo | 1597(0.46%) | 1324(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (pp_out_fifo_6432) | packet_fifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo | 1399(0.40%) | 1126(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila | 1399(0.40%) | 1126(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register | 910(0.26%) | 909(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register | 325(0.09%) | 324(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | proc_clock_gen | packet_processor_clock | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | packet_processor_clock_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_top | system_top_reset | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_pwr | reset_count | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | top_vio | vio_top | 166(0.05%) | 166(0.05%) | 0(0.00%) | 0(0.00%) | 331(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (top_vio) | vio_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_top_vio_v3_0_22_vio | 166(0.05%) | 166(0.05%) | 0(0.00%) | 0(0.00%) | 331(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_top_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_top_vio_v3_0_22_decoder | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_top_vio_v3_0_22_probe_in_one | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 81(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_top_vio_v3_0_22_probe_out_all | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_top_vio_v3_0_22_probe_out_all | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[3].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[4].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[5].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[6].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_top_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_source_sel | vio_ttc_HD428 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ttc_source_sel) | vio_ttc_HD428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD429 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD430 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD431 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD432 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD433 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD434 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +---------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+----------------+----------------+-------------+--------------+----------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining