*** Running vivado with args -log vio_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_top.tcl ****** Vivado v2022.1 (64-bit) **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022 **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source vio_top.tcl -notrace Command: synth_design -top vio_top -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 6848 WARNING: [Synth 8-9501] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:4023] WARNING: [Synth 8-9187] begin/end is required for generate-for in this mode of verilog [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/hdl/vio_v3_0_syn_rfs.v:1365] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3033.070 ; gain = 0.000 ; free physical = 61320 ; free virtual = 74402 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'vio_top' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/synth/vio_top.v:49] INFO: [Synth 8-6155] done synthesizing module 'vio_top' (0#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/synth/vio_top.v:49] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_top does not have driver. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/synth/vio_top.v:95] WARNING: [Synth 8-7129] Port Bus_rst in module vio_v3_0_22_probe_width__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Rd_probe_width in module vio_v3_0_22_probe_width__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Internal_cnt_rst in module vio_v3_0_22_probe_width__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_rst in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Read in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[15] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[14] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[13] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[12] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[11] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[10] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[9] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[8] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[7] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[6] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[5] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[4] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[3] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[2] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[1] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Internal_cnt_rst in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_rst in module vio_v3_0_22_probe_width is either unconnected or has no load WARNING: [Synth 8-7129] Port Rd_probe_width in module vio_v3_0_22_probe_width is either unconnected or has no load WARNING: [Synth 8-7129] Port Internal_cnt_rst in module vio_v3_0_22_probe_width is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in12[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in13[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in14[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in15[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in16[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in17[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in18[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in19[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in20[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in21[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in22[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in23[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in24[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in25[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in26[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in27[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in28[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in29[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in30[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in31[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in32[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in33[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in34[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in35[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in36[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in37[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in38[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in39[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in40[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in41[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in42[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in43[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in44[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in45[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in46[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in47[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in48[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in49[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in50[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in51[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in52[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in53[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in54[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in55[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in56[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in57[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in58[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in59[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in60[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in61[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in62[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in63[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in64[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in65[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in66[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in67[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in68[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in69[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in70[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in71[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in72[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in73[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in74[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in75[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in76[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in77[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in78[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in79[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in80[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in81[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in82[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in83[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in84[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in85[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in86[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in87[0] in module vio_v3_0_22_vio is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3033.070 ; gain = 0.000 ; free physical = 61117 ; free virtual = 74190 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 3033.070 ; gain = 0.000 ; free physical = 61188 ; free virtual = 74261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 3033.070 ; gain = 0.000 ; free physical = 61188 ; free virtual = 74261 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3033.070 ; gain = 0.000 ; free physical = 61234 ; free virtual = 74307 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top_ooc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top_ooc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vio_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/vio_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3193.871 ; gain = 0.000 ; free physical = 58790 ; free virtual = 71863 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3193.871 ; gain = 0.000 ; free physical = 58744 ; free virtual = 71817 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 60154 ; free virtual = 73229 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 60163 ; free virtual = 73238 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 60194 ; free virtual = 73268 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 60257 ; free virtual = 73333 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 16 Bit Registers := 16 12 Bit Registers := 5 7 Bit Registers := 1 5 Bit Registers := 1 3 Bit Registers := 4 1 Bit Registers := 28 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 2 2 Input 1 Bit Muxes := 13 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 59913 ; free virtual = 73004 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 60069 ; free virtual = 73148 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 60073 ; free virtual = 73152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 59966 ; free virtual = 73045 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56141 ; free virtual = 69226 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56139 ; free virtual = 69224 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56117 ; free virtual = 69203 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56112 ; free virtual = 69197 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56084 ; free virtual = 69170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56077 ; free virtual = 69162 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT1 | 1| |2 |LUT2 | 8| |3 |LUT3 | 66| |4 |LUT4 | 8| |5 |LUT5 | 19| |6 |LUT6 | 82| |7 |FDRE | 331| +------+-----+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56075 ; free virtual = 69160 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 282 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 3193.871 ; gain = 0.000 ; free physical = 56046 ; free virtual = 69131 Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 3193.871 ; gain = 160.801 ; free physical = 56044 ; free virtual = 69129 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3193.871 ; gain = 0.000 ; free physical = 56068 ; free virtual = 69153 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3193.871 ; gain = 0.000 ; free physical = 56805 ; free virtual = 69890 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete, checksum: 782c4ee5 INFO: [Common 17-83] Releasing license: Synthesis 18 Infos, 157 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:54 ; elapsed = 00:00:51 . Memory (MB): peak = 3193.871 ; gain = 169.023 ; free physical = 56969 ; free virtual = 70055 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/vio_top_synth_1/vio_top.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_top, cache-ID = 5cd24f7e37bc3424 INFO: [Coretcl 2-1174] Renamed 12 cell refs. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/vio_top_synth_1/vio_top.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_top_utilization_synth.rpt -pb vio_top_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Thu Jan 4 18:05:01 2024...