## Repository info
- Merge request number: 123
- Branch name: 112-input_data_stuck_bit

## MR Description
Changes to constraints to eliminate overriding constraints within the FIFO IP 
Closes #112


## Changelog


## rod_efex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.034847       |
| TNS:          | 0.000000       |
| WHS:          | 0.050180       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    37064    |    0         |   0              |    346400        |    10.70     |   
| Slice  Registers |    51600    |    81        |   0              |    692800        |    7.45      |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    86356    |   0         |   0              |    346400        |    24.93     |    
| Slice  Registers |    135061   |   0         |   0              |    692800        |    19.49     |    
| Block  RAM       Tile |        393 |         0   |              0    |             1180 |         33.31
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 8f37344        | 1.0.1       |
| Constraints       | 4fb58450       | 1.0.1       |
| IPbus XML         | 8f37344        | 1.0.1       |
| Top Directory     | 989ee7c        | 0.5.24      |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_efex | 538979f        | 1.0.1       |
| **Lib:** others   | 7f1c6f3        | 1.0.0       |



</details>
</p>

 
## rod_jfex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.132154       |
| TNS:          | 0.000000       |
| WHS:          | 0.047355       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    52170    |    0         |   0              |    346400        |    15.06     |   
| Slice  Registers |    76619    |    81        |   0              |    692800        |    11.06     |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex Implementation Utilization report


                                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         --- |              ---  |             ---  |              
| Slice  LUTs      |    128621   |     0         |   0              |    346400        |    37.13     |    
| Slice  Registers |    212728   |     0         |   0              |    692800        |    30.71     |    
| Block  RAM       Tile |        664.5 |         0   |              0    |             1180 |         56.31
| DSPs   |         0    |        0     |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |     111       |   0              |    600           |    18.50     |    
                                                                                                           
## rod_jfex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 8f37344        | 1.0.1       |
| Constraints       | 4fb58450       | 1.0.1       |
| IPbus XML         | 8f37344        | 1.0.1       |
| Top Directory     | 276b635        | 1.0.1       |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_jfex | e76bc64        | 1.0.1       |
| **Lib:** others   | dc482e1        | 1.0.1       |



</details>
</p>

 
## rod_efex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.120113       |
| TNS:          | 0.000000       |
| WHS:          | 0.050602       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    44512    |    0         |   0              |    346400        |    12.85     |   
| Slice  Registers |    59717    |    81        |   0              |    692800        |    8.62      |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex_p2 Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    102948   |   0         |   0              |    346400        |    29.72     |    
| Slice  Registers |    159109   |   0         |   0              |    692800        |    22.97     |    
| Block  RAM       Tile |        536 |         0   |              0    |             1180 |         45.42
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | ad77580        | 1.0.1       |
| Constraints          | bf5742a2       | 1.0.1       |
| IPbus XML            | 8f37344        | 1.0.1       |
| Top Directory        | 4a18e6f        | 1.0.1       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_efex_p2 | ad77580        | 1.0.1       |
| **Lib:** others      | b0338c5        | 1.0.0       |



</details>
</p>

 
## rod_jfex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.026746       |
| TNS:          | 0.000000       |
| WHS:          | 0.048738       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    60468    |    0         |   0              |    346400        |    17.46     |   
| Slice  Registers |    86333    |    81        |   0              |    692800        |    12.46     |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex_p2 Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    138544   |   0         |   0              |    346400        |    40.00     |    
| Slice  Registers |    227443   |   0         |   0              |    692800        |    32.83     |    
| Block  RAM       Tile |        895 |         0   |              0    |             1180 |         75.85
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_jfex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | ad77580        | 1.0.1       |
| Constraints          | dde9177c       | 1.0.1       |
| IPbus XML            | 8f37344        | 1.0.1       |
| Top Directory        | 276b635        | 1.0.1       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_jfex_p2 | ad77580        | 1.0.1       |
| **Lib:** others      | dc482e1        | 1.0.1       |



</details>
</p>