Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022 | Date : Thu Feb 22 21:37:25 2024 | Host : atlas-tdaq-firmware-dev.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core) | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/v1VqaazS/2/atlas-l1calo-efex/RODFirmware/bin/rod_efex_p2-v1.0.1-AD77580/reports/hierarchical_utilization.txt | Design : top_rod_efex_p2 | Device : xc7vx550tffg1927-2 | Speed File : -2 | Design State : Routed -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +---------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+----------------+---------------+-------------+-------------+----------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +---------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+----------------+---------------+-------------+-------------+----------------+-------------+-----------+------------+ | top_rod_efex_p2 | (top) | 102967(29.72%) | 92907(26.82%) | 2497(1.43%) | 7563(4.34%) | 159109(22.97%) | 521(44.15%) | 30(1.27%) | 0(0.00%) | | (top_rod_efex_p2) | (top) | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_0_64_32 | packet_fifo__xdcDup__1 | 1599(0.46%) | 1326(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (Bulk_0_64_32) | packet_fifo__xdcDup__1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo_HD37 | 1401(0.40%) | 1128(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo_HD37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila_HD38 | 1401(0.40%) | 1128(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila_HD38 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core_HD39 | 1400(0.40%) | 1127(0.33%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core_HD39 | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory_HD40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5_HD41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth_HD42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD55 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD55 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD56 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7_HD57 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1_HD58 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD59 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD59 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1_HD60 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD61 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD61 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1_HD62 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1_HD63 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6_HD64 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1_HD65 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD66 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD67 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD67 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72_HD68 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73_HD69 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD70 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD70 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4_HD71 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5_HD72 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2_HD73 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay_HD74 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD75 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD76 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD76 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD77 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD78 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2_HD79 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD80 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD81 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD81 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68_HD82 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69_HD83 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register_HD84 | 912(0.26%) | 911(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register_HD84 | 326(0.09%) | 325(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s_HD85 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD86 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD87 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD88 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD89 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD90 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD91 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD92 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD93 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD94 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD95 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD96 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD97 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD98 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs_HD99 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50_HD100 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62_HD101 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51_HD102 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61_HD103 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52_HD104 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60_HD105 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53_HD106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59_HD107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54_HD108 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58_HD109 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55_HD110 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57_HD111 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35_HD112 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65_HD113 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36_HD114 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD115 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37_HD116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64_HD117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56_HD118 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56_HD119 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57_HD120 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55_HD121 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58_HD122 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD123 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59_HD124 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54_HD125 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60_HD126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53_HD127 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61_HD128 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52_HD129 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63_HD130 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51_HD131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65_HD132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50_HD133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49_HD135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38_HD136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63_HD137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD138 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream_HD139 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_HD140 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD141 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD141 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_HD142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD143 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD143 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection_HD144 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD145 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD146 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD147 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer_HD148 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger_HD150 | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger_HD150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match_HD151 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match_HD151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_HD152 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_HD152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA_HD153 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA_HD153 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD154 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD155 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match_HD156 | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match_HD156 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD157 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD158 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD159 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD159 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39_HD160 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40_HD161 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41_HD162 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42_HD163 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43_HD164 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44_HD165 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45_HD166 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD167 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD168 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD169 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD170 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD170 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD171 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD172 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD173 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD174 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD174 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD175 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD176 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD177 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD178 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD178 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD179 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD180 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD181 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD182 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD182 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD183 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD184 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD185 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD186 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD186 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD187 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD188 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD189 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD190 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD190 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32_HD191 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD192 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD193 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD194 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD194 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29_HD195 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD196 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD197 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD198 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD198 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23_HD199 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24_HD200 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25_HD201 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD202 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD203 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD204 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD205 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD205 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17_HD206 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18_HD207 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19_HD208 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD209 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD210 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD211 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD212 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD212 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD213 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD214 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD215 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD216 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD216 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_HD217 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9_HD218 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10_HD219 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD220 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD221 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD222 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD223 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD223 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD224 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd_HD225 | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32_HD797 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD798 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer_HD799 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0_HD813 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0_HD813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top_HD814 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis_HD815 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis_HD815 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3_HD816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base_HD817 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base_HD817 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1_HD818 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray_HD819 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_HD820 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_HD821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0_HD822 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1_HD823 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0_HD824 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2_HD825 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn_HD826 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base_HD827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_HD828 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_HD829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit_HD830 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2_HD831 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3_HD832 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2_HD833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst_HD834 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst_HD834 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst_HD835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4_HD836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_1_64_32 | packet_fifo__xdcDup__2 | 1595(0.46%) | 1322(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (Bulk_1_64_32) | packet_fifo__xdcDup__2 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo_HD226 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo_HD226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila_HD227 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila_HD227 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core_HD228 | 1397(0.40%) | 1124(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core_HD228 | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory_HD229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5_HD230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth_HD231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD244 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD244 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD245 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7_HD246 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1_HD247 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD248 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD248 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1_HD249 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD250 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD250 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1_HD251 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1_HD252 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6_HD253 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1_HD254 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD255 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD256 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD256 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72_HD257 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73_HD258 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD259 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD259 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4_HD260 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5_HD261 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2_HD262 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay_HD263 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD264 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD265 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD265 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD266 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD267 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2_HD268 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD269 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD270 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD270 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68_HD271 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69_HD272 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register_HD273 | 909(0.26%) | 908(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register_HD273 | 326(0.09%) | 325(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s_HD274 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD275 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD276 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD277 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD278 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD279 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD280 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD281 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD282 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD283 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD284 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD285 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD286 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD287 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs_HD288 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50_HD289 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62_HD290 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51_HD291 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61_HD292 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52_HD293 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60_HD294 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53_HD295 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59_HD296 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54_HD297 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58_HD298 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55_HD299 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57_HD300 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35_HD301 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65_HD302 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36_HD303 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD304 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37_HD305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64_HD306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56_HD307 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56_HD308 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57_HD309 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55_HD310 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58_HD311 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD312 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59_HD313 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54_HD314 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60_HD315 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53_HD316 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61_HD317 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52_HD318 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63_HD319 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51_HD320 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65_HD321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50_HD322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49_HD324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38_HD325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63_HD326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD327 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream_HD328 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_HD329 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD330 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD330 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_HD331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD332 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD332 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection_HD333 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD335 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD336 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer_HD337 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD338 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger_HD339 | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger_HD339 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match_HD340 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match_HD340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_HD341 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_HD341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA_HD342 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA_HD342 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD343 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD344 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match_HD345 | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match_HD345 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD346 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD347 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD348 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD348 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39_HD349 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40_HD350 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41_HD351 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42_HD352 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43_HD353 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44_HD354 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45_HD355 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD356 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD357 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD358 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD359 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD359 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD360 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD361 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD362 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD363 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD363 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD364 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD365 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD366 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD367 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD367 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD368 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD369 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD370 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD371 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD371 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD372 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD373 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD374 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD375 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD375 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD376 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD377 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD378 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD379 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD379 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32_HD380 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD381 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD382 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD383 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD383 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29_HD384 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD385 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD386 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD387 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD387 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23_HD388 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24_HD389 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25_HD390 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD391 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD392 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD393 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD394 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD394 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17_HD395 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18_HD396 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19_HD397 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD398 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD399 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD400 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD401 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD401 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD402 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD403 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD404 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD405 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD405 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_HD406 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9_HD407 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10_HD408 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD409 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD410 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD411 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD412 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD412 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD413 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd_HD414 | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32_HD800 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD801 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer_HD802 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0_HD837 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0_HD837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top_HD838 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis_HD839 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis_HD839 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3_HD840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base_HD841 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base_HD841 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1_HD842 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray_HD843 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_HD844 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_HD845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0_HD846 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1_HD847 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0_HD848 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2_HD849 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn_HD850 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base_HD851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_HD852 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_HD853 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit_HD854 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2_HD855 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3_HD856 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2_HD857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst_HD858 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst_HD858 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst_HD859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4_HD860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_2_64_32 | packet_fifo__xdcDup__3 | 1595(0.46%) | 1322(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (Bulk_2_64_32) | packet_fifo__xdcDup__3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo_HD415 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila_HD416 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila_HD416 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core_HD417 | 1397(0.40%) | 1124(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core_HD417 | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory_HD418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5_HD419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth_HD420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD433 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD433 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD434 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7_HD435 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1_HD436 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD437 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD437 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1_HD438 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD439 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD439 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1_HD440 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1_HD441 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6_HD442 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1_HD443 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD444 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD445 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD445 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72_HD446 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73_HD447 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD448 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD448 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4_HD449 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5_HD450 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2_HD451 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay_HD452 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD453 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD454 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD454 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD455 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD456 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2_HD457 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD458 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD459 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD459 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68_HD460 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69_HD461 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register_HD462 | 909(0.26%) | 908(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register_HD462 | 325(0.09%) | 324(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s_HD463 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD464 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD465 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD466 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD467 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD468 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD469 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD470 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD471 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD472 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD473 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD474 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD475 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD476 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs_HD477 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50_HD478 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62_HD479 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51_HD480 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61_HD481 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52_HD482 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60_HD483 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53_HD484 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59_HD485 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54_HD486 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58_HD487 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55_HD488 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57_HD489 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35_HD490 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65_HD491 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36_HD492 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD493 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37_HD494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64_HD495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56_HD496 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56_HD497 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57_HD498 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55_HD499 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58_HD500 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD501 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59_HD502 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54_HD503 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60_HD504 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53_HD505 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61_HD506 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52_HD507 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63_HD508 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51_HD509 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65_HD510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50_HD511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49_HD513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38_HD514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63_HD515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD516 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream_HD517 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_HD518 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD519 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD519 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_HD520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD521 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD521 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection_HD522 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD523 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD524 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD525 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer_HD526 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger_HD528 | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger_HD528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match_HD529 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match_HD529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_HD530 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_HD530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA_HD531 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA_HD531 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD532 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD533 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match_HD534 | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match_HD534 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD535 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD536 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD537 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD537 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39_HD538 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40_HD539 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41_HD540 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42_HD541 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43_HD542 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44_HD543 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45_HD544 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD545 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD546 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD547 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD548 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD548 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD549 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD550 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD551 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD552 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD552 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD553 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD554 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD555 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD556 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD556 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD557 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD558 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD559 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD560 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD560 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD561 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD562 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD563 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD564 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD564 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD565 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD566 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD567 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD568 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD568 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32_HD569 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD570 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD571 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD572 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD572 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29_HD573 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD574 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD575 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD576 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD576 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23_HD577 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24_HD578 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25_HD579 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD580 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD581 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD582 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD583 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD583 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17_HD584 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18_HD585 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19_HD586 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD587 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD588 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD589 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD590 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD590 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD591 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD592 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD593 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD594 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD594 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_HD595 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9_HD596 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10_HD597 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD598 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD599 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD600 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD601 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD601 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD602 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd_HD603 | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32_HD803 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD804 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer_HD805 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0_HD861 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0_HD861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top_HD862 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis_HD863 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis_HD863 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3_HD864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base_HD865 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base_HD865 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1_HD866 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray_HD867 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_HD868 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_HD869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0_HD870 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1_HD871 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0_HD872 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2_HD873 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn_HD874 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base_HD875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_HD876 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_HD877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit_HD878 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2_HD879 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3_HD880 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2_HD881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst_HD882 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst_HD882 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst_HD883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4_HD884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_0 | fex_rx_checker__xdcDup__1 | 1509(0.44%) | 1329(0.38%) | 0(0.00%) | 180(0.10%) | 1966(0.28%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ILA_axi_chan_0) | fex_rx_checker__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | backplane_crc__2 | 355(0.10%) | 355(0.10%) | 0(0.00%) | 0(0.00%) | 175(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | backplane_crc__2 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC | 252(0.07%) | 252(0.07%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_crc_check | chan_crc_ila_HD910 | 1154(0.33%) | 974(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_crc_check) | chan_crc_ila_HD910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | chan_crc_ila_ila_v6_2_12_ila_HD911 | 1154(0.33%) | 974(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | chan_crc_ila_ila_v6_2_12_ila_HD911 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | chan_crc_ila_ila_v6_2_12_ila_core_HD912 | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1783(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | chan_crc_ila_ila_v6_2_12_ila_core_HD912 | 38(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.02%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | chan_crc_ila_ila_v6_2_12_ila_trace_memory_HD913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | chan_crc_ila_blk_mem_gen_v8_4_5_HD914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_synth_HD915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD924 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy_HD924 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | chan_crc_ila_ltlib_v1_0_0_cfglut6__parameterized0_HD925 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | chan_crc_ila_ltlib_v1_0_0_cfglut7_HD926 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | chan_crc_ila_ltlib_v1_0_0_cfglut7__1_HD927 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD928 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen_HD928 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | chan_crc_ila_ltlib_v1_0_0_cfglut6__1_HD929 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD930 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter_HD930 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | chan_crc_ila_ltlib_v1_0_0_cfglut4__1_HD931 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__1_HD932 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | chan_crc_ila_ltlib_v1_0_0_cfglut6_HD933 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__1_HD934 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD935 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57_HD935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD936 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58_HD936 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_59_HD937 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_60_HD938 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD939 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter_HD939 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | chan_crc_ila_ltlib_v1_0_0_cfglut4_HD940 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5_HD941 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__2_HD942 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay_HD943 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD944 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_HD944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD945 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_HD945 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD946 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD947 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__2_HD948 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD949 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53_HD949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD950 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54_HD950 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_55_HD951 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_56_HD952 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | chan_crc_ila_ila_v6_2_12_ila_register_HD953 | 843(0.24%) | 842(0.24%) | 0(0.00%) | 1(0.01%) | 1223(0.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | chan_crc_ila_ila_v6_2_12_ila_register_HD953 | 322(0.09%) | 321(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s_HD954 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized9_HD955 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized0_HD956 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized1_HD957 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized2_HD958 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized3_HD959 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized4_HD960 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized5_HD961 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized6_HD962 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized7_HD963 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized8_HD964 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized10_HD965 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | chan_crc_ila_xsdbs_v1_0_2_xsdbs_HD966 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized46_HD967 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_49_HD968 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized47_HD969 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_48_HD970 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized48_HD971 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_47_HD972 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized49_HD973 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_46_HD974 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized50_HD975 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_45_HD976 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized51_HD977 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_44_HD978 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized31_HD979 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_52_HD980 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized32_HD981 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized0_HD982 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized33_HD983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_51_HD984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized52_HD985 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_43_HD986 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized53_HD987 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_42_HD988 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized54_HD989 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_HD990 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized55_HD991 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_41_HD992 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized56_HD993 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_40_HD994 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized57_HD995 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_39_HD996 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized59_HD997 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_38_HD998 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized61_HD999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_37_HD1000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64_HD1001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_36_HD1002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized34_HD1003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_50_HD1004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1005 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | chan_crc_ila_xsdbs_v1_0_2_reg_stream_HD1006 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_HD1007 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1008 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0_HD1008 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_HD1009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1010 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl_HD1010 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection_HD1011 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__2_HD1012 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__3_HD1013 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__1_HD1014 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer_HD1015 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection__1_HD1016 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1017 | 130(0.04%) | 38(0.01%) | 0(0.00%) | 92(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | chan_crc_ila_ila_v6_2_12_ila_trigger_HD1017 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | chan_crc_ila_ltlib_v1_0_0_match_HD1018 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | chan_crc_ila_ltlib_v1_0_0_match_HD1018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1019 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_HD1019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1020 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA_HD1020 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_34_HD1021 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD1022 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1023 | 120(0.03%) | 37(0.01%) | 0(0.00%) | 83(0.05%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | chan_crc_ila_ila_v6_2_12_ila_trig_match_HD1023 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1024 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized0_HD1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1025 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0_HD1025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1026 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0_HD1026 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_HD1027 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_27_HD1028 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_28_HD1029 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_29_HD1030 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_30_HD1031 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_31_HD1032 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_32_HD1033 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1034 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1035 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1_HD1035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1036 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_HD1036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1037 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_HD1037 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1038 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1039 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1_HD1039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1040 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24_HD1040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1041 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25_HD1041 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD1042 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1043 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2_HD1043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1044 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21_HD1044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1045 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22_HD1045 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23_HD1046 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1047 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3_HD1047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1048 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18_HD1048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1049 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1049 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD1050 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1051 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4_HD1051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1052 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15_HD1052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1053 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1053 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD1054 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1055 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5_HD1055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1056 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD1056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1057 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1057 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD1058 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1059 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6_HD1059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1060 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9_HD1060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1061 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1061 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD1062 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1063 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7_HD1063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1064 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD1064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1065 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1065 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1066 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1067 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8_HD1067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1068 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD1068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1069 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1069 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD1070 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1071 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9_HD1071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1072 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD1072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1073 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1073 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD1074 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | chan_crc_ila_ltlib_v1_0_0_generic_memrd_HD1075 | 55(0.02%) | 53(0.02%) | 0(0.00%) | 2(0.01%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_axi_chan_6 | fex_rx_checker | 1515(0.44%) | 1335(0.39%) | 0(0.00%) | 180(0.10%) | 1966(0.28%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ILA_axi_chan_6) | fex_rx_checker | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | backplane_crc | 362(0.10%) | 362(0.10%) | 0(0.00%) | 0(0.00%) | 175(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | backplane_crc | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_0 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_1 | 262(0.08%) | 262(0.08%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_crc_check | chan_crc_ila | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_crc_check) | chan_crc_ila | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | chan_crc_ila_ila_v6_2_12_ila | 1153(0.33%) | 973(0.28%) | 0(0.00%) | 180(0.10%) | 1789(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | chan_crc_ila_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | chan_crc_ila_ila_v6_2_12_ila_core | 1152(0.33%) | 972(0.28%) | 0(0.00%) | 180(0.10%) | 1783(0.26%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | chan_crc_ila_ila_v6_2_12_ila_core | 38(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.02%) | 117(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | chan_crc_ila_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | chan_crc_ila_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | chan_crc_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | chan_crc_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | chan_crc_ila_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | chan_crc_ila_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | chan_crc_ila_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | chan_crc_ila_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | chan_crc_ila_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | chan_crc_ila_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | chan_crc_ila_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_58 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_60 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | chan_crc_ila_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | chan_crc_ila_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | chan_crc_ila_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | chan_crc_ila_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA_nodelay_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized2_54 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_56 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | chan_crc_ila_ila_v6_2_12_ila_register | 842(0.24%) | 841(0.24%) | 0(0.00%) | 1(0.01%) | 1223(0.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | chan_crc_ila_ila_v6_2_12_ila_register | 320(0.09%) | 319(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | chan_crc_ila_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl_39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized59 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_38 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | chan_crc_ila_xsdbs_v1_0_2_reg__parameterized34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | chan_crc_ila_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | chan_crc_ila_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | chan_crc_ila_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | chan_crc_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | chan_crc_ila_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | chan_crc_ila_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | chan_crc_ila_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | chan_crc_ila_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | chan_crc_ila_ila_v6_2_12_ila_trigger | 130(0.04%) | 38(0.01%) | 0(0.00%) | 92(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | chan_crc_ila_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | chan_crc_ila_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | chan_crc_ila_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | chan_crc_ila_ila_v6_2_12_ila_trig_match | 120(0.03%) | 37(0.01%) | 0(0.00%) | 83(0.05%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | chan_crc_ila_ila_v6_2_12_ila_trig_match | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_25 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_10 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | chan_crc_ila_ltlib_v1_0_0_match__parameterized1__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | chan_crc_ila_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | chan_crc_ila_ltlib_v1_0_0_all_typeA__parameterized1_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | chan_crc_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | chan_crc_ila_ltlib_v1_0_0_generic_memrd | 55(0.02%) | 53(0.02%) | 0(0.00%) | 2(0.01%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_1_64_32 | packet_fifo | 1595(0.46%) | 1322(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (TOB_1_64_32) | packet_fifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo | 1397(0.40%) | 1124(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila | 1397(0.40%) | 1124(0.32%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core | 1396(0.40%) | 1123(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register | 908(0.26%) | 907(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register | 326(0.09%) | 325(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | alternate_cttc.fm_interface_3 | Full_Mode_CTTC | 5737(1.66%) | 4997(1.44%) | 64(0.04%) | 676(0.39%) | 9279(1.34%) | 16(1.36%) | 4(0.17%) | 0(0.00%) | | (alternate_cttc.fm_interface_3) | Full_Mode_CTTC | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CTTC_receiver | combined_ttc_no_mgt | 1749(0.50%) | 1430(0.41%) | 0(0.00%) | 319(0.18%) | 3092(0.45%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (CTTC_receiver) | combined_ttc_no_mgt | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_frame_check | sume_RO_Rx_GT_FRAME_CHECK | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_rx2_inst | ila_2 | 1574(0.45%) | 1255(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_rx2_inst) | ila_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_2_ila_v6_2_12_ila | 1574(0.45%) | 1255(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_2_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_2_ila_v6_2_12_ila_core | 1573(0.45%) | 1254(0.36%) | 0(0.00%) | 319(0.18%) | 2578(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_2_ila_v6_2_12_ila_core | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 255(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_2_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_2_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[10].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[11].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[8].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[9].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy | 82(0.02%) | 35(0.01%) | 0(0.00%) | 47(0.03%) | 137(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_2_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_2_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_2_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_2_ila_v6_2_12_ila_cap_addrgen | 67(0.02%) | 30(0.01%) | 0(0.00%) | 37(0.02%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_2_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_2_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_2_ila_v6_2_12_ila_cap_sample_counter | 33(0.01%) | 20(0.01%) | 0(0.00%) | 13(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_2_ila_v6_2_12_ila_cap_sample_counter | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_2_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_2_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_2_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_2_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_83 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_84 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_2_ila_v6_2_12_ila_cap_window_counter | 30(0.01%) | 9(0.01%) | 0(0.00%) | 21(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_2_ila_v6_2_12_ila_cap_window_counter | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_2_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_2_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_2_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_2_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_2_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_79 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_80 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_2_ila_v6_2_12_ila_register | 1003(0.29%) | 1002(0.29%) | 0(0.00%) | 1(0.01%) | 1439(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_2_ila_v6_2_12_ila_register | 328(0.09%) | 327(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_2_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_2_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_73 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_2_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_72 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_2_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_2_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_2_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_2_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_2_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_76 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_2_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_2_xsdbs_v1_0_2_reg__parameterized43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_2_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_2_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_2_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_2_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_2_xsdbs_v1_0_2_reg__parameterized66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_2_xsdbs_v1_0_2_reg__parameterized67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_2_xsdbs_v1_0_2_reg__parameterized69 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_2_xsdbs_v1_0_2_reg__parameterized71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_2_xsdbs_v1_0_2_reg__parameterized74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_2_xsdbs_v1_0_2_reg__parameterized74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_2_xsdbs_v1_0_2_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_2_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_2_ila_v6_2_12_ila_reset_ctrl | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_2_ila_v6_2_12_ila_reset_ctrl | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_2_ila_v6_2_12_ila_trigger | 268(0.08%) | 107(0.03%) | 0(0.00%) | 161(0.09%) | 475(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_2_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_2_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_2_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_58 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_2_ila_v6_2_12_ila_trig_match | 258(0.07%) | 106(0.03%) | 0(0.00%) | 152(0.09%) | 456(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_2_ila_v6_2_12_ila_trig_match | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_54 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_56 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_57 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__5 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_2_ltlib_v1_0_0_match__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_2_ltlib_v1_0_0_match__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_2_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_51 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_2_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_2_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_2_ltlib_v1_0_0_generic_memrd | 102(0.03%) | 100(0.03%) | 0(0.00%) | 2(0.01%) | 238(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_regs | rx_registers | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_ttc | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_ttc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_stretcher | pulse_stretch__parameterized7_27 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_0 | FM_channel__xdcDup__3 | 1821(0.53%) | 1614(0.47%) | 32(0.02%) | 175(0.10%) | 2787(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_0) | FM_channel__xdcDup__3 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi_35 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__9 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux_36 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode | 1195(0.34%) | 1023(0.30%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila | 1195(0.34%) | 1023(0.30%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core | 1194(0.34%) | 1022(0.30%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register | 916(0.26%) | 915(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__3 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__3 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__9 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__9 | 175(0.05%) | 175(0.05%) | 0(0.00%) | 0(0.00%) | 168(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_37 | 158(0.05%) | 158(0.05%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_39 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__3 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_1 | FM_channel__xdcDup__4 | 1826(0.53%) | 1619(0.47%) | 32(0.02%) | 175(0.10%) | 2793(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_1) | FM_channel__xdcDup__4 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD1529 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD1530 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD1531 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD1532 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD1533 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD1534 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD1534 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD1535 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD1536 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD1537 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD1539 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD1540 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD1541 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD1542 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD1543 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory_HD1544 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem_HD1545 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD1546 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD1546 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD1547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD1548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD1549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD1550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi_28 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__8 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux_29 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD1644 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD1644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD1645 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD1645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD1646 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD1646 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD1647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD1648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD1649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD1656 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD1656 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD1657 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD1658 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD1659 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD1660 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD1660 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD1661 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD1662 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD1662 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD1663 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD1664 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD1665 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD1666 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD1667 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD1667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD1668 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD1668 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD1669 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD1670 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD1671 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD1671 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD1672 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD1673 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD1674 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD1675 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD1676 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD1676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD1677 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD1677 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1678 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1679 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD1680 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD1681 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD1681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD1682 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD1682 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD1683 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD1684 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD1685 | 914(0.26%) | 913(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD1685 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD1686 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1687 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1688 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1689 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1690 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1691 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1692 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1693 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1694 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1695 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1696 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1697 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD1698 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1699 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD1700 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD1701 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD1702 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD1703 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD1704 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD1705 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD1706 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD1707 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD1708 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD1709 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD1710 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD1711 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD1712 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD1713 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD1714 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD1715 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1716 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD1717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD1718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD1719 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD1720 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD1721 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD1722 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD1723 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1724 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD1725 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD1726 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD1727 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD1728 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD1729 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD1730 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD1731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD1732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD1733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD1734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD1735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD1735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD1736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD1737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD1738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD1739 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD1740 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD1741 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD1742 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD1742 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD1743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD1744 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD1744 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD1745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD1746 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD1747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD1748 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD1749 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD1750 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD1751 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD1751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD1752 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD1752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD1753 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD1753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD1754 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD1754 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD1755 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD1756 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD1757 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD1757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD1758 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD1758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD1759 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD1759 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD1760 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD1761 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD1762 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD1762 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD1763 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD1763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD1764 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD1764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD1765 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD1765 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD1766 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD1767 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD1768 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD1769 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD1770 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD1770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD1771 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD1771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1772 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1772 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD1773 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD1774 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD1774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD1775 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD1775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD1776 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD1776 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1777 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD1778 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD1778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD1779 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD1779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD1780 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD1780 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD1781 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD1782 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD1783 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD1784 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD1785 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD1785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD1786 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD1786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1787 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1787 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD1788 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD1789 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD1789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD1790 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD1790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1791 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1791 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD1792 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD1793 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD1793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD1794 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD1794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1795 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1795 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD1796 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD1797 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD1797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD1798 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD1798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1799 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1799 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD1800 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD1801 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD1801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD1802 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD1802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1803 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1803 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD1804 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD1805 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD1805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD1806 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD1806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1807 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1807 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD1808 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD1809 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD1809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD1810 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD1810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1811 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1811 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1812 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD1813 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD1813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD1814 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD1814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1815 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1815 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD1816 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD1817 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__4 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__4 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__8 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__8 | 181(0.05%) | 181(0.05%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_30 | 157(0.05%) | 157(0.05%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eob_space_trig | pulse_pdxx_pwxx_31 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sob_space_trig | pulse_pdxx_pwxx_33 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_34 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__4 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2614 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2615 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2616 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2617 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2618 | 59(0.02%) | 56(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2619 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2619 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2620 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2621 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2622 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2623 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2624 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2625 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2626 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as_HD2627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2628 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2629 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2630 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2631 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2632 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2633 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2634 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2635 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2635 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2636 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2637 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2637 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2519 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2520 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2521 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2522 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2523 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2523 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2524 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2525 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2526 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2528 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_blk | clk_wiz_240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_240_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | combined_transceiver | FullMode_tx_CTTC_rx_support | 235(0.07%) | 228(0.07%) | 0(0.00%) | 7(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (combined_transceiver) | FullMode_tx_CTTC_rx_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_CTTC_rx_init_i | FullMode_tx_CTTC_rx | 156(0.05%) | 149(0.04%) | 0(0.00%) | 7(0.01%) | 237(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | FullMode_tx_CTTC_rx_init | 156(0.05%) | 149(0.04%) | 0(0.00%) | 7(0.01%) | 237(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | FullMode_tx_CTTC_rx_init | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_CTTC_rx_i | FullMode_tx_CTTC_rx_multi_gt | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | FullMode_tx_CTTC_rx_cpll_railing | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_FullMode_tx_CTTC_rx_i | FullMode_tx_CTTC_rx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | FullMode_tx_CTTC_rx_RX_STARTUP_FSM | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | FullMode_tx_CTTC_rx_RX_STARTUP_FSM | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullMode_tx_CTTC_rx_sync_block_5 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullMode_tx_CTTC_rx_sync_block_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullMode_tx_CTTC_rx_sync_block_7 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullMode_tx_CTTC_rx_sync_block_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullMode_tx_CTTC_rx_sync_block_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullMode_tx_CTTC_rx_sync_block_10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullMode_tx_CTTC_rx_sync_block_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | FullMode_tx_CTTC_rx_TX_STARTUP_FSM | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | FullMode_tx_CTTC_rx_TX_STARTUP_FSM | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | FullMode_tx_CTTC_rx_sync_block | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | FullMode_tx_CTTC_rx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullMode_tx_CTTC_rx_sync_block_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullMode_tx_CTTC_rx_sync_block_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullMode_tx_CTTC_rx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | FullMode_tx_CTTC_rx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_i | FullMode_tx | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | FullMode_tx_init | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FullMode_tx_i | FullMode_tx_multi_gt | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_FullMode_tx_i | FullMode_tx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | FullMode_tx_TX_STARTUP_FSM | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | FullMode_tx_TX_STARTUP_FSM | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | FullMode_tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | FullMode_tx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullMode_tx_sync_block_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullMode_tx_sync_block_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullMode_tx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | FullMode_tx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | FullMode_tx_CTTC_rx_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | FullMode_tx_CTTC_rx_common_reset | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | FullMode_tx_CTTC_rx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | polarity | vio_ttc_HD5 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (polarity) | vio_ttc_HD5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD6 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD7 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD11 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | backplane | aurora_64b_rx_12ch | 15373(4.44%) | 13869(4.00%) | 0(0.00%) | 1504(0.86%) | 21734(3.14%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (backplane) | aurora_64b_rx_12ch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_10 | aurora_rx_4l_64b_exdes__parameterized2 | 1057(0.31%) | 965(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_10) | aurora_rx_4l_64b_exdes__parameterized2 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_4l_64b_support__parameterized1 | 1012(0.29%) | 920(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_4l_64b_support__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_4l_64b_CLOCK_MODULE_1519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_common.aurora_rx_4l_64b_i | aurora_rx_4l_64b_HD2759 | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_4l_64b_core_HD2760 | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_4l_64b_core_HD2760 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_4l_64b_RESET_LOGIC_HD2761 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_4l_64b_RESET_LOGIC_HD2761 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_36_HD2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_37_HD2763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_HD2764 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_4l_64b_GT_WRAPPER_HD2765 | 249(0.07%) | 217(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_4l_64b_GT_WRAPPER_HD2765 | 20(0.01%) | 16(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_multi_gt_i | aurora_rx_4l_64b_multi_gt_HD2766 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_HD2767 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_33_HD2768 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_34_HD2769 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_35_HD2770 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_4l_64b_rx_startup_fsm_HD2771 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_4l_64b_rx_startup_fsm_HD2771 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_4l_64b_cdc_sync_23_HD2773 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_25_HD2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_4l_64b_cdc_sync_26_HD2776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_28_HD2778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_29_HD2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_32_HD2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_21_HD2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_0_HD2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_4l_64b_cdc_sync_1_HD2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_HD2788 | 100(0.03%) | 98(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_16_HD2789 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_16_HD2789 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_20_HD2790 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17_HD2791 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18_HD2792 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_19_HD2793 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2_HD2794 | 96(0.03%) | 94(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_11_HD2795 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_11_HD2795 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_15_HD2796 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12_HD2797 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13_HD2798 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_14_HD2799 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3_HD2800 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_6_HD2801 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_6_HD2801 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_10_HD2802 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7_HD2803 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8_HD2804 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_9_HD2805 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4_HD2806 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_HD2807 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_HD2807 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_HD2808 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_HD2809 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_HD2810 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_HD2811 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX_HD2812 | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD2813 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX_HD2814 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_4l_64b_RX_LL_HD2815 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD2816 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD2816 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_4l_64b_OUTPUT_MUX_HD2817 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_4l_64b_SIDEBAND_OUTPUT_HD2818 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_4l_64b_RX_LL_DEFRAMER_HD2819 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_4l_64b_LEFT_ALIGN_CONTROL_HD2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_4l_64b_VALID_DATA_COUNTER_5_HD2821 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_4l_64b_LEFT_ALIGN_MUX_HD2822 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL_HD2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_4l_64b_STORAGE_CE_CONTROL_HD2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_4l_64b_STORAGE_COUNT_CONTROL_HD2825 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL_HD2826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_4l_64b_STORAGE_MUX_HD2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD2828 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD2828 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL_HD2829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_HD2830 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_4l_64b_UFC_OUTPUT_MUX_HD2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT_HD2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL_HD2834 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_4l_64b_UFC_STORAGE_MUX_HD2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL_HD2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_4l_64b_VALID_DATA_COUNTER_HD2837 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_4l_64b_UFC_FILTER_HD2838 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1520 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1520 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_4l_64b_cdc_sync_exdes_1521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_11 | aurora_rx_1q_exdes__xdcDup__5 | 1051(0.30%) | 959(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_11) | aurora_rx_1q_exdes__xdcDup__5 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_1q_support__xdcDup__5 | 1006(0.29%) | 914(0.26%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_1q_support__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_1q_CLOCK_MODULE_1515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_1q_SUPPORT_RESET_LOGIC_1516 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_1q_SUPPORT_RESET_LOGIC_1516 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_1q_cdc_sync_exdes_1518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_1q_i | aurora_rx_1q_HD3484 | 1004(0.29%) | 912(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_1q_i) | aurora_rx_1q_HD3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_1q_core_HD3485 | 1004(0.29%) | 912(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_1q_core_HD3485 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_1q_RESET_LOGIC_HD3486 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_1q_RESET_LOGIC_HD3486 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_36_HD3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_37_HD3488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_1q_cdc_sync_HD3489 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_1q_GT_WRAPPER_HD3490 | 245(0.07%) | 213(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_1q_GT_WRAPPER_HD3490 | 19(0.01%) | 15(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_multi_gt_i | aurora_rx_1q_multi_gt_HD3491 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_1q_i | aurora_rx_1q_gt_HD3492 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_1q_i | aurora_rx_1q_gt_33_HD3493 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_1q_i | aurora_rx_1q_gt_34_HD3494 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_1q_i | aurora_rx_1q_gt_35_HD3495 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_1q_rx_startup_fsm_HD3496 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_1q_rx_startup_fsm_HD3496 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_1q_cdc_sync_23_HD3498 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_25_HD3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_1q_cdc_sync_26_HD3501 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_28_HD3503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_29_HD3504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_32_HD3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_21_HD3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_1q_cdc_sync_0_HD3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_1q_cdc_sync_1_HD3512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_HD3513 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_16_HD3514 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_16_HD3514 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_20_HD3515 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_17_HD3516 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_18_HD3517 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_19_HD3518 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_2_HD3519 | 96(0.03%) | 94(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_11_HD3520 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_11_HD3520 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_15_HD3521 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_12_HD3522 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_13_HD3523 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_14_HD3524 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_3_HD3525 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_6_HD3526 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_6_HD3526 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_10_HD3527 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_7_HD3528 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_8_HD3529 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_9_HD3530 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_4_HD3531 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_HD3532 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_HD3532 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_HD3533 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_HD3534 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_HD3535 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_HD3536 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_1q_RX_GLOBAL_LOGIC_SIMPLEX_HD3537 | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_1q_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3538 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_1q_RX_CHANNEL_INIT_SM_SIMPLEX_HD3539 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_1q_RX_LL_HD3540 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3541 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3541 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_1q_OUTPUT_MUX_HD3542 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_1q_SIDEBAND_OUTPUT_HD3543 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_1q_RX_LL_DEFRAMER_HD3544 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_1q_LEFT_ALIGN_CONTROL_HD3545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_1q_VALID_DATA_COUNTER_5_HD3546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_1q_LEFT_ALIGN_MUX_HD3547 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_1q_OUTPUT_SWITCH_CONTROL_HD3548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_1q_STORAGE_CE_CONTROL_HD3549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_1q_STORAGE_COUNT_CONTROL_HD3550 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_1q_STORAGE_SWITCH_CONTROL_HD3551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_1q_STORAGE_MUX_HD3552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3553 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3553 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_1q_UFC_BARREL_SHIFTER_CONTROL_HD3554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_1q_UFC_BARREL_SHIFTER_HD3555 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_1q_UFC_OUTPUT_MUX_HD3556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_1q_UFC_SIDEBAND_OUTPUT_HD3558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_1q_UFC_STORAGE_COUNT_CONTROL_HD3559 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_1q_UFC_STORAGE_MUX_HD3560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_1q_UFC_STORAGE_SWITCH_CONTROL_HD3561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_1q_VALID_DATA_COUNTER_HD3562 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_1q_UFC_FILTER_HD3563 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_1q_gt_common_wrapper_1517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_12 | aurora_rx_4l_64b_exdes__xdcDup__4 | 1055(0.30%) | 963(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_12) | aurora_rx_4l_64b_exdes__xdcDup__4 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_4l_64b_support__xdcDup__4 | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_4l_64b_support__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_4l_64b_CLOCK_MODULE_1511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1512 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1512 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_4l_64b_cdc_sync_exdes_1514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_4l_64b_i | aurora_rx_4l_64b_HD3079 | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_4l_64b_i) | aurora_rx_4l_64b_HD3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_4l_64b_core_HD3080 | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_4l_64b_core_HD3080 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_4l_64b_RESET_LOGIC_HD3081 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_4l_64b_RESET_LOGIC_HD3081 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_36_HD3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_37_HD3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_HD3084 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_4l_64b_GT_WRAPPER_HD3085 | 248(0.07%) | 216(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_4l_64b_GT_WRAPPER_HD3085 | 20(0.01%) | 16(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_multi_gt_i | aurora_rx_4l_64b_multi_gt_HD3086 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_HD3087 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_33_HD3088 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_34_HD3089 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_35_HD3090 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_4l_64b_rx_startup_fsm_HD3091 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_4l_64b_rx_startup_fsm_HD3091 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_4l_64b_cdc_sync_23_HD3093 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_25_HD3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_4l_64b_cdc_sync_26_HD3096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_28_HD3098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_29_HD3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_32_HD3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_21_HD3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_0_HD3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_4l_64b_cdc_sync_1_HD3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_HD3108 | 100(0.03%) | 98(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_16_HD3109 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_16_HD3109 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_20_HD3110 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17_HD3111 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18_HD3112 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_19_HD3113 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2_HD3114 | 96(0.03%) | 94(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_11_HD3115 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_11_HD3115 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_15_HD3116 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12_HD3117 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13_HD3118 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_14_HD3119 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3_HD3120 | 93(0.03%) | 91(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_6_HD3121 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_6_HD3121 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_10_HD3122 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7_HD3123 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8_HD3124 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_9_HD3125 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4_HD3126 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_HD3127 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_HD3127 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_HD3128 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_HD3129 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_HD3130 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_HD3131 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX_HD3132 | 45(0.01%) | 41(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3133 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX_HD3134 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_4l_64b_RX_LL_HD3135 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD3136 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD3136 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_4l_64b_OUTPUT_MUX_HD3137 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_4l_64b_SIDEBAND_OUTPUT_HD3138 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_4l_64b_RX_LL_DEFRAMER_HD3139 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_4l_64b_LEFT_ALIGN_CONTROL_HD3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_4l_64b_VALID_DATA_COUNTER_5_HD3141 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_4l_64b_LEFT_ALIGN_MUX_HD3142 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL_HD3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_4l_64b_STORAGE_CE_CONTROL_HD3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_4l_64b_STORAGE_COUNT_CONTROL_HD3145 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL_HD3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_4l_64b_STORAGE_MUX_HD3147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD3148 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD3148 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL_HD3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_HD3150 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_4l_64b_UFC_OUTPUT_MUX_HD3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT_HD3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL_HD3154 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_4l_64b_UFC_STORAGE_MUX_HD3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL_HD3156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_4l_64b_VALID_DATA_COUNTER_HD3157 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_4l_64b_UFC_FILTER_HD3158 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_4l_64b_gt_common_wrapper_1513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_13 | aurora_rx_1q_exdes | 1055(0.30%) | 963(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_13) | aurora_rx_1q_exdes | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_1q_support | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_1q_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_1q_CLOCK_MODULE_1507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_1q_SUPPORT_RESET_LOGIC_1508 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_1q_SUPPORT_RESET_LOGIC_1508 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_1q_cdc_sync_exdes_1510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_1q_i | aurora_rx_1q | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_1q_i) | aurora_rx_1q | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_1q_core | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_1q_core | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_1q_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_1q_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_1q_cdc_sync | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_1q_GT_WRAPPER | 249(0.07%) | 217(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_1q_GT_WRAPPER | 19(0.01%) | 15(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_multi_gt_i | aurora_rx_1q_multi_gt | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_1q_i | aurora_rx_1q_gt | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_1q_i | aurora_rx_1q_gt_33 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_1q_i | aurora_rx_1q_gt_34 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_1q_i | aurora_rx_1q_gt_35 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_1q_rx_startup_fsm | 93(0.03%) | 93(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_1q_rx_startup_fsm | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_1q_cdc_sync_23 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_1q_cdc_sync_26 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_1q_cdc_sync_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_1q_cdc_sync_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_16 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_16 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_20 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_17 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_18 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_19 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_2 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_11 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_11 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_15 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_12 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_13 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_3 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_6 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_10 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_7 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_8 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_9 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_4 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_1q_RX_GLOBAL_LOGIC_SIMPLEX | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_1q_RX_CHANNEL_ERR_DETECT_SIMPLEX | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_1q_RX_CHANNEL_INIT_SM_SIMPLEX | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_1q_RX_LL | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_1q_RX_LL_PDU_DATAPATH | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_1q_RX_LL_PDU_DATAPATH | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_1q_OUTPUT_MUX | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_1q_SIDEBAND_OUTPUT | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_1q_RX_LL_DEFRAMER | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_1q_LEFT_ALIGN_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_1q_VALID_DATA_COUNTER_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_1q_LEFT_ALIGN_MUX | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_1q_OUTPUT_SWITCH_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_1q_STORAGE_CE_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_1q_STORAGE_COUNT_CONTROL | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_1q_STORAGE_SWITCH_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_1q_STORAGE_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_1q_RX_LL_UFC_DATAPATH | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_1q_RX_LL_UFC_DATAPATH | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_1q_UFC_BARREL_SHIFTER_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_1q_UFC_BARREL_SHIFTER | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_1q_UFC_OUTPUT_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_1q_UFC_SIDEBAND_OUTPUT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_1q_UFC_STORAGE_COUNT_CONTROL | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_1q_UFC_STORAGE_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_1q_UFC_STORAGE_SWITCH_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_1q_VALID_DATA_COUNTER | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_1q_UFC_FILTER | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_1q_gt_common_wrapper_1509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_14 | aurora_rx_4l_64b_exdes | 1056(0.30%) | 964(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_14) | aurora_rx_4l_64b_exdes | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_4l_64b_support | 1012(0.29%) | 920(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_4l_64b_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_4l_64b_CLOCK_MODULE_1503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1504 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1504 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_4l_64b_cdc_sync_exdes_1506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_4l_64b_i | aurora_rx_4l_64b | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_4l_64b_i) | aurora_rx_4l_64b | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_4l_64b_core | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_4l_64b_core | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_4l_64b_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_4l_64b_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_4l_64b_GT_WRAPPER | 248(0.07%) | 216(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_4l_64b_GT_WRAPPER | 20(0.01%) | 16(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_multi_gt_i | aurora_rx_4l_64b_multi_gt | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_33 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_34 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_35 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_4l_64b_rx_startup_fsm | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_4l_64b_rx_startup_fsm | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_4l_64b_cdc_sync_23 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_4l_64b_cdc_sync_26 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_4l_64b_cdc_sync_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_16 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_16 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_20 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_19 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_11 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_11 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_15 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_6 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_10 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_9 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_4l_64b_RX_LL | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_4l_64b_OUTPUT_MUX | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_4l_64b_SIDEBAND_OUTPUT | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_4l_64b_RX_LL_DEFRAMER | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_4l_64b_LEFT_ALIGN_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_4l_64b_VALID_DATA_COUNTER_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_4l_64b_LEFT_ALIGN_MUX | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_4l_64b_STORAGE_CE_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_4l_64b_STORAGE_COUNT_CONTROL | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_4l_64b_STORAGE_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_4l_64b_UFC_OUTPUT_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_4l_64b_UFC_STORAGE_MUX | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_4l_64b_VALID_DATA_COUNTER | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_4l_64b_UFC_FILTER | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_4l_64b_gt_common_wrapper_1505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_3 | aurora_rx_1q_exdes__xdcDup__1 | 1059(0.31%) | 967(0.28%) | 0(0.00%) | 92(0.05%) | 1428(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_3) | aurora_rx_1q_exdes__xdcDup__1 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_1q_support__xdcDup__1 | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_1q_support__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_1q_CLOCK_MODULE_1499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_1q_SUPPORT_RESET_LOGIC_1500 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_1q_SUPPORT_RESET_LOGIC_1500 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_1q_cdc_sync_exdes_1502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_1q_i | aurora_rx_1q_HD3164 | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_1q_i) | aurora_rx_1q_HD3164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_1q_core_HD3165 | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_1q_core_HD3165 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_1q_RESET_LOGIC_HD3166 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_1q_RESET_LOGIC_HD3166 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_36_HD3167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_37_HD3168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_1q_cdc_sync_HD3169 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_1q_GT_WRAPPER_HD3170 | 246(0.07%) | 214(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_1q_GT_WRAPPER_HD3170 | 19(0.01%) | 15(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_multi_gt_i | aurora_rx_1q_multi_gt_HD3171 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_1q_i | aurora_rx_1q_gt_HD3172 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_1q_i | aurora_rx_1q_gt_33_HD3173 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_1q_i | aurora_rx_1q_gt_34_HD3174 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_1q_i | aurora_rx_1q_gt_35_HD3175 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_1q_rx_startup_fsm_HD3176 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_1q_rx_startup_fsm_HD3176 | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_1q_cdc_sync_23_HD3178 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_25_HD3180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_1q_cdc_sync_26_HD3181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_28_HD3183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_29_HD3184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_32_HD3187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_21_HD3188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_1q_cdc_sync_0_HD3189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_1q_cdc_sync_1_HD3192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_HD3193 | 100(0.03%) | 98(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_16_HD3194 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_16_HD3194 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_20_HD3195 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_17_HD3196 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_18_HD3197 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_19_HD3198 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_2_HD3199 | 96(0.03%) | 94(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_11_HD3200 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_11_HD3200 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_15_HD3201 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_12_HD3202 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_13_HD3203 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_14_HD3204 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_3_HD3205 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_6_HD3206 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_6_HD3206 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_10_HD3207 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_7_HD3208 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_8_HD3209 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_9_HD3210 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_4_HD3211 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_HD3212 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_HD3212 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_HD3213 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_HD3214 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_HD3215 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_HD3216 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_1q_RX_GLOBAL_LOGIC_SIMPLEX_HD3217 | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_1q_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3218 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_1q_RX_CHANNEL_INIT_SM_SIMPLEX_HD3219 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_1q_RX_LL_HD3220 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3221 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3221 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_1q_OUTPUT_MUX_HD3222 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_1q_SIDEBAND_OUTPUT_HD3223 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_1q_RX_LL_DEFRAMER_HD3224 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_1q_LEFT_ALIGN_CONTROL_HD3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_1q_VALID_DATA_COUNTER_5_HD3226 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_1q_LEFT_ALIGN_MUX_HD3227 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_1q_OUTPUT_SWITCH_CONTROL_HD3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_1q_STORAGE_CE_CONTROL_HD3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_1q_STORAGE_COUNT_CONTROL_HD3230 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_1q_STORAGE_SWITCH_CONTROL_HD3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_1q_STORAGE_MUX_HD3232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3233 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3233 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_1q_UFC_BARREL_SHIFTER_CONTROL_HD3234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_1q_UFC_BARREL_SHIFTER_HD3235 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_1q_UFC_OUTPUT_MUX_HD3236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_1q_UFC_SIDEBAND_OUTPUT_HD3238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_1q_UFC_STORAGE_COUNT_CONTROL_HD3239 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_1q_UFC_STORAGE_MUX_HD3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_1q_UFC_STORAGE_SWITCH_CONTROL_HD3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_1q_VALID_DATA_COUNTER_HD3242 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_1q_UFC_FILTER_HD3243 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_1q_gt_common_wrapper_1501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_4 | aurora_rx_4l_64b_exdes__xdcDup__1 | 1055(0.30%) | 963(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_4) | aurora_rx_4l_64b_exdes__xdcDup__1 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_4l_64b_support__xdcDup__1 | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_4l_64b_support__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_4l_64b_CLOCK_MODULE_1495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1496 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1496 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_4l_64b_cdc_sync_exdes_1498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_4l_64b_i | aurora_rx_4l_64b_HD2839 | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_4l_64b_i) | aurora_rx_4l_64b_HD2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_4l_64b_core_HD2840 | 1008(0.29%) | 916(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_4l_64b_core_HD2840 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_4l_64b_RESET_LOGIC_HD2841 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_4l_64b_RESET_LOGIC_HD2841 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_36_HD2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_37_HD2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_HD2844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_4l_64b_GT_WRAPPER_HD2845 | 249(0.07%) | 217(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_4l_64b_GT_WRAPPER_HD2845 | 20(0.01%) | 16(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_multi_gt_i | aurora_rx_4l_64b_multi_gt_HD2846 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_HD2847 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_33_HD2848 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_34_HD2849 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_35_HD2850 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_4l_64b_rx_startup_fsm_HD2851 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_4l_64b_rx_startup_fsm_HD2851 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_4l_64b_cdc_sync_23_HD2853 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_25_HD2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_4l_64b_cdc_sync_26_HD2856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_28_HD2858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_29_HD2859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_32_HD2862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_21_HD2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_0_HD2864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_4l_64b_cdc_sync_1_HD2867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_HD2868 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_16_HD2869 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_16_HD2869 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_20_HD2870 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17_HD2871 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18_HD2872 | 21(0.01%) | 20(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_19_HD2873 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2_HD2874 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_11_HD2875 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_11_HD2875 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_15_HD2876 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12_HD2877 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13_HD2878 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_14_HD2879 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3_HD2880 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_6_HD2881 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_6_HD2881 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_10_HD2882 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7_HD2883 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8_HD2884 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_9_HD2885 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4_HD2886 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_HD2887 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_HD2887 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_HD2888 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_HD2889 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_HD2890 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_HD2891 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX_HD2892 | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD2893 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX_HD2894 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_4l_64b_RX_LL_HD2895 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD2896 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD2896 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_4l_64b_OUTPUT_MUX_HD2897 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_4l_64b_SIDEBAND_OUTPUT_HD2898 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_4l_64b_RX_LL_DEFRAMER_HD2899 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_4l_64b_LEFT_ALIGN_CONTROL_HD2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_4l_64b_VALID_DATA_COUNTER_5_HD2901 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_4l_64b_LEFT_ALIGN_MUX_HD2902 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL_HD2903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_4l_64b_STORAGE_CE_CONTROL_HD2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_4l_64b_STORAGE_COUNT_CONTROL_HD2905 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL_HD2906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_4l_64b_STORAGE_MUX_HD2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD2908 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD2908 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL_HD2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_HD2910 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_4l_64b_UFC_OUTPUT_MUX_HD2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT_HD2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL_HD2914 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_4l_64b_UFC_STORAGE_MUX_HD2915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL_HD2916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_4l_64b_VALID_DATA_COUNTER_HD2917 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_4l_64b_UFC_FILTER_HD2918 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_4l_64b_gt_common_wrapper_1497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_5 | aurora_rx_1q_exdes__xdcDup__2 | 1057(0.31%) | 965(0.28%) | 0(0.00%) | 92(0.05%) | 1428(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_5) | aurora_rx_1q_exdes__xdcDup__2 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_1q_support__xdcDup__2 | 1009(0.29%) | 917(0.26%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_1q_support__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_1q_CLOCK_MODULE_1491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_1q_SUPPORT_RESET_LOGIC_1492 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_1q_SUPPORT_RESET_LOGIC_1492 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_1q_cdc_sync_exdes_1494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_1q_i | aurora_rx_1q_HD3244 | 1007(0.29%) | 915(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_1q_i) | aurora_rx_1q_HD3244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_1q_core_HD3245 | 1007(0.29%) | 915(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_1q_core_HD3245 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_1q_RESET_LOGIC_HD3246 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_1q_RESET_LOGIC_HD3246 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_36_HD3247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_37_HD3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_1q_cdc_sync_HD3249 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_1q_GT_WRAPPER_HD3250 | 248(0.07%) | 216(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_1q_GT_WRAPPER_HD3250 | 19(0.01%) | 15(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_multi_gt_i | aurora_rx_1q_multi_gt_HD3251 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_1q_i | aurora_rx_1q_gt_HD3252 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_1q_i | aurora_rx_1q_gt_33_HD3253 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_1q_i | aurora_rx_1q_gt_34_HD3254 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_1q_i | aurora_rx_1q_gt_35_HD3255 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_1q_rx_startup_fsm_HD3256 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_1q_rx_startup_fsm_HD3256 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_1q_cdc_sync_23_HD3258 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_25_HD3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_1q_cdc_sync_26_HD3261 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_28_HD3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_29_HD3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_32_HD3267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_21_HD3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_1q_cdc_sync_0_HD3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_1q_cdc_sync_1_HD3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_HD3273 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_16_HD3274 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_16_HD3274 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_20_HD3275 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_17_HD3276 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_18_HD3277 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_19_HD3278 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_2_HD3279 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_11_HD3280 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_11_HD3280 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_15_HD3281 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_12_HD3282 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_13_HD3283 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_14_HD3284 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_3_HD3285 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_6_HD3286 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_6_HD3286 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_10_HD3287 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_7_HD3288 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_8_HD3289 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_9_HD3290 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_4_HD3291 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_HD3292 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_HD3292 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_HD3293 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_HD3294 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_HD3295 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_HD3296 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_1q_RX_GLOBAL_LOGIC_SIMPLEX_HD3297 | 45(0.01%) | 41(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_1q_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3298 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_1q_RX_CHANNEL_INIT_SM_SIMPLEX_HD3299 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_1q_RX_LL_HD3300 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3301 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3301 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_1q_OUTPUT_MUX_HD3302 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_1q_SIDEBAND_OUTPUT_HD3303 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_1q_RX_LL_DEFRAMER_HD3304 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_1q_LEFT_ALIGN_CONTROL_HD3305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_1q_VALID_DATA_COUNTER_5_HD3306 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_1q_LEFT_ALIGN_MUX_HD3307 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_1q_OUTPUT_SWITCH_CONTROL_HD3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_1q_STORAGE_CE_CONTROL_HD3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_1q_STORAGE_COUNT_CONTROL_HD3310 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_1q_STORAGE_SWITCH_CONTROL_HD3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_1q_STORAGE_MUX_HD3312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3313 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3313 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_1q_UFC_BARREL_SHIFTER_CONTROL_HD3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_1q_UFC_BARREL_SHIFTER_HD3315 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_1q_UFC_OUTPUT_MUX_HD3316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_1q_UFC_SIDEBAND_OUTPUT_HD3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_1q_UFC_STORAGE_COUNT_CONTROL_HD3319 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_1q_UFC_STORAGE_MUX_HD3320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_1q_UFC_STORAGE_SWITCH_CONTROL_HD3321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_1q_VALID_DATA_COUNTER_HD3322 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_1q_UFC_FILTER_HD3323 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_1q_gt_common_wrapper_1493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_6 | aurora_rx_4l_64b_exdes__xdcDup__2 | 1056(0.30%) | 964(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_6) | aurora_rx_4l_64b_exdes__xdcDup__2 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_4l_64b_support__xdcDup__2 | 1012(0.29%) | 920(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_4l_64b_support__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_4l_64b_CLOCK_MODULE_1487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1488 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1488 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_4l_64b_cdc_sync_exdes_1490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_4l_64b_i | aurora_rx_4l_64b_HD2919 | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_4l_64b_i) | aurora_rx_4l_64b_HD2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_4l_64b_core_HD2920 | 1010(0.29%) | 918(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_4l_64b_core_HD2920 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_4l_64b_RESET_LOGIC_HD2921 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_4l_64b_RESET_LOGIC_HD2921 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_36_HD2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_37_HD2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_HD2924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_4l_64b_GT_WRAPPER_HD2925 | 249(0.07%) | 217(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_4l_64b_GT_WRAPPER_HD2925 | 20(0.01%) | 16(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_multi_gt_i | aurora_rx_4l_64b_multi_gt_HD2926 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_HD2927 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_33_HD2928 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_34_HD2929 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_35_HD2930 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_4l_64b_rx_startup_fsm_HD2931 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_4l_64b_rx_startup_fsm_HD2931 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_4l_64b_cdc_sync_23_HD2933 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_25_HD2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_4l_64b_cdc_sync_26_HD2936 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_28_HD2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_29_HD2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_32_HD2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_21_HD2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_0_HD2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_4l_64b_cdc_sync_1_HD2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_HD2948 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_16_HD2949 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_16_HD2949 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_20_HD2950 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17_HD2951 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18_HD2952 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_19_HD2953 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2_HD2954 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_11_HD2955 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_11_HD2955 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_15_HD2956 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12_HD2957 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13_HD2958 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_14_HD2959 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3_HD2960 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_6_HD2961 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_6_HD2961 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_10_HD2962 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7_HD2963 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8_HD2964 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_9_HD2965 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4_HD2966 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_HD2967 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_HD2967 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_HD2968 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_HD2969 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_HD2970 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_HD2971 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX_HD2972 | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD2973 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX_HD2974 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_4l_64b_RX_LL_HD2975 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD2976 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD2976 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_4l_64b_OUTPUT_MUX_HD2977 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_4l_64b_SIDEBAND_OUTPUT_HD2978 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_4l_64b_RX_LL_DEFRAMER_HD2979 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_4l_64b_LEFT_ALIGN_CONTROL_HD2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_4l_64b_VALID_DATA_COUNTER_5_HD2981 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_4l_64b_LEFT_ALIGN_MUX_HD2982 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL_HD2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_4l_64b_STORAGE_CE_CONTROL_HD2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_4l_64b_STORAGE_COUNT_CONTROL_HD2985 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL_HD2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_4l_64b_STORAGE_MUX_HD2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD2988 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD2988 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL_HD2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_HD2990 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_4l_64b_UFC_OUTPUT_MUX_HD2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT_HD2993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL_HD2994 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_4l_64b_UFC_STORAGE_MUX_HD2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL_HD2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_4l_64b_VALID_DATA_COUNTER_HD2997 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_4l_64b_UFC_FILTER_HD2998 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_4l_64b_gt_common_wrapper_1489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_7 | aurora_rx_1q_exdes__xdcDup__3 | 1057(0.31%) | 965(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_7) | aurora_rx_1q_exdes__xdcDup__3 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_1q_support__xdcDup__3 | 1013(0.29%) | 921(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_1q_support__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_1q_CLOCK_MODULE_1483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_1q_SUPPORT_RESET_LOGIC_1484 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_1q_SUPPORT_RESET_LOGIC_1484 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_1q_cdc_sync_exdes_1486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_1q_i | aurora_rx_1q_HD3324 | 1011(0.29%) | 919(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_1q_i) | aurora_rx_1q_HD3324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_1q_core_HD3325 | 1011(0.29%) | 919(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_1q_core_HD3325 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_1q_RESET_LOGIC_HD3326 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_1q_RESET_LOGIC_HD3326 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_36_HD3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_37_HD3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_1q_cdc_sync_HD3329 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_1q_GT_WRAPPER_HD3330 | 248(0.07%) | 216(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_1q_GT_WRAPPER_HD3330 | 19(0.01%) | 15(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_multi_gt_i | aurora_rx_1q_multi_gt_HD3331 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_1q_i | aurora_rx_1q_gt_HD3332 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_1q_i | aurora_rx_1q_gt_33_HD3333 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_1q_i | aurora_rx_1q_gt_34_HD3334 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_1q_i | aurora_rx_1q_gt_35_HD3335 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_1q_rx_startup_fsm_HD3336 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_1q_rx_startup_fsm_HD3336 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_1q_cdc_sync_23_HD3338 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_25_HD3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_1q_cdc_sync_26_HD3341 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_28_HD3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_29_HD3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_32_HD3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_21_HD3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_1q_cdc_sync_0_HD3349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_1q_cdc_sync_1_HD3352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_HD3353 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_16_HD3354 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_16_HD3354 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_20_HD3355 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_17_HD3356 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_18_HD3357 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_19_HD3358 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_2_HD3359 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_11_HD3360 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_11_HD3360 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_15_HD3361 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_12_HD3362 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_13_HD3363 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_14_HD3364 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_3_HD3365 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_6_HD3366 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_6_HD3366 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_10_HD3367 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_7_HD3368 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_8_HD3369 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_9_HD3370 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_4_HD3371 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_HD3372 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_HD3372 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_HD3373 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_HD3374 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_HD3375 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_HD3376 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_1q_RX_GLOBAL_LOGIC_SIMPLEX_HD3377 | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_1q_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3378 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_1q_RX_CHANNEL_INIT_SM_SIMPLEX_HD3379 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_1q_RX_LL_HD3380 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3381 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3381 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_1q_OUTPUT_MUX_HD3382 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_1q_SIDEBAND_OUTPUT_HD3383 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_1q_RX_LL_DEFRAMER_HD3384 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_1q_LEFT_ALIGN_CONTROL_HD3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_1q_VALID_DATA_COUNTER_5_HD3386 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_1q_LEFT_ALIGN_MUX_HD3387 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_1q_OUTPUT_SWITCH_CONTROL_HD3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_1q_STORAGE_CE_CONTROL_HD3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_1q_STORAGE_COUNT_CONTROL_HD3390 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_1q_STORAGE_SWITCH_CONTROL_HD3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_1q_STORAGE_MUX_HD3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3393 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3393 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_1q_UFC_BARREL_SHIFTER_CONTROL_HD3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_1q_UFC_BARREL_SHIFTER_HD3395 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_1q_UFC_OUTPUT_MUX_HD3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_1q_UFC_SIDEBAND_OUTPUT_HD3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_1q_UFC_STORAGE_COUNT_CONTROL_HD3399 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_1q_UFC_STORAGE_MUX_HD3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_1q_UFC_STORAGE_SWITCH_CONTROL_HD3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_1q_VALID_DATA_COUNTER_HD3402 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_1q_UFC_FILTER_HD3403 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_1q_gt_common_wrapper_1485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_8 | aurora_rx_4l_64b_exdes__xdcDup__3 | 1057(0.31%) | 965(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_8) | aurora_rx_4l_64b_exdes__xdcDup__3 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_4l_64b_support__xdcDup__3 | 1013(0.29%) | 921(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_4l_64b_support__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_4l_64b_CLOCK_MODULE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_4l_64b_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_4l_64b_cdc_sync_exdes | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_4l_64b_i | aurora_rx_4l_64b_HD2999 | 1011(0.29%) | 919(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_4l_64b_i) | aurora_rx_4l_64b_HD2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_4l_64b_core_HD3000 | 1011(0.29%) | 919(0.27%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_4l_64b_core_HD3000 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_4l_64b_RESET_LOGIC_HD3001 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_4l_64b_RESET_LOGIC_HD3001 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_36_HD3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_37_HD3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_HD3004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_4l_64b_GT_WRAPPER_HD3005 | 249(0.07%) | 217(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_4l_64b_GT_WRAPPER_HD3005 | 20(0.01%) | 16(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_multi_gt_i | aurora_rx_4l_64b_multi_gt_HD3006 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_HD3007 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_33_HD3008 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_34_HD3009 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_4l_64b_i | aurora_rx_4l_64b_gt_35_HD3010 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_4l_64b_rx_startup_fsm_HD3011 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_4l_64b_rx_startup_fsm_HD3011 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_4l_64b_cdc_sync_23_HD3013 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_25_HD3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_4l_64b_cdc_sync_26_HD3016 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_28_HD3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_29_HD3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_32_HD3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_21_HD3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_4l_64b_cdc_sync_0_HD3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_4l_64b_cdc_sync_1_HD3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_HD3028 | 100(0.03%) | 98(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_16_HD3029 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_16_HD3029 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_20_HD3030 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17_HD3031 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18_HD3032 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_19_HD3033 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2_HD3034 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_11_HD3035 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_11_HD3035 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_15_HD3036 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12_HD3037 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13_HD3038 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_14_HD3039 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3_HD3040 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_6_HD3041 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_6_HD3041 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_10_HD3042 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7_HD3043 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8_HD3044 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_9_HD3045 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4_HD3046 | 99(0.03%) | 97(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_4l_64b_hotplug_i | aurora_rx_4l_64b_HOTPLUG_HD3047 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_4l_64b_hotplug_i) | aurora_rx_4l_64b_HOTPLUG_HD3047 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_4l_64b_cdc_sync__parameterized2_HD3048 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_HD3049 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_HD3050 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_4l_64b_SYM_DEC_HD3051 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX_HD3052 | 45(0.01%) | 41(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3053 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX_HD3054 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_4l_64b_RX_LL_HD3055 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD3056 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_4l_64b_RX_LL_PDU_DATAPATH_HD3056 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_4l_64b_OUTPUT_MUX_HD3057 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_4l_64b_SIDEBAND_OUTPUT_HD3058 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_4l_64b_RX_LL_DEFRAMER_HD3059 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_4l_64b_LEFT_ALIGN_CONTROL_HD3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_4l_64b_VALID_DATA_COUNTER_5_HD3061 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_4l_64b_LEFT_ALIGN_MUX_HD3062 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL_HD3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_4l_64b_STORAGE_CE_CONTROL_HD3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_4l_64b_STORAGE_COUNT_CONTROL_HD3065 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL_HD3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_4l_64b_STORAGE_MUX_HD3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD3068 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_4l_64b_RX_LL_UFC_DATAPATH_HD3068 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL_HD3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_4l_64b_UFC_BARREL_SHIFTER_HD3070 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_4l_64b_UFC_OUTPUT_MUX_HD3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT_HD3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL_HD3074 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_4l_64b_UFC_STORAGE_MUX_HD3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL_HD3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_4l_64b_VALID_DATA_COUNTER_HD3077 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_4l_64b_UFC_FILTER_HD3078 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_4l_64b_gt_common_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_9 | aurora_rx_1q_exdes__xdcDup__4 | 1056(0.30%) | 964(0.28%) | 0(0.00%) | 92(0.05%) | 1420(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_9) | aurora_rx_1q_exdes__xdcDup__4 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | aurora_rx_1q_support__xdcDup__4 | 1011(0.29%) | 919(0.27%) | 0(0.00%) | 92(0.05%) | 1408(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | aurora_rx_1q_support__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | aurora_rx_1q_CLOCK_MODULE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | aurora_rx_1q_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | aurora_rx_1q_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | aurora_rx_1q_cdc_sync_exdes | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.aurora_rx_1q_i | aurora_rx_1q_HD3404 | 1009(0.29%) | 917(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (use_common.aurora_rx_1q_i) | aurora_rx_1q_HD3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_rx_1q_core_HD3405 | 1009(0.29%) | 917(0.26%) | 0(0.00%) | 92(0.05%) | 1394(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | aurora_rx_1q_core_HD3405 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | aurora_rx_1q_RESET_LOGIC_HD3406 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | aurora_rx_1q_RESET_LOGIC_HD3406 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_36_HD3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_37_HD3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | aurora_rx_1q_cdc_sync_HD3409 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | aurora_rx_1q_GT_WRAPPER_HD3410 | 247(0.07%) | 215(0.06%) | 0(0.00%) | 32(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | aurora_rx_1q_GT_WRAPPER_HD3410 | 19(0.01%) | 15(0.01%) | 0(0.00%) | 4(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_multi_gt_i | aurora_rx_1q_multi_gt_HD3411 | 137(0.04%) | 109(0.03%) | 0(0.00%) | 28(0.02%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_aurora_rx_1q_i | aurora_rx_1q_gt_HD3412 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_aurora_rx_1q_i | aurora_rx_1q_gt_33_HD3413 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_aurora_rx_1q_i | aurora_rx_1q_gt_34_HD3414 | 35(0.01%) | 28(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_aurora_rx_1q_i | aurora_rx_1q_gt_35_HD3415 | 34(0.01%) | 27(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rxresetfsm_i | aurora_rx_1q_rx_startup_fsm_HD3416 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 101(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_rxresetfsm_i) | aurora_rx_1q_rx_startup_fsm_HD3416 | 84(0.02%) | 84(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | aurora_rx_1q_cdc_sync_23_HD3418 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_25_HD3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | aurora_rx_1q_cdc_sync_26_HD3421 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_28_HD3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_29_HD3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_32_HD3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtrxreset_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_21_HD3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hpcnt_reset_cdc_sync | aurora_rx_1q_cdc_sync_0_HD3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | aurora_rx_1q_cdc_sync_1_HD3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_0_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_HD3433 | 100(0.03%) | 98(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_16_HD3434 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_16_HD3434 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_20_HD3435 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_17_HD3436 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_18_HD3437 | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_19_HD3438 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_1_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_2_HD3439 | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_11_HD3440 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_11_HD3440 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_15_HD3441 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_12_HD3442 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_13_HD3443 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_14_HD3444 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_2_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_3_HD3445 | 94(0.03%) | 92(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_6_HD3446 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_6_HD3446 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_10_HD3447 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_7_HD3448 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_8_HD3449 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_9_HD3450 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_aurora_lane_simplex_v5_3_i | aurora_rx_1q_RX_AURORA_LANE_SIMPLEX_V5_4_HD3451 | 98(0.03%) | 96(0.03%) | 0(0.00%) | 2(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_rx_1q_hotplug_i | aurora_rx_1q_HOTPLUG_HD3452 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_rx_1q_hotplug_i) | aurora_rx_1q_HOTPLUG_HD3452 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_cc_cdc_sync | aurora_rx_1q_cdc_sync__parameterized2_HD3453 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_err_detect_simplex_gtp_i | aurora_rx_1q_RX_ERR_DETECT_SIMPLEX_V5_HD3454 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_lane_init_sm_simplex_i | aurora_rx_1q_RX_LANE_INIT_SM_SIMPLEX_HD3455 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_dec_i | aurora_rx_1q_SYM_DEC_HD3456 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_global_logic_simplex_i | aurora_rx_1q_RX_GLOBAL_LOGIC_SIMPLEX_HD3457 | 46(0.01%) | 42(0.01%) | 0(0.00%) | 4(0.01%) | 75(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_err_detect_simplex_i | aurora_rx_1q_RX_CHANNEL_ERR_DETECT_SIMPLEX_HD3458 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_channel_init_sm_simplex_i | aurora_rx_1q_RX_CHANNEL_INIT_SM_SIMPLEX_HD3459 | 42(0.01%) | 38(0.01%) | 0(0.00%) | 4(0.01%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_i | aurora_rx_1q_RX_LL_HD3460 | 325(0.09%) | 277(0.08%) | 0(0.00%) | 48(0.03%) | 533(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_pdu_datapath_i | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3461 | 185(0.05%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 312(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_pdu_datapath_i) | aurora_rx_1q_RX_LL_PDU_DATAPATH_HD3461 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | output_mux_i | aurora_rx_1q_OUTPUT_MUX_HD3462 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sideband_output_i | aurora_rx_1q_SIDEBAND_OUTPUT_HD3463 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_1_rx_ll_deframer_i | aurora_rx_1q_RX_LL_DEFRAMER_HD3464 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_left_align_control_i | aurora_rx_1q_LEFT_ALIGN_CONTROL_HD3465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_2_valid_data_counter_i | aurora_rx_1q_VALID_DATA_COUNTER_5_HD3466 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_left_align_datapath_mux_i | aurora_rx_1q_LEFT_ALIGN_MUX_HD3467 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_output_switch_control_i | aurora_rx_1q_OUTPUT_SWITCH_CONTROL_HD3468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_ce_control_i | aurora_rx_1q_STORAGE_CE_CONTROL_HD3469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_count_control_i | aurora_rx_1q_STORAGE_COUNT_CONTROL_HD3470 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_3_storage_switch_control_i | aurora_rx_1q_STORAGE_SWITCH_CONTROL_HD3471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_4_storage_mux_i | aurora_rx_1q_STORAGE_MUX_HD3472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ll_ufc_datapath_i | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3473 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_ll_ufc_datapath_i) | aurora_rx_1q_RX_LL_UFC_DATAPATH_HD3473 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_control_i | aurora_rx_1q_UFC_BARREL_SHIFTER_CONTROL_HD3474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_barrel_shifter_i | aurora_rx_1q_UFC_BARREL_SHIFTER_HD3475 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_output_mux_i | aurora_rx_1q_UFC_OUTPUT_MUX_HD3476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_sideband_output_i | aurora_rx_1q_UFC_SIDEBAND_OUTPUT_HD3478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_count_control_i | aurora_rx_1q_UFC_STORAGE_COUNT_CONTROL_HD3479 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_mux_i | aurora_rx_1q_UFC_STORAGE_MUX_HD3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_storage_switch_control_i | aurora_rx_1q_UFC_STORAGE_SWITCH_CONTROL_HD3481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_valid_data_counter | aurora_rx_1q_VALID_DATA_COUNTER_HD3482 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_filter_i | aurora_rx_1q_UFC_FILTER_HD3483 | 69(0.02%) | 21(0.01%) | 0(0.00%) | 48(0.03%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | use_common.gt_common_support | aurora_rx_1q_gt_common_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | combined_ttc | combined_ttc_rx | 1851(0.53%) | 1525(0.44%) | 0(0.00%) | 326(0.19%) | 3244(0.47%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (combined_ttc) | combined_ttc_rx | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_frame_check | sume_RO_Rx_GT_FRAME_CHECK__2 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_rx2_inst | ila_2_HD1084 | 1569(0.45%) | 1250(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_rx2_inst) | ila_2_HD1084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_2_ila_v6_2_12_ila_HD1085 | 1569(0.45%) | 1250(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_2_ila_v6_2_12_ila_HD1085 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_2_ila_v6_2_12_ila_core_HD1086 | 1568(0.45%) | 1249(0.36%) | 0(0.00%) | 319(0.18%) | 2578(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_2_ila_v6_2_12_ila_core_HD1086 | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 255(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_2_ila_v6_2_12_ila_trace_memory_HD1087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_2_blk_mem_gen_v8_4_5_HD1088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_synth_HD1089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[10].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized9_HD1094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized9_HD1095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[11].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized10_HD1096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized10_HD1097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD1100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD1101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD1102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD1103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD1104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD1105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4_HD1106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4_HD1107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5_HD1108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5_HD1109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized6_HD1110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized6_HD1111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[8].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized7_HD1112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized7_HD1113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[9].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized8_HD1114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized8_HD1115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD1116 | 81(0.02%) | 34(0.01%) | 0(0.00%) | 47(0.03%) | 137(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD1116 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_2_ltlib_v1_0_0_cfglut6__parameterized0_HD1117 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_2_ltlib_v1_0_0_cfglut7_HD1118 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_2_ltlib_v1_0_0_cfglut7__1_HD1119 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_2_ila_v6_2_12_ila_cap_addrgen_HD1120 | 66(0.02%) | 29(0.01%) | 0(0.00%) | 37(0.02%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_2_ila_v6_2_12_ila_cap_addrgen_HD1120 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_2_ltlib_v1_0_0_cfglut6__1_HD1121 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD1122 | 33(0.01%) | 20(0.01%) | 0(0.00%) | 13(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD1122 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_2_ltlib_v1_0_0_cfglut4__1_HD1123 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_2_ltlib_v1_0_0_cfglut5__1_HD1124 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_2_ltlib_v1_0_0_cfglut6_HD1125 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_2_ltlib_v1_0_0_match_nodelay__1_HD1126 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD1127 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD1127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD1128 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD1128 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_83_HD1129 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_84_HD1130 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_2_ila_v6_2_12_ila_cap_window_counter_HD1131 | 30(0.01%) | 9(0.01%) | 0(0.00%) | 21(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_2_ila_v6_2_12_ila_cap_window_counter_HD1131 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_2_ltlib_v1_0_0_cfglut4_HD1132 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_2_ltlib_v1_0_0_cfglut5_HD1133 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_2_ltlib_v1_0_0_cfglut5__2_HD1134 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_2_ltlib_v1_0_0_match_nodelay_HD1135 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD1136 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD1136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD1137 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD1137 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1138 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1139 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_2_ltlib_v1_0_0_match_nodelay__2_HD1140 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD1141 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD1141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD1142 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD1142 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_79_HD1143 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_80_HD1144 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_2_ila_v6_2_12_ila_register_HD1145 | 1000(0.29%) | 999(0.29%) | 0(0.00%) | 1(0.01%) | 1439(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_2_ila_v6_2_12_ila_register_HD1145 | 327(0.09%) | 326(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s_HD1146 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1147 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1148 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1149 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized12_HD1150 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized13_HD1151 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized14_HD1152 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1153 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1154 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1155 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1156 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1157 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1158 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1159 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1160 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1161 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized15_HD1162 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_2_xsdbs_v1_0_2_xsdbs_HD1163 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_2_xsdbs_v1_0_2_reg__parameterized56_HD1164 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_73_HD1165 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_2_xsdbs_v1_0_2_reg__parameterized57_HD1166 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_72_HD1167 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_2_xsdbs_v1_0_2_reg__parameterized58_HD1168 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_71_HD1169 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_2_xsdbs_v1_0_2_reg__parameterized59_HD1170 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_70_HD1171 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_2_xsdbs_v1_0_2_reg__parameterized60_HD1172 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_69_HD1173 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_2_xsdbs_v1_0_2_reg__parameterized61_HD1174 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_68_HD1175 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_2_xsdbs_v1_0_2_reg__parameterized41_HD1176 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_76_HD1177 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_2_xsdbs_v1_0_2_reg__parameterized42_HD1178 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1179 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_2_xsdbs_v1_0_2_reg__parameterized43_HD1180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_75_HD1181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_2_xsdbs_v1_0_2_reg__parameterized62_HD1182 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_67_HD1183 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_2_xsdbs_v1_0_2_reg__parameterized63_HD1184 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_66_HD1185 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_2_xsdbs_v1_0_2_reg__parameterized64_HD1186 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1187 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_2_xsdbs_v1_0_2_reg__parameterized65_HD1188 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_65_HD1189 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_2_xsdbs_v1_0_2_reg__parameterized66_HD1190 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_64_HD1191 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_2_xsdbs_v1_0_2_reg__parameterized67_HD1192 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_63_HD1193 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_2_xsdbs_v1_0_2_reg__parameterized69_HD1194 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_62_HD1195 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_2_xsdbs_v1_0_2_reg__parameterized71_HD1196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_61_HD1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD1198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD1198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_60_HD1199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_2_xsdbs_v1_0_2_reg__parameterized44_HD1200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_74_HD1201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized16_HD1202 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_2_xsdbs_v1_0_2_reg_stream_HD1203 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_HD1204 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD1205 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD1205 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_HD1206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_2_ila_v6_2_12_ila_reset_ctrl_HD1207 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_2_ila_v6_2_12_ila_reset_ctrl_HD1207 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection_HD1208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__2_HD1209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__3_HD1210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__1_HD1211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer_HD1212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection__1_HD1213 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_2_ila_v6_2_12_ila_trigger_HD1214 | 268(0.08%) | 107(0.03%) | 0(0.00%) | 161(0.09%) | 475(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_2_ila_v6_2_12_ila_trigger_HD1214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_2_ltlib_v1_0_0_match_HD1215 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_2_ltlib_v1_0_0_match_HD1215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_HD1216 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_HD1216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA_HD1217 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA_HD1217 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_58_HD1218 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_59_HD1219 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_2_ila_v6_2_12_ila_trig_match_HD1220 | 258(0.07%) | 106(0.03%) | 0(0.00%) | 152(0.09%) | 456(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_2_ila_v6_2_12_ila_trig_match_HD1220 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD1221 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD1222 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD1222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD1223 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD1223 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_54_HD1224 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_55_HD1225 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_56_HD1226 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_57_HD1227 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD1228 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD1228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD1229 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD1230 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD1230 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_13_HD1231 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_14_HD1232 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_15_HD1233 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD1234 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_2_ltlib_v1_0_0_match__parameterized0_HD1235 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0_HD1235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD1236 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD1236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD1237 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD1237 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_HD1238 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_8_HD1239 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_9_HD1240 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD1241 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD1242 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD1242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD1243 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD1243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD1244 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD1244 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD1245 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD1246 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD1246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD1247 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD1247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD1248 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD1248 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD1249 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_2_ltlib_v1_0_0_match__parameterized3_HD1250 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3_HD1250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD1251 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD1251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD1252 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD1252 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD1253 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_2_ltlib_v1_0_0_match__parameterized1_HD1254 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1_HD1254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD1255 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD1255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD1256 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD1256 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1257 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD1258 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD1258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD1259 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD1259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD1260 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD1260 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_51_HD1261 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD1262 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD1262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD1263 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD1263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD1264 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD1264 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD1265 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD1266 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD1266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD1267 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD1268 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD1268 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_42_HD1269 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_43_HD1270 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_44_HD1271 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_45_HD1272 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD1273 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD1273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD1274 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD1274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD1275 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD1275 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_36_HD1276 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_37_HD1277 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_38_HD1278 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_39_HD1279 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD1280 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD1280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD1281 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD1281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD1282 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD1282 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_30_HD1283 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_31_HD1284 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_32_HD1285 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1286 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_2_ltlib_v1_0_0_match__parameterized2_HD1287 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_2_ltlib_v1_0_0_match__parameterized2_HD1287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD1288 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD1288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD1289 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD1289 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD1290 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD1291 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD1291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD1292 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD1292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1293 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1293 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD1294 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD1295 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD1295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD1296 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1297 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1297 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD1298 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD1299 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD1299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD1300 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD1300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD1301 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD1301 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD1302 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_2_ltlib_v1_0_0_generic_memrd_HD1303 | 102(0.03%) | 100(0.03%) | 0(0.00%) | 2(0.01%) | 238(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_regs | rx_registers__2 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sume_RO_Rx_support_i | sume_RO_Rx_support | 104(0.03%) | 97(0.03%) | 0(0.00%) | 7(0.01%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (sume_RO_Rx_support_i) | sume_RO_Rx_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cttc_Rx_init_i | MGT_combined_ttc_rx | 104(0.03%) | 97(0.03%) | 0(0.00%) | 7(0.01%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | MGT_combined_ttc_rx_init | 104(0.03%) | 97(0.03%) | 0(0.00%) | 7(0.01%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | MGT_combined_ttc_rx_init | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_combined_ttc_rx_i | MGT_combined_ttc_rx_multi_gt | 9(0.01%) | 2(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | MGT_combined_ttc_rx_cpll_railing | 9(0.01%) | 2(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_MGT_combined_ttc_rx_i | MGT_combined_ttc_rx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | MGT_combined_ttc_rx_RX_STARTUP_FSM | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | MGT_combined_ttc_rx_RX_STARTUP_FSM | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 91(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_combined_ttc_rx_sync_block | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_combined_ttc_rx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_combined_ttc_rx_sync_block_1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_combined_ttc_rx_sync_block_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_combined_ttc_rx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_combined_ttc_rx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_combined_ttc_rx_sync_block_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | sume_RO_Rx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_ttc_HD12 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_ttc_HD12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD13 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD14 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD15 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD16 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD18 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pwer_on_rst | pwr_on_timer | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | readout_ctrl | rod_RO_Tx_exdes | 800(0.23%) | 726(0.21%) | 0(0.00%) | 74(0.04%) | 1394(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (readout_ctrl) | rod_RO_Tx_exdes | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_tx0_inst | ila_1 | 627(0.18%) | 560(0.16%) | 0(0.00%) | 67(0.04%) | 1038(0.15%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_tx0_inst) | ila_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_1_ila_v6_2_12_ila | 627(0.18%) | 560(0.16%) | 0(0.00%) | 67(0.04%) | 1038(0.15%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_1_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_1_ila_v6_2_12_ila_core | 626(0.18%) | 559(0.16%) | 0(0.00%) | 67(0.04%) | 1032(0.15%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_1_ila_v6_2_12_ila_core | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_1_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_1_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_1_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_1_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | u_ila_cap_ctrl | ila_1_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_1_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_1_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_1_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_1_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_1_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_1_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_1_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_1_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_1_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_1_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_1_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_1_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_1_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_27 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized1_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_1_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_1_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_1_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_1_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_1_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_1_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA__parameterized0 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_1_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_22 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA_nodelay_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_23 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA__parameterized0_23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized0_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice__parameterized1_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_1_ila_v6_2_12_ila_register | 494(0.14%) | 493(0.14%) | 0(0.00%) | 1(0.01%) | 819(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_1_ila_v6_2_12_ila_register | 245(0.07%) | 244(0.07%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_1_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_1_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_1_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_1_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_1_xsdbs_v1_0_2_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_1_xsdbs_v1_0_2_reg__parameterized29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_1_xsdbs_v1_0_2_reg__parameterized30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_1_xsdbs_v1_0_2_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_1_xsdbs_v1_0_2_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_1_xsdbs_v1_0_2_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized1_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_1_xsdbs_v1_0_2_reg__parameterized13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_1_xsdbs_v1_0_2_reg__parameterized14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_1_xsdbs_v1_0_2_reg__parameterized15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_1_xsdbs_v1_0_2_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized1_12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_1_xsdbs_v1_0_2_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_1_xsdbs_v1_0_2_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_1_xsdbs_v1_0_2_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_10 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_1_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_9 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_1_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl_8 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_1_xsdbs_v1_0_2_reg__parameterized41 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_1_xsdbs_v1_0_2_reg__parameterized43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_1_xsdbs_v1_0_2_reg__parameterized46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_1_xsdbs_v1_0_2_reg__parameterized46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_1_xsdbs_v1_0_2_reg__parameterized16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_1_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_1_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_1_xsdbs_v1_0_2_reg_stream__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_1_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_2_reg_stat | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_1_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_1_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_1_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_1_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_1_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_1_ila_v6_2_12_ila_trigger | 17(0.01%) | 2(0.01%) | 0(0.00%) | 15(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_1_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_1_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_1_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_1_ila_v6_2_12_ila_trig_match | 11(0.01%) | 1(0.01%) | 0(0.00%) | 10(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_1_ila_v6_2_12_ila_trig_match | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_1_ltlib_v1_0_0_match__parameterized0__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_1_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_1_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_1_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_1_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_1_ltlib_v1_0_0_generic_memrd | 26(0.01%) | 24(0.01%) | 0(0.00%) | 2(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_RO_Tx_support_i | rod_RO_Tx_support | 71(0.02%) | 64(0.02%) | 0(0.00%) | 7(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rod_RO_Tx_support_i) | rod_RO_Tx_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | rod_RO_Tx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_RO_Tx_init_i | rod_RO_Tx | 71(0.02%) | 64(0.02%) | 0(0.00%) | 7(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | rod_RO_Tx_init | 71(0.02%) | 64(0.02%) | 0(0.00%) | 7(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | rod_RO_Tx_TX_STARTUP_FSM | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | rod_RO_Tx_TX_STARTUP_FSM | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | rod_RO_Tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | rod_RO_Tx_sync_block_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | rod_RO_Tx_sync_block_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | rod_RO_Tx_sync_block_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | rod_RO_Tx_sync_block_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | rod_RO_Tx_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_RO_Tx_i | rod_RO_Tx_multi_gt | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | rod_RO_Tx_cpll_railing | 8(0.01%) | 1(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rod_RO_Tx_i | rod_RO_Tx_GT | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_0 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_0_vio_v3_0_22_vio | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_0_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_0_vio_v3_0_22_decoder | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_0_vio_v3_0_22_probe_in_one | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_0_vio_v3_0_22_probe_out_all | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_0_vio_v3_0_22_probe_out_all | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_0_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_0_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_hub | dbg_hub | 891(0.26%) | 867(0.25%) | 24(0.01%) | 0(0.00%) | 1187(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dbg_hub) | dbg_hub | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dbg_hub_xsdbm_v3_0_0_xsdbm | 891(0.26%) | 867(0.25%) | 24(0.01%) | 0(0.00%) | 1187(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BSCANID.u_xsdbm_id | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 891(0.26%) | 867(0.25%) | 24(0.01%) | 0(0.00%) | 1187(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (BSCANID.u_xsdbm_id) | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.UUT_MASTER | dbg_hub_xsdbm_v3_0_0_icon2xsdb | 716(0.21%) | 692(0.20%) | 24(0.01%) | 0(0.00%) | 1000(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_ICON_INTERFACE | dbg_hub_xsdbm_v3_0_0_if | 333(0.10%) | 309(0.09%) | 24(0.01%) | 0(0.00%) | 690(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_ICON_INTERFACE) | dbg_hub_xsdbm_v3_0_0_if | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD1 | dbg_hub_xsdbm_v3_0_0_ctl_reg | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD2 | dbg_hub_xsdbm_v3_0_0_stat_reg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD3 | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized0 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD4 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized0 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD5 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_RD | dbg_hub_xsdbm_v3_0_0_rdreg | 66(0.02%) | 54(0.02%) | 12(0.01%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_RD) | dbg_hub_xsdbm_v3_0_0_rdreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_FIFO | dbg_hub_xsdbm_v3_0_0_rdfifo | 64(0.02%) | 52(0.02%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_RD_FIFO) | dbg_hub_xsdbm_v3_0_0_rdfifo | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst) | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs_6 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs_6 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | dbg_hub_rd_fwft | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr_17 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as_13 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory__parameterized0 | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | dbg_hub_memory__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem_12 | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo_7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_WR | dbg_hub_xsdbm_v3_0_0_wrreg | 45(0.01%) | 33(0.01%) | 12(0.01%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_WR) | dbg_hub_xsdbm_v3_0_0_wrreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WR_FIFO | dbg_hub_xsdbm_v3_0_0_wrfifo | 43(0.01%) | 31(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_WR_FIFO) | dbg_hub_xsdbm_v3_0_0_wrfifo | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst | dbg_hub_fifo_generator_v13_1_4 | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst) | dbg_hub_fifo_generator_v13_1_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_CTL | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_STAT | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STATIC_STATUS | dbg_hub_xsdbm_v3_0_0_if_static_status | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_ADDRESS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_addr_ctl | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BURST_WD_LEN_CONTROLLER | dbg_hub_xsdbm_v3_0_0_burst_wdlen_ctl | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_bus_ctl | 159(0.05%) | 159(0.05%) | 0(0.00%) | 0(0.00%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_CONTROLLER) | dbg_hub_xsdbm_v3_0_0_bus_ctl | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 243(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_ABORT_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_REQ_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TIMER | dbg_hub_xsdbm_v3_0_0_bus_ctl_cnt | 141(0.04%) | 141(0.04%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_MSTR2SL_PORT_IFACE | dbg_hub_xsdbm_v3_0_0_bus_mstr2sl_if | 186(0.05%) | 186(0.05%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_MSTR2SL_PORT_IFACE) | dbg_hub_xsdbm_v3_0_0_bus_mstr2sl_if | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_DIN_BUS_MUX | dbg_hub_ltlib_v1_0_0_generic_mux | 177(0.05%) | 177(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.U_ICON | dbg_hub_xsdbm_v3_0_0_icon | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (CORE_XSDB.U_ICON) | dbg_hub_xsdbm_v3_0_0_icon | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD | dbg_hub_xsdbm_v3_0_0_cmd_decode | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STAT | dbg_hub_xsdbm_v3_0_0_stat | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SYNC | dbg_hub_xsdbm_v3_0_0_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_inst | dbg_hub_ltlib_v1_0_0_bscan | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_switch | dbg_hub_xsdbm_v3_0_0_bscan_switch | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 125(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_builder | packet_processor_p2 | 47847(13.81%) | 43503(12.56%) | 1968(1.13%) | 2376(1.36%) | 78172(11.28%) | 402(34.07%) | 4(0.17%) | 0(0.00%) | | (event_builder) | packet_processor_p2 | 188(0.05%) | 188(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CTTC_receiver | combined_ttc_no_mgt__xdcDup__1 | 1746(0.50%) | 1427(0.41%) | 0(0.00%) | 319(0.18%) | 3092(0.45%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (CTTC_receiver) | combined_ttc_no_mgt__xdcDup__1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_frame_check | sume_RO_Rx_GT_FRAME_CHECK__3 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 133(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_rx2_inst | ila_2_HD1304 | 1573(0.45%) | 1254(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_rx2_inst) | ila_2_HD1304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_2_ila_v6_2_12_ila_HD1305 | 1573(0.45%) | 1254(0.36%) | 0(0.00%) | 319(0.18%) | 2584(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_2_ila_v6_2_12_ila_HD1305 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_2_ila_v6_2_12_ila_core_HD1306 | 1572(0.45%) | 1253(0.36%) | 0(0.00%) | 319(0.18%) | 2578(0.37%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_2_ila_v6_2_12_ila_core_HD1306 | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 255(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_2_ila_v6_2_12_ila_trace_memory_HD1307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_2_blk_mem_gen_v8_4_5_HD1308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_synth_HD1309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(1.02%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[10].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized9_HD1314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized9_HD1315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[11].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized10_HD1316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized10_HD1317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD1320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD1322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD1323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD1324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD1325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4_HD1326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4_HD1327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5_HD1328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5_HD1329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized6_HD1330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized6_HD1331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[8].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized7_HD1332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized7_HD1333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[9].ram.r | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized8_HD1334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_2_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized8_HD1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD1336 | 81(0.02%) | 34(0.01%) | 0(0.00%) | 47(0.03%) | 137(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_2_ila_v6_2_12_ila_cap_ctrl_legacy_HD1336 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_2_ltlib_v1_0_0_cfglut6__parameterized0_HD1337 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_2_ltlib_v1_0_0_cfglut7_HD1338 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_2_ltlib_v1_0_0_cfglut7__1_HD1339 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_2_ila_v6_2_12_ila_cap_addrgen_HD1340 | 66(0.02%) | 29(0.01%) | 0(0.00%) | 37(0.02%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_2_ila_v6_2_12_ila_cap_addrgen_HD1340 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_2_ltlib_v1_0_0_cfglut6__1_HD1341 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD1342 | 33(0.01%) | 20(0.01%) | 0(0.00%) | 13(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_2_ila_v6_2_12_ila_cap_sample_counter_HD1342 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_2_ltlib_v1_0_0_cfglut4__1_HD1343 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_2_ltlib_v1_0_0_cfglut5__1_HD1344 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_2_ltlib_v1_0_0_cfglut6_HD1345 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_2_ltlib_v1_0_0_match_nodelay__1_HD1346 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD1347 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_81_HD1347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD1348 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_82_HD1348 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_83_HD1349 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_84_HD1350 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_2_ila_v6_2_12_ila_cap_window_counter_HD1351 | 30(0.01%) | 9(0.01%) | 0(0.00%) | 21(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_2_ila_v6_2_12_ila_cap_window_counter_HD1351 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_2_ltlib_v1_0_0_cfglut4_HD1352 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_2_ltlib_v1_0_0_cfglut5_HD1353 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_2_ltlib_v1_0_0_cfglut5__2_HD1354 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_2_ltlib_v1_0_0_match_nodelay_HD1355 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD1356 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_HD1356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD1357 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_HD1357 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1358 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1359 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_2_ltlib_v1_0_0_match_nodelay__2_HD1360 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD1361 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_nodelay_77_HD1361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD1362 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized2_78_HD1362 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized1_79_HD1363 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized2_80_HD1364 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_2_ila_v6_2_12_ila_register_HD1365 | 1004(0.29%) | 1003(0.29%) | 0(0.00%) | 1(0.01%) | 1439(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_2_ila_v6_2_12_ila_register_HD1365 | 328(0.09%) | 327(0.09%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s_HD1366 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1367 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1368 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1369 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized12_HD1370 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized13_HD1371 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized14_HD1372 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1373 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1374 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1375 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1376 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1377 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1378 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1379 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1380 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1381 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized15_HD1382 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_2_xsdbs_v1_0_2_xsdbs_HD1383 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_2_xsdbs_v1_0_2_reg__parameterized56_HD1384 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_73_HD1385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_2_xsdbs_v1_0_2_reg__parameterized57_HD1386 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_72_HD1387 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_2_xsdbs_v1_0_2_reg__parameterized58_HD1388 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_71_HD1389 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_2_xsdbs_v1_0_2_reg__parameterized59_HD1390 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_70_HD1391 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_2_xsdbs_v1_0_2_reg__parameterized60_HD1392 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_69_HD1393 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_2_xsdbs_v1_0_2_reg__parameterized61_HD1394 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_68_HD1395 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_2_xsdbs_v1_0_2_reg__parameterized41_HD1396 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_76_HD1397 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_2_xsdbs_v1_0_2_reg__parameterized42_HD1398 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1399 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_2_xsdbs_v1_0_2_reg__parameterized43_HD1400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_75_HD1401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_2_xsdbs_v1_0_2_reg__parameterized62_HD1402 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_67_HD1403 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_2_xsdbs_v1_0_2_reg__parameterized63_HD1404 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_66_HD1405 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_2_xsdbs_v1_0_2_reg__parameterized64_HD1406 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1407 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_2_xsdbs_v1_0_2_reg__parameterized65_HD1408 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_65_HD1409 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_2_xsdbs_v1_0_2_reg__parameterized66_HD1410 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_64_HD1411 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_2_xsdbs_v1_0_2_reg__parameterized67_HD1412 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_63_HD1413 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_2_xsdbs_v1_0_2_reg__parameterized69_HD1414 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_62_HD1415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_2_xsdbs_v1_0_2_reg__parameterized71_HD1416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_61_HD1417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD1418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_2_xsdbs_v1_0_2_reg__parameterized74_HD1418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_60_HD1419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_2_xsdbs_v1_0_2_reg__parameterized44_HD1420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_74_HD1421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_2_xsdbs_v1_0_2_reg_p2s__parameterized16_HD1422 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_2_xsdbs_v1_0_2_reg_stream_HD1423 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_2_xsdbs_v1_0_2_reg_ctl_HD1424 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD1425 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_2_xsdbs_v1_0_2_reg_stream__parameterized0_HD1425 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_2_xsdbs_v1_0_2_reg_stat_HD1426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_2_ila_v6_2_12_ila_reset_ctrl_HD1427 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_2_ila_v6_2_12_ila_reset_ctrl_HD1427 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection_HD1428 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__2_HD1429 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__3_HD1430 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer__1_HD1431 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_2_ltlib_v1_0_0_async_edge_xfer_HD1432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_2_ltlib_v1_0_0_rising_edge_detection__1_HD1433 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_2_ila_v6_2_12_ila_trigger_HD1434 | 268(0.08%) | 107(0.03%) | 0(0.00%) | 161(0.09%) | 475(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_2_ila_v6_2_12_ila_trigger_HD1434 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_2_ltlib_v1_0_0_match_HD1435 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_2_ltlib_v1_0_0_match_HD1435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA_HD1436 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA_HD1436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA_HD1437 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA_HD1437 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_58_HD1438 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_59_HD1439 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_2_ila_v6_2_12_ila_trig_match_HD1440 | 258(0.07%) | 106(0.03%) | 0(0.00%) | 152(0.09%) | 456(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_2_ila_v6_2_12_ila_trig_match_HD1440 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD1441 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__1_HD1441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD1442 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_52_HD1442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD1443 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_53_HD1443 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_54_HD1444 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_55_HD1445 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_56_HD1446 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_57_HD1447 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD1448 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__5_HD1448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD1449 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_11_HD1449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD1450 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_12_HD1450 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_13_HD1451 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_14_HD1452 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_15_HD1453 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_16_HD1454 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_2_ltlib_v1_0_0_match__parameterized0_HD1455 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0_HD1455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD1456 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_HD1456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD1457 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_HD1457 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_HD1458 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_8_HD1459 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_9_HD1460 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_10_HD1461 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD1462 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__4_HD1462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD1463 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_5_HD1463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD1464 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_6_HD1464 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD1465 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD1466 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__5_HD1466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD1467 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_2_HD1467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD1468 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_3_HD1468 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD1469 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_2_ltlib_v1_0_0_match__parameterized3_HD1470 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3_HD1470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD1471 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_HD1471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD1472 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_0_HD1472 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD1473 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_2_ltlib_v1_0_0_match__parameterized1_HD1474 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1_HD1474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD1475 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_HD1475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD1476 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_HD1476 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1477 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD1478 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__1_HD1478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD1479 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_49_HD1479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD1480 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_50_HD1480 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_51_HD1481 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD1482 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_2_ltlib_v1_0_0_match__parameterized1__2_HD1482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD1483 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized1_46_HD1483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD1484 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_47_HD1484 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD1485 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD1486 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__2_HD1486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD1487 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_40_HD1487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD1488 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_41_HD1488 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_42_HD1489 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_43_HD1490 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_44_HD1491 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_45_HD1492 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD1493 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__3_HD1493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD1494 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_34_HD1494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD1495 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_35_HD1495 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_36_HD1496 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_37_HD1497 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_38_HD1498 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_39_HD1499 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD1500 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_2_ltlib_v1_0_0_match__parameterized0__4_HD1500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD1501 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized0_28_HD1501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD1502 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized0_29_HD1502 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_30_HD1503 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_31_HD1504 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice_32_HD1505 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_33_HD1506 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_2_ltlib_v1_0_0_match__parameterized2_HD1507 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_2_ltlib_v1_0_0_match__parameterized2_HD1507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD1508 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized2_HD1508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD1509 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_26_HD1509 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_27_HD1510 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD1511 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__1_HD1511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD1512 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_23_HD1512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1513 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1513 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD1514 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD1515 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__2_HD1515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD1516 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_20_HD1516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1517 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1517 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD1518 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD1519 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_2_ltlib_v1_0_0_match__parameterized3__3_HD1519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD1520 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_2_ltlib_v1_0_0_allx_typeA__parameterized3_17_HD1520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD1521 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_2_ltlib_v1_0_0_all_typeA__parameterized1_18_HD1521 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_2_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD1522 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_2_ltlib_v1_0_0_generic_memrd_HD1523 | 102(0.03%) | 100(0.03%) | 0(0.00%) | 2(0.01%) | 238(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_regs | rx_registers__3 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_gt_inst | vio_ttc_HD19 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_gt_inst) | vio_ttc_HD19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD20 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD21 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD22 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD23 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD24 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD25 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | alt_cttc_crc | cttc_crc_test | 846(0.24%) | 739(0.21%) | 0(0.00%) | 107(0.06%) | 1321(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (alt_cttc_crc) | cttc_crc_test | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_check_ila | ila_CRC | 779(0.22%) | 672(0.19%) | 0(0.00%) | 107(0.06%) | 1312(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (crc_check_ila) | ila_CRC | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_CRC_ila_v6_2_12_ila | 779(0.22%) | 672(0.19%) | 0(0.00%) | 107(0.06%) | 1312(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_CRC_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_CRC_ila_v6_2_12_ila_core | 778(0.22%) | 671(0.19%) | 0(0.00%) | 107(0.06%) | 1306(0.19%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_CRC_ila_v6_2_12_ila_core | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_CRC_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_CRC_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_CRC_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_CRC_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_CRC_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_CRC_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_CRC_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_CRC_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_CRC_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_CRC_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_CRC_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_CRC_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_CRC_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_CRC_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_CRC_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_CRC_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_CRC_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_CRC_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_31 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_32 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized1_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized2_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_CRC_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_CRC_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_CRC_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_CRC_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_CRC_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_CRC_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_CRC_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_27 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA_nodelay_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_28 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized1_28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized1_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized2_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_CRC_ila_v6_2_12_ila_register | 569(0.16%) | 568(0.16%) | 0(0.00%) | 1(0.01%) | 920(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_CRC_ila_v6_2_12_ila_register | 263(0.08%) | 262(0.08%) | 0(0.00%) | 1(0.01%) | 159(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_CRC_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_CRC_xsdbs_v1_0_2_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_23 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_CRC_xsdbs_v1_0_2_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_22 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_CRC_xsdbs_v1_0_2_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_CRC_xsdbs_v1_0_2_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_20 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_CRC_xsdbs_v1_0_2_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_19 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_CRC_xsdbs_v1_0_2_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized1_18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_CRC_xsdbs_v1_0_2_reg__parameterized17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_CRC_xsdbs_v1_0_2_reg__parameterized18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_CRC_xsdbs_v1_0_2_reg__parameterized19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_CRC_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized1_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_CRC_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_CRC_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_CRC_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_CRC_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_CRC_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_CRC_xsdbs_v1_0_2_reg__parameterized45 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_CRC_xsdbs_v1_0_2_reg__parameterized47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_CRC_xsdbs_v1_0_2_reg__parameterized50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_CRC_xsdbs_v1_0_2_reg__parameterized50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_CRC_xsdbs_v1_0_2_reg__parameterized20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_CRC_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_CRC_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_CRC_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_CRC_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_CRC_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_CRC_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_CRC_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_CRC_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_CRC_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_CRC_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_CRC_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_CRC_ila_v6_2_12_ila_trigger | 56(0.02%) | 19(0.01%) | 0(0.00%) | 37(0.02%) | 87(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_CRC_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_CRC_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_CRC_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA_8 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_CRC_ila_v6_2_12_ila_trig_match | 50(0.01%) | 18(0.01%) | 0(0.00%) | 32(0.02%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_CRC_ila_v6_2_12_ila_trig_match | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized2__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_CRC_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_CRC_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_CRC_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_CRC_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_CRC_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_CRC_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_CRC_ltlib_v1_0_0_generic_memrd | 46(0.01%) | 44(0.01%) | 0(0.00%) | 2(0.01%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cttc_crc | osum_crc9d32__10 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bkpln_rst_pulse_stretcher | pulse_stretch__parameterized1 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_0 | bulk_processor__xdcDup__1 | 926(0.27%) | 926(0.27%) | 0(0.00%) | 0(0.00%) | 1410(0.20%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (bulk_0) | bulk_processor__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | bulk_controller_1428 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF__parameterized1_1481 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | bulk_data_fifo_HD3566 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | bulk_data_fifo_axis_data_fifo_v2_0_8_top_HD3567 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | bulk_data_fifo_xpm_fifo_axis_HD3568 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | bulk_data_fifo_xpm_fifo_axis_HD3568 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | bulk_data_fifo_xpm_cdc_sync_rst_HD3569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | bulk_data_fifo_xpm_fifo_base_HD3570 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | bulk_data_fifo_xpm_fifo_base_HD3570 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized1_HD3571 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | bulk_data_fifo_xpm_memory_base_HD3572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_HD3573 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_HD3574 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | bulk_data_fifo_xpm_fifo_reg_bit_HD3575 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_0_HD3576 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_1_HD3577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | bulk_data_fifo_xpm_counter_updn__parameterized0_HD3578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | bulk_data_fifo_xpm_fifo_rst_HD3579 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_1482 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | bulk_channel_mux_1429 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_regs | bulk_proc_regs_1430 | 594(0.17%) | 594(0.17%) | 0(0.00%) | 0(0.00%) | 1166(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (status_regs) | bulk_proc_regs_1430 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_counter | threshold_counter_1432 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_flag | threshold_counter__parameterized0_1433 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_counter | threshold_counter_1434 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_flag | threshold_counter__parameterized0_1435 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Bulk_proc_status_reg | ipbus_syncreg_v_1436 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.Bulk_proc_status_reg) | ipbus_syncreg_v_1436 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1480 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_control_reg | ipbus_reg_v_1437 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_reset_reg | ipbus_reg_v_1438 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Full_mode_control_reg | ipbus_reg_v_1439 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_busy_Count_reg | ipbus_syncreg_v_1440 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_busy_Count_reg) | ipbus_syncreg_v_1440 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1479 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_fifo_status_reg | ipbus_syncreg_v_1441 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_fifo_status_reg) | ipbus_syncreg_v_1441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1478 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_xoff_Count_reg | ipbus_syncreg_v_1442 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_xoff_Count_reg) | ipbus_syncreg_v_1442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1477 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_control_reg | ipbus_reg_v_1443 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_fifo_resets_reg | ipbus_reg_v_1444 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_thresholds_reg | ipbus_reg_v_1445 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_1446 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_1446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1476 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_watermark | watermark_1447 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.flx_bp_time_reg | ipbus_syncreg_v_1448 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.flx_bp_time_reg) | ipbus_syncreg_v_1448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1475 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_L1id_reg | ipbus_syncreg_v_1449 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fm_L1id_reg) | ipbus_syncreg_v_1449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1474 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_fifo_watermark | watermark_1450 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.full_mode_status_reg | ipbus_syncreg_v_1451 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.full_mode_status_reg) | ipbus_syncreg_v_1451 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1473 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_1452 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_1452 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1472 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_1453 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_1453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1471 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_watermark | watermark_1454 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_capture | pkt_capture_regs__parameterized1_1455 | 156(0.05%) | 156(0.05%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (packet_capture) | pkt_capture_regs__parameterized1_1455 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_1456 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_1457 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_1457 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1470 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_1458 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_1458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1469 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_1459 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_1459 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1468 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_1460 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_1460 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1467 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_1461 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_1461 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1466 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_1462 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_1462 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1465 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_1463 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_1463 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1464 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized1_1431 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_1 | bulk_processor__xdcDup__2 | 911(0.26%) | 911(0.26%) | 0(0.00%) | 0(0.00%) | 1410(0.20%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (bulk_1) | bulk_processor__xdcDup__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | bulk_controller_1373 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF__parameterized1_1426 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | bulk_data_fifo_HD3580 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | bulk_data_fifo_axis_data_fifo_v2_0_8_top_HD3581 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | bulk_data_fifo_xpm_fifo_axis_HD3582 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | bulk_data_fifo_xpm_fifo_axis_HD3582 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | bulk_data_fifo_xpm_cdc_sync_rst_HD3583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | bulk_data_fifo_xpm_fifo_base_HD3584 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | bulk_data_fifo_xpm_fifo_base_HD3584 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized1_HD3585 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | bulk_data_fifo_xpm_memory_base_HD3586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_HD3587 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_HD3588 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | bulk_data_fifo_xpm_fifo_reg_bit_HD3589 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_0_HD3590 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_1_HD3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | bulk_data_fifo_xpm_counter_updn__parameterized0_HD3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | bulk_data_fifo_xpm_fifo_rst_HD3593 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9__7 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9__7 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_1427 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | bulk_channel_mux_1374 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_regs | bulk_proc_regs_1375 | 574(0.17%) | 574(0.17%) | 0(0.00%) | 0(0.00%) | 1166(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (status_regs) | bulk_proc_regs_1375 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_counter | threshold_counter_1377 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_flag | threshold_counter__parameterized0_1378 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_counter | threshold_counter_1379 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_flag | threshold_counter__parameterized0_1380 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Bulk_proc_status_reg | ipbus_syncreg_v_1381 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.Bulk_proc_status_reg) | ipbus_syncreg_v_1381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1425 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_control_reg | ipbus_reg_v_1382 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_reset_reg | ipbus_reg_v_1383 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Full_mode_control_reg | ipbus_reg_v_1384 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_busy_Count_reg | ipbus_syncreg_v_1385 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_busy_Count_reg) | ipbus_syncreg_v_1385 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1424 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_fifo_status_reg | ipbus_syncreg_v_1386 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_fifo_status_reg) | ipbus_syncreg_v_1386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1423 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_xoff_Count_reg | ipbus_syncreg_v_1387 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_xoff_Count_reg) | ipbus_syncreg_v_1387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1422 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_control_reg | ipbus_reg_v_1388 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_fifo_resets_reg | ipbus_reg_v_1389 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_thresholds_reg | ipbus_reg_v_1390 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_1391 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_1391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1421 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_watermark | watermark_1392 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.flx_bp_time_reg | ipbus_syncreg_v_1393 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.flx_bp_time_reg) | ipbus_syncreg_v_1393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1420 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_L1id_reg | ipbus_syncreg_v_1394 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fm_L1id_reg) | ipbus_syncreg_v_1394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1419 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_fifo_watermark | watermark_1395 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.full_mode_status_reg | ipbus_syncreg_v_1396 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.full_mode_status_reg) | ipbus_syncreg_v_1396 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1418 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_1397 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_1397 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1417 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_1398 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_1398 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1416 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_watermark | watermark_1399 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_capture | pkt_capture_regs__parameterized1_1400 | 162(0.05%) | 162(0.05%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (packet_capture) | pkt_capture_regs__parameterized1_1400 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_1401 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_1402 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_1402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1415 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_1403 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_1403 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1414 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_1404 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_1404 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1413 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_1405 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_1405 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1412 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_1406 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_1406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1411 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_1407 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_1407 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1410 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_1408 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_1408 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1409 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized1_1376 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_2 | bulk_processor | 943(0.27%) | 943(0.27%) | 0(0.00%) | 0(0.00%) | 1410(0.20%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (bulk_2) | bulk_processor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | bulk_controller | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF__parameterized1 | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | bulk_data_fifo | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | bulk_data_fifo_axis_data_fifo_v2_0_8_top | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | bulk_data_fifo_xpm_fifo_axis | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | bulk_data_fifo_xpm_fifo_axis | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | bulk_data_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | bulk_data_fifo_xpm_fifo_base | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | bulk_data_fifo_xpm_fifo_base | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | bulk_data_fifo_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | bulk_data_fifo_xpm_fifo_reg_bit | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | bulk_data_fifo_xpm_counter_updn__parameterized2_0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | bulk_data_fifo_xpm_counter_updn__parameterized3_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | bulk_data_fifo_xpm_counter_updn__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | bulk_data_fifo_xpm_fifo_rst | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9__6 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9__6 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_1372 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | bulk_channel_mux | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_regs | bulk_proc_regs | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1166(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (status_regs) | bulk_proc_regs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_counter | threshold_counter_1324 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_busy_flag | threshold_counter__parameterized0_1325 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_counter | threshold_counter_1326 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_stage_xoff_flag | threshold_counter__parameterized0_1327 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Bulk_proc_status_reg | ipbus_syncreg_v_1328 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.Bulk_proc_status_reg) | ipbus_syncreg_v_1328 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1371 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_control_reg | ipbus_reg_v_1329 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Event_fifo_reset_reg | ipbus_reg_v_1330 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.Full_mode_control_reg | ipbus_reg_v_1331 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_busy_Count_reg | ipbus_syncreg_v_1332 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_busy_Count_reg) | ipbus_syncreg_v_1332 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1370 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_fifo_status_reg | ipbus_syncreg_v_1333 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_fifo_status_reg) | ipbus_syncreg_v_1333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1369 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_stage_xoff_Count_reg | ipbus_syncreg_v_1334 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.bulk_stage_xoff_Count_reg) | ipbus_syncreg_v_1334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1368 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_control_reg | ipbus_reg_v_1335 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_fifo_resets_reg | ipbus_reg_v_1336 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.bulk_staging_thresholds_reg | ipbus_reg_v_1337 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_1338 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_1338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1367 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.event_fifo_watermark | watermark_1339 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.flx_bp_time_reg | ipbus_syncreg_v_1340 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.flx_bp_time_reg) | ipbus_syncreg_v_1340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1366 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_L1id_reg | ipbus_syncreg_v_1341 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fm_L1id_reg) | ipbus_syncreg_v_1341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1365 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fm_fifo_watermark | watermark_1342 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.full_mode_status_reg | ipbus_syncreg_v_1343 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.full_mode_status_reg) | ipbus_syncreg_v_1343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1364 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_1344 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_1344 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1363 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_1345 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_1345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1362 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_regs.stage_fifo_watermark | watermark_1346 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_capture | pkt_capture_regs__parameterized1 | 188(0.05%) | 188(0.05%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (packet_capture) | pkt_capture_regs__parameterized1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_1347 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_1348 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_1348 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1361 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_1349 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_1349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1360 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_1350 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_1350 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1359 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_1351 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_1351 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1358 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_1352 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_1352 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1357 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_1353 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_1353 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1356 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_1354 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_1354 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1355 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized1_1323 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_layer | input_fifos_p2 | 21438(6.19%) | 21294(6.15%) | 0(0.00%) | 144(0.08%) | 43423(6.27%) | 324(27.46%) | 0(0.00%) | 0(0.00%) | | ch0 | channel_fifo_p2 | 1637(0.47%) | 1625(0.47%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch0) | channel_fifo_p2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_1245 | 828(0.24%) | 828(0.24%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_1245 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1250 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1251 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1252 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1322 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1253 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1321 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1254 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1320 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1255 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1256 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1257 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1319 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1258 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1318 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1259 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1317 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1260 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1261 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1316 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_1262 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_1262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1315 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_1263 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_1263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1314 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_1264 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_1264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1313 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1265 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1312 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1266 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1267 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1311 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1268 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1269 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1310 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1270 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1309 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1271 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1308 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1272 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1307 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1273 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1274 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1306 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1275 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1276 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1305 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1277 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1278 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1304 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1279 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1280 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1303 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1281 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1282 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1282 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1302 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1283 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1284 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1285 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1299 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1300 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1301 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1286 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1298 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1287 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1288 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1289 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1290 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_1291 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_1292 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_1293 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1294 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1295 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1296 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2 | 114(0.03%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1248 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1249 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__3 | 213(0.06%) | 209(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__3 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3662 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3663 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3664 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3665 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3666 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3667 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3667 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3668 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3669 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3670 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3671 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3673 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3674 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3676 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3677 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3679 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3679 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3682 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3683 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3684 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3685 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3686 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3687 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3688 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3688 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3689 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3690 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3690 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD4861 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD4862 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4863 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4863 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD4864 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD4865 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD4866 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD4867 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD4868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD4868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD4869 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD4870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD4871 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD4872 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD4873 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD4873 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD4874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD4875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD4876 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD4877 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD4878 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD4878 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD4879 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD4880 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD4881 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD4882 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD4883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD4884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD4885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD4886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD4887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD4888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD4889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD4890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD4891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD4892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD4893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD4894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD4895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD4896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4897 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4897 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD4898 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4899 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4899 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD4900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD4901 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__2 | 225(0.06%) | 221(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__2 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3629 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3630 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3631 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3632 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3633 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3634 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3634 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3635 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3636 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3637 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3638 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3643 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3644 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3646 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3646 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3649 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3650 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3651 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3652 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3653 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3654 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3655 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3655 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3656 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3657 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3657 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD4819 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD4820 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4821 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4821 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD4822 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD4823 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD4824 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD4825 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD4826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD4826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD4827 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD4828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD4829 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD4830 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD4831 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD4831 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD4832 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD4834 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD4835 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD4836 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD4836 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD4837 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD4838 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD4839 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD4840 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD4844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD4846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD4847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD4849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD4851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD4852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4855 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4855 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD4856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4857 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4857 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD4858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD4859 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__1 | 250(0.07%) | 246(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__1 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1246 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1247 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1 | channel_fifo_p2__parameterized1 | 1617(0.47%) | 1605(0.46%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch1) | channel_fifo_p2__parameterized1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_1167 | 821(0.24%) | 821(0.24%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_1167 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1172 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1173 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1174 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1244 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1175 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1243 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1176 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1242 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1177 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1178 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1179 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1241 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1180 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1240 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1181 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1239 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1182 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1183 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1238 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_1184 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_1184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1237 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_1185 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_1185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1236 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_1186 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_1186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1235 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1187 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1234 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1188 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1189 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1233 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1190 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1191 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1232 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1192 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1231 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1193 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1230 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1194 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1229 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1195 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1196 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1228 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1197 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1198 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1227 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1199 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1200 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1226 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1201 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1202 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1225 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1203 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1204 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1204 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1224 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1205 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1206 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1207 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1221 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1222 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1223 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1208 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1220 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1209 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1210 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1211 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1212 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_1213 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_1214 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_1215 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1216 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1217 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1218 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1219 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized1 | 114(0.03%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1170 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1171 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__6 | 241(0.07%) | 237(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__6 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3761 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3762 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3763 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3764 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3765 | 89(0.03%) | 86(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3766 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3766 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3767 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3768 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3769 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3770 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3772 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3773 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3775 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3776 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3778 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3778 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3781 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3782 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3783 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3784 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3785 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3786 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3787 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3787 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3788 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3789 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3789 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD4987 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD4988 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4989 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4989 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD4990 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD4991 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD4992 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD4993 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD4994 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD4994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD4995 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD4996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD4997 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD4998 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD4999 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD4999 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5000 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5002 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5003 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5004 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5004 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5005 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5006 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5007 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5008 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5023 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5023 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5024 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5025 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5025 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5027 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__5 | 206(0.06%) | 202(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__5 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3728 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3729 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3730 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3731 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3732 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3733 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3733 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3734 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3735 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3736 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3737 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3742 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3743 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3745 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3745 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3748 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3749 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3750 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3751 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3752 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3753 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3754 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3754 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3755 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3756 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3756 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD4945 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD4946 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4947 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4947 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD4948 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD4949 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD4950 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD4951 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD4952 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD4952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD4953 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD4954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD4955 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD4956 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD4957 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD4957 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD4958 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD4959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD4960 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD4961 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD4962 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD4962 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD4963 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD4964 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD4965 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD4966 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD4967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD4968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD4969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD4970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD4971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD4972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD4973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD4974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD4975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD4976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD4977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD4978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD4979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD4980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4981 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4981 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD4982 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4983 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4983 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD4984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD4985 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__4 | 228(0.07%) | 224(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__4 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3695 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3696 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3697 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3698 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3699 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3700 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3700 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3701 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3702 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3703 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3704 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3706 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3709 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3710 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3715 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3716 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3717 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3718 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3719 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3720 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3721 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3721 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3722 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3723 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3723 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD4903 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD4904 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4905 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD4905 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD4906 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD4907 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD4908 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD4909 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD4910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD4910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD4911 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD4912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD4913 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD4914 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD4915 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD4915 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD4916 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD4917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD4918 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD4919 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD4920 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD4920 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD4921 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD4922 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD4923 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD4924 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD4925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD4926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD4927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD4928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD4929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD4930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD4931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD4932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD4933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD4934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD4935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD4936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD4937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD4938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4939 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD4939 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD4940 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4941 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD4941 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD4943 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1168 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1169 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch10 | channel_fifo_p2__parameterized19 | 1633(0.47%) | 1621(0.47%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch10) | channel_fifo_p2__parameterized19 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_1089 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_1089 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1094 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1095 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1096 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1166 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1097 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1165 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1098 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1164 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1099 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1100 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1101 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1163 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1102 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1162 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1103 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1161 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1104 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1105 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1160 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_1106 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_1106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1159 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_1107 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_1107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1158 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_1108 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_1108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1157 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1109 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1156 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1110 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1111 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1155 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1112 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1113 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1154 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1114 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1153 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1115 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1152 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1116 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1151 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1117 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1118 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1150 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1119 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1120 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1149 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1121 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1122 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1148 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1123 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1124 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1147 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1125 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1126 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1146 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1127 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1128 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1129 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1143 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1144 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1145 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1130 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1142 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1131 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1132 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1133 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1134 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_1135 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_1136 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_1137 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1138 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1139 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1140 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1141 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized19 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized19 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1092 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1093 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__33 | 240(0.07%) | 236(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__33 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4256 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4257 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4258 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4259 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4260 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4261 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4261 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4262 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4263 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4264 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4265 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4267 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4268 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4270 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4271 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4273 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4273 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4275 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4276 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4277 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4278 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4279 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4280 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4281 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4282 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4282 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4283 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4284 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4284 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5617 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5618 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5619 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5619 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5620 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5621 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5622 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5623 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5624 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5625 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5627 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5628 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5629 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5629 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5633 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5634 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5634 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5635 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5636 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5637 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5638 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5653 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5653 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5655 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5655 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5657 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__32 | 211(0.06%) | 207(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__32 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4223 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4224 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4225 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4226 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4227 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4228 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4228 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4229 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4230 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4231 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4232 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4237 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4238 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4240 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4240 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4243 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4244 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4245 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4246 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4247 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4248 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4249 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4249 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4250 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4251 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4251 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5575 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5576 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5577 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5577 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5578 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5579 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5580 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5581 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5582 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5583 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5585 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5586 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5587 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5587 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5588 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5590 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5591 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5592 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5592 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5593 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5594 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5595 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5596 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5611 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5611 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5612 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5613 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5613 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__31 | 233(0.07%) | 229(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__31 | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4190 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4191 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4192 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4193 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4194 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4195 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4195 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4196 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4197 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4198 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4199 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4201 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4202 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4204 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4205 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4207 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4207 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4210 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4211 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4212 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4213 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4214 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4215 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4216 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4216 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4217 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4218 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4218 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5533 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5534 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5535 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5535 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5536 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5537 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5538 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5539 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5540 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5541 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5543 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5544 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5545 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5545 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5548 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5549 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5550 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5550 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5551 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5552 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5553 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5554 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5569 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5569 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5571 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5571 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5573 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1090 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1091 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch11 | channel_fifo_p2__parameterized21 | 1665(0.48%) | 1653(0.48%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch11) | channel_fifo_p2__parameterized21 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_1011 | 871(0.25%) | 871(0.25%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_1011 | 203(0.06%) | 203(0.06%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_1016 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_1017 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_1018 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_1018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1088 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_1019 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_1019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1087 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_1020 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_1020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1086 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_1021 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_1022 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_1023 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_1023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1085 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_1024 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1084 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_1025 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_1025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_1026 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_1027 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_1027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1082 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_1028 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_1028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1081 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_1029 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_1029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1080 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_1030 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_1030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1079 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_1031 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_1031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1078 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_1032 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_1033 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_1033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1077 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_1034 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_1035 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_1035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1076 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_1036 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_1036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1075 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_1037 | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_1037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1074 | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_1038 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_1038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1073 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_1039 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_1040 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_1040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1072 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_1041 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_1042 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_1042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1071 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_1043 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_1044 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_1044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1070 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_1045 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_1046 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_1046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1069 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_1047 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_1048 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_1048 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1068 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_1049 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_1050 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_1051 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_1065 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_1066 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_1067 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_1052 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_1052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1064 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_1053 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_1054 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_1055 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_1056 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_1057 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_1058 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_1059 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_1060 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_1061 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_1062 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_1063 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized21 | 114(0.03%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized21 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_1014 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_1015 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k | 224(0.06%) | 220(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4289 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4290 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4291 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4292 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4293 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4294 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4294 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4295 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4296 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4297 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4298 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4300 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4301 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4303 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4304 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4306 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4306 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4308 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4309 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4310 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4311 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4312 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4313 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4314 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4315 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4315 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4317 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4317 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5659 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5660 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5661 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5661 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5662 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5663 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5664 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5665 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5667 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5669 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5670 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5671 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5671 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5672 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5674 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5675 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5676 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5676 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5677 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5678 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5679 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5680 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5695 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5695 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5697 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5697 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5699 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__35 | 212(0.06%) | 208(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__35 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4355 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4356 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4357 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4358 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4359 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4360 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4360 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4361 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4362 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4363 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4364 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4366 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4369 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4370 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4372 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4372 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4374 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4375 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4376 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4377 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4378 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4379 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4380 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4381 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4381 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4382 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4383 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4383 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5743 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5744 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5745 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5745 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5746 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5747 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5748 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5749 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5750 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5753 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5754 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5755 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5755 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5756 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5758 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5759 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5760 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5760 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5761 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5762 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5763 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5764 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5779 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5779 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5781 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5781 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5783 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__34 | 237(0.07%) | 233(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__34 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4322 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4323 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4324 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4325 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4326 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4327 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4327 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4328 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4329 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4330 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4331 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4333 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4336 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4337 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4339 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4339 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4341 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4342 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4343 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4344 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4345 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4346 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4347 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4348 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4348 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4350 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4350 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5701 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5702 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5703 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5703 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5704 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5705 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5706 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5707 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5708 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5709 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5711 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5712 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5713 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5713 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5716 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5717 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5718 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5718 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5719 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5720 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5721 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5722 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5737 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5737 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5739 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5739 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5741 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_1012 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_1013 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2 | channel_fifo_p2__parameterized3 | 1623(0.47%) | 1611(0.47%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch2) | channel_fifo_p2__parameterized3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_933 | 829(0.24%) | 829(0.24%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_933 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_938 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_939 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_940 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1010 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_941 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1009 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_942 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1008 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_943 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_944 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_945 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1007 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_946 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1006 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_947 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1005 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_948 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_949 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1004 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_950 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1003 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_951 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1002 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_952 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1001 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_953 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1000 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_954 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_955 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_999 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_956 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_957 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_998 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_958 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_997 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_959 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_996 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_960 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_995 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_961 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_962 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_994 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_963 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_964 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_993 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_965 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_966 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_992 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_967 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_968 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_991 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_969 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_970 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_970 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_990 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_971 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_972 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_973 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_987 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_988 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_989 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_974 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_986 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_975 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_976 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_977 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_978 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_979 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_980 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_981 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_982 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_983 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_984 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_985 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized3 | 114(0.03%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized3 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_936 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_937 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__9 | 242(0.07%) | 238(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__9 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4454 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4455 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4456 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4457 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4458 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4459 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4459 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4460 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4461 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4462 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4463 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4465 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4466 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4468 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4469 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4471 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4471 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4473 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4474 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4475 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4476 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4477 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4478 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4479 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4480 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4480 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4481 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4482 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4482 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5869 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5870 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5871 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5871 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5872 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5873 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5874 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5875 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5876 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5879 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5880 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5881 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5881 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5882 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5884 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5885 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5886 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5886 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5887 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5888 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5889 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5890 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5905 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5905 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5907 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5907 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5909 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__8 | 204(0.06%) | 200(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__8 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4421 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4422 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4423 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4424 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4425 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4426 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4426 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4427 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4428 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4429 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4430 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4433 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4435 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4436 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4438 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4438 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4440 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4441 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4442 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4443 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4444 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4445 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4446 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4447 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4447 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4448 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4449 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4449 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5827 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5828 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5829 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5829 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5830 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5831 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5832 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5833 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5834 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5835 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5837 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5838 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5839 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5839 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5840 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5842 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5843 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5844 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5844 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5845 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5846 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5847 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5848 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5863 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5863 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5864 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5865 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5865 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5867 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__7 | 227(0.07%) | 223(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__7 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4388 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4389 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4390 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4391 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4392 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4393 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4393 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4394 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4395 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4396 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4397 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4399 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4400 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4402 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4403 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4405 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4405 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4407 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4408 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4409 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4410 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4411 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4412 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4413 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4414 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4414 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4416 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4416 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5785 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5786 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5787 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5787 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5788 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5789 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5790 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5791 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5792 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5795 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5796 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5797 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5797 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5801 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5802 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5802 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5803 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5804 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5805 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5806 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5821 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5821 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5822 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5823 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5823 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5825 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_934 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_935 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3 | channel_fifo_p2__parameterized5 | 1632(0.47%) | 1620(0.47%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch3) | channel_fifo_p2__parameterized5 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_855 | 834(0.24%) | 834(0.24%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_855 | 154(0.04%) | 154(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_860 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_861 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_862 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_932 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_863 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_931 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_864 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_930 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_865 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_866 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_867 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_929 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_868 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_928 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_869 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_927 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_870 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_871 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_926 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_872 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_925 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_873 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_924 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_874 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_923 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_875 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_922 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_876 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_877 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_921 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_878 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_879 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_920 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_880 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_919 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_881 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_918 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_882 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_917 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_883 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_884 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_916 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_885 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_886 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_915 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_887 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_888 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_914 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_889 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_890 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_913 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_891 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_892 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_912 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_893 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_894 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_895 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_909 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_910 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_911 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_896 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_908 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_897 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_898 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_899 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_900 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_901 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_902 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_903 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_904 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_905 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_906 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_907 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized5 | 115(0.03%) | 115(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized5 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_858 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_859 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__12 | 223(0.06%) | 219(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__12 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4553 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4554 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4555 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4556 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4557 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4558 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4558 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4559 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4560 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4561 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4562 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4564 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4565 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4567 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4568 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4570 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4570 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4572 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4573 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4574 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4575 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4576 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4577 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4578 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4579 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4579 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4580 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4581 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4581 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5995 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5996 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5997 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5997 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5998 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5999 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6000 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6001 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6002 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6003 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6005 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6006 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6007 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6007 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6008 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6010 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6011 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6012 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6012 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6013 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6014 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6015 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6016 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6031 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6031 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6032 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6033 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6033 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6035 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__11 | 213(0.06%) | 209(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__11 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4520 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4521 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4522 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4523 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4524 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4525 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4525 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4526 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4527 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4528 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4529 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4531 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4534 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4535 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4537 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4537 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4539 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4540 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4541 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4542 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4543 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4544 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4545 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4546 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4546 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4548 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4548 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5953 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5954 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5955 | 96(0.03%) | 95(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5955 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5956 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5957 | 91(0.03%) | 90(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5958 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5959 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5960 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5961 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5963 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5964 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5965 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5965 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5966 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5968 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5969 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5970 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5970 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5971 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5972 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5973 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5974 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5989 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5989 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5990 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5991 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5991 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5993 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__10 | 240(0.07%) | 236(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__10 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4487 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4488 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4489 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4490 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4491 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4492 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4492 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4493 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4494 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4495 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4496 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4498 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4501 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4502 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4504 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4504 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4507 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4508 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4509 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4510 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4511 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4512 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4513 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4513 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4514 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4515 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4515 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5911 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5912 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5913 | 97(0.03%) | 96(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5913 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5914 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5915 | 92(0.03%) | 91(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5916 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5917 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5918 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5919 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5921 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5922 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5923 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5923 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5926 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5927 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5928 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5928 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5929 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5930 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5931 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5932 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5947 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5947 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5948 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5949 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5949 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5951 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_856 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_857 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch4 | channel_fifo_p2__parameterized7 | 1611(0.47%) | 1599(0.46%) | 0(0.00%) | 12(0.01%) | 3501(0.51%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch4) | channel_fifo_p2__parameterized7 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_776 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 1624(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_776 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_781 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_782 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_783 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_854 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_784 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_853 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_785 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_852 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_786 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_787 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_788 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_851 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_789 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_850 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_790 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_849 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_791 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_792 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_848 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_793 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_847 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_794 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_846 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_795 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_845 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_796 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_844 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_797 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_798 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_843 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_799 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_800 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_842 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_801 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_841 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_802 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_840 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_803 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_839 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_804 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_805 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_838 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_806 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_807 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_837 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_808 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_809 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_836 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_810 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_811 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_835 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_812 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_813 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_813 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_834 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_814 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_815 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_816 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_831 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_832 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_833 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_817 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_830 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_818 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_819 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_820 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_821 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_822 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_823 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_824 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_825 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_826 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_827 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_828 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized7 | 113(0.03%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized7 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_779 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_780 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__15 | 212(0.06%) | 208(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__15 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4652 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4653 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4654 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4655 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4656 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4657 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4657 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4658 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4659 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4660 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4661 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4664 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4666 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4667 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4669 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4669 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4672 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4673 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4674 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4675 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4676 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4677 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4678 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4678 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4680 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4680 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6121 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6122 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6123 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6123 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6124 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6125 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6126 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6127 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6131 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6132 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6133 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6133 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6134 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6137 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6138 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6138 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6139 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6140 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6141 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6142 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6157 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6157 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6159 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6159 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6161 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__14 | 215(0.06%) | 211(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__14 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4619 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4620 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4621 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4622 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4623 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4624 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4624 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4625 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4626 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4627 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4628 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4631 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4633 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4634 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4636 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4636 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4638 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4639 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4640 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4641 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4642 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4643 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4644 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4645 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4645 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4647 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4647 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6079 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6080 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6081 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6081 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6082 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6083 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6084 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6085 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6086 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6089 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6090 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6091 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6091 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6092 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6095 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6096 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6096 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6097 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6098 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6099 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6100 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6115 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6115 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6117 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6117 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6119 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__13 | 238(0.07%) | 234(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__13 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4586 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4587 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4588 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4589 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4590 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4591 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4591 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4592 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4593 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4594 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4595 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4597 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4600 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4601 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4603 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4603 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4606 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4607 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4608 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4609 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4610 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4611 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4612 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4612 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4613 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4614 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4614 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6037 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6038 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6039 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6039 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6040 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6041 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6042 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6043 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6044 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6045 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6047 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6048 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6049 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6049 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6050 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6053 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6054 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6054 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6055 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6056 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6057 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6058 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6073 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6073 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6075 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6075 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6077 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_777 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_778 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch5 | channel_fifo_p2__parameterized9 | 1626(0.47%) | 1614(0.47%) | 0(0.00%) | 12(0.01%) | 3501(0.51%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch5) | channel_fifo_p2__parameterized9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_697 | 837(0.24%) | 837(0.24%) | 0(0.00%) | 0(0.00%) | 1624(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_697 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_702 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_703 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_704 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_775 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_705 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_774 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_706 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_773 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_707 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_708 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_709 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_772 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_710 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_771 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_711 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_770 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_712 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_713 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_769 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_714 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_768 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_715 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_767 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_716 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_766 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_717 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_765 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_718 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_719 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_764 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_720 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_721 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_763 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_722 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_762 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_723 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_761 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_724 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_760 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_725 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_726 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_759 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_727 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_728 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_758 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_729 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_730 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_757 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_731 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_732 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_756 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_733 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_734 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_755 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_735 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_736 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_737 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_752 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_753 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_754 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_738 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_751 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_739 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_740 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_741 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_742 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_743 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_744 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_745 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_746 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_747 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_748 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_749 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_750 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized9 | 114(0.03%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized9 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_700 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_701 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__18 | 239(0.07%) | 235(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__18 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4751 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4752 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4753 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4754 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4755 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4756 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4756 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4757 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4758 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4759 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4760 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4762 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4765 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4766 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4768 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4768 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4771 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4772 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4773 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4774 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4775 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4776 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4777 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4777 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4779 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4779 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6247 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6248 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6249 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6249 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6250 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6251 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6252 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6253 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6257 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6258 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6259 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6259 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6260 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6263 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6264 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6264 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6265 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6266 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6267 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6268 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6283 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6283 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6285 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6285 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6287 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__17 | 202(0.06%) | 198(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__17 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4718 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4719 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4720 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4721 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4722 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4723 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4723 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4724 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4725 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4726 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4727 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4730 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4732 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4733 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4735 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4735 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4737 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4738 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4739 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4740 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4741 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4742 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4743 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4744 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4744 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4746 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4746 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6205 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6206 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6207 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6207 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6208 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6209 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6210 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6211 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6213 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6215 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6216 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6217 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6217 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6218 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6220 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6221 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6222 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6222 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6223 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6224 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6225 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6226 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6241 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6241 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6243 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6243 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6245 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__16 | 227(0.07%) | 223(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__16 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4685 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4686 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4687 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4688 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4689 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4690 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4690 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4691 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4692 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4693 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4694 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4697 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4699 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4700 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4702 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4702 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4705 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4706 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4707 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4708 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4709 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4710 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4711 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4711 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4713 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4713 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD6163 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD6164 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6165 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD6165 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD6166 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD6167 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD6168 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD6169 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD6170 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD6170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD6171 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD6172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD6173 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD6174 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD6175 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD6175 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD6176 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD6177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD6178 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD6179 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD6180 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD6180 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD6181 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD6182 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD6183 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD6184 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD6185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD6186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD6187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD6188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD6189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD6190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD6191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD6192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD6193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD6194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD6195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD6196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD6197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD6198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6199 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD6199 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD6200 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6201 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD6201 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD6202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD6203 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_698 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_699 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch6 | channel_fifo_p2__parameterized11 | 1647(0.48%) | 1635(0.47%) | 0(0.00%) | 12(0.01%) | 3501(0.51%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch6) | channel_fifo_p2__parameterized11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_618 | 842(0.24%) | 842(0.24%) | 0(0.00%) | 0(0.00%) | 1624(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_618 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_623 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_624 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_625 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_696 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_626 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_695 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_627 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_694 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_628 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_629 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_630 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_693 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_631 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_692 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_632 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_691 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_633 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_634 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_690 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_635 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_689 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_636 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_688 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_637 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_687 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_638 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_686 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_639 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_640 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_685 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_641 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_642 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_684 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_643 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_683 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_644 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_682 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_645 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_681 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_646 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_647 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_680 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_648 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_649 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_679 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_650 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_651 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_678 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_652 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_653 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_677 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_654 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_655 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_655 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_676 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_656 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_657 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_658 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_673 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_674 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_675 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_659 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_672 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_660 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_661 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | odd_word_counter | error_counter__parameterized0_662 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_663 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_664 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_665 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_666 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_667 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_668 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_669 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_670 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized11 | 115(0.03%) | 115(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized11 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_621 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_622 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__21 | 239(0.07%) | 235(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__21 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3860 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3861 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3862 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3863 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3864 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3865 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3865 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3866 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3867 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3868 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3869 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3871 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3872 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3874 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3875 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3877 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3877 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3879 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3880 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3881 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3882 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3883 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3884 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3885 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3886 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3886 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3887 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3888 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3888 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5113 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5114 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5115 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5115 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5116 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5117 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5118 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5119 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5120 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5121 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5123 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5124 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5125 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5125 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5129 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5130 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5130 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5131 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5132 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5133 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5134 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5149 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5149 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5151 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5151 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5153 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__20 | 210(0.06%) | 206(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__20 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3827 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3828 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3829 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3830 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3831 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3832 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3832 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3833 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3834 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3835 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3836 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3839 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3841 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3842 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3844 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3844 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3846 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3847 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3848 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3849 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3850 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3851 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3852 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3853 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3853 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3854 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3855 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3855 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5071 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5072 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5073 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5073 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5074 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5075 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5076 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5077 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5078 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5079 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5081 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5082 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5083 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5084 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5086 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5087 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5088 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5088 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5089 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5090 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5091 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5092 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5107 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5107 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5108 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5109 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5109 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5111 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__19 | 234(0.07%) | 230(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__19 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3794 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3795 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3796 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3797 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3798 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3799 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3799 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3800 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3801 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3802 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3803 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3805 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3806 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3808 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3809 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3811 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3811 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3813 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3814 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3815 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3816 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3817 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3818 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3819 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3820 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3820 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3821 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3822 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3822 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5029 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5030 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5031 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5031 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5032 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5033 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5034 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5035 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5037 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5039 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5040 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5041 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5041 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5044 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5045 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5046 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5046 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5047 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5048 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5049 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5050 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5065 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5065 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5066 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5067 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5067 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5069 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_619 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_620 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch7 | channel_fifo_p2__parameterized13 | 1595(0.46%) | 1583(0.46%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch7) | channel_fifo_p2__parameterized13 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_540 | 823(0.24%) | 823(0.24%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_540 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_545 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_546 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_547 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_617 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_548 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_616 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_549 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_615 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_550 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_551 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_552 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_614 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_553 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_613 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_554 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_612 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_555 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_556 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_611 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_557 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_610 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_558 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_609 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_559 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_608 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_560 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_607 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_561 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_562 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_606 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_563 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_564 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_605 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_565 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_604 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_566 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_603 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_567 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_602 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_568 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_569 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_601 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_570 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_571 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_600 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_572 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_573 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_599 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_574 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_575 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_598 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_576 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_577 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_577 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_597 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_578 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_579 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_580 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_594 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_595 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_596 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_581 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_593 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_582 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_583 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_584 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_585 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_586 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_587 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_588 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_589 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_590 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_591 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized13 | 115(0.03%) | 115(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized13 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_543 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_544 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__24 | 225(0.06%) | 221(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__24 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3959 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3960 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3961 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3962 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3963 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3964 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3964 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3965 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3966 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3967 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3968 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3970 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3971 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3973 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3974 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3976 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3976 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3978 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3979 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3980 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3981 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3982 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3983 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3984 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3985 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3985 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3986 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3987 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3987 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5239 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5240 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5241 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5241 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5242 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5243 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5244 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5245 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5249 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5250 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5251 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5251 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5252 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5255 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5256 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5256 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5257 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5258 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5259 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5260 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5275 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5275 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5276 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5277 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5277 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5279 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__23 | 202(0.06%) | 198(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__23 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3926 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3927 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3928 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3929 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3930 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3931 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3931 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3932 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3933 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3934 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3935 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3937 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3938 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3940 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3941 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3943 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3943 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3945 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3946 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3947 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3948 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3949 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3950 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3951 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3952 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3952 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3953 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3954 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3954 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5197 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5198 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5199 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5199 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5200 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5201 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5202 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5203 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5204 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5205 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5207 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5208 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5209 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5209 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5213 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5214 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5214 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5215 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5216 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5217 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5218 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5233 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5233 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5235 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5235 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5237 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__22 | 223(0.06%) | 219(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__22 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3893 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3894 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3895 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3896 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3897 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3898 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3898 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3899 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3900 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD3901 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD3902 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD3903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD3904 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD3904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD3905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD3907 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD3908 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD3910 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD3910 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD3911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD3912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD3913 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD3914 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD3914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD3915 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD3916 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD3917 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD3918 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD3919 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD3919 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD3920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD3921 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD3921 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD3922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD3924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD3925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5155 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5156 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5157 | 93(0.03%) | 92(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5157 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5158 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5159 | 88(0.03%) | 87(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5160 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5161 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5162 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5165 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5166 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5167 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5167 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5168 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5170 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5171 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5172 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5172 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5173 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5174 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5175 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5176 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5191 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5191 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5193 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5193 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5195 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_541 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_542 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch8 | channel_fifo_p2__parameterized15 | 1591(0.46%) | 1579(0.46%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch8) | channel_fifo_p2__parameterized15 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2_462 | 829(0.24%) | 829(0.24%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2_462 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_467 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_468 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_469 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_539 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_470 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_538 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_471 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_537 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_472 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_473 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_474 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_536 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_475 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_535 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_476 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_534 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0_477 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_478 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_533 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_479 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_532 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_480 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_531 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_481 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_530 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_482 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_529 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_483 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_484 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_528 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_485 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_486 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_527 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_487 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_526 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_488 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_525 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_489 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_524 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_490 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_491 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_523 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5_492 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_493 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_522 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_494 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_495 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_521 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_496 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_497 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_520 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_498 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_499 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_519 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_500 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter_501 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init_502 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_516 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset_517 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_518 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_503 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_515 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_504 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_505 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_506 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_507 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_508 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_509 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_510 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_511 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_512 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_513 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer_514 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized15 | 118(0.03%) | 118(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized15 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_465 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_466 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__27 | 212(0.06%) | 208(0.06%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__27 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4058 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4059 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4060 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4061 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4062 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4063 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4063 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4064 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4065 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4066 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4067 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4069 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4072 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4073 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4075 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4075 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4077 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4078 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4079 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4080 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4081 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4082 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4083 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4084 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4084 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4085 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4086 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4086 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5365 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5366 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5367 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5367 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5368 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5369 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5370 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5371 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5372 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5373 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5375 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5376 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5377 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5377 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5378 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5380 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5381 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5382 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5382 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5383 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5384 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5385 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5386 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5401 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5401 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5403 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5403 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5405 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__26 | 201(0.06%) | 197(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__26 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4025 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4026 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4027 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4028 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4029 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4030 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4030 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4031 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4032 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4033 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4034 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4037 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4039 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4040 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4042 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4042 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4044 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4045 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4046 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4047 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4048 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4049 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4050 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4051 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4051 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4053 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4053 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5323 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5324 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5325 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5325 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5326 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5327 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5328 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5329 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5330 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5333 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5334 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5335 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5335 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5336 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5338 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5339 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5340 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5340 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5341 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5342 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5343 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5344 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5359 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5359 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5360 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5361 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5361 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5363 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__25 | 224(0.06%) | 220(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__25 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD3992 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD3993 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD3994 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD3995 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD3996 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD3997 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD3997 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD3998 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD3999 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4000 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4001 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4003 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4006 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4007 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4009 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4009 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4011 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4012 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4013 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4014 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4015 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4016 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4017 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4018 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4018 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4020 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4020 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5281 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5282 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5283 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5283 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5284 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5285 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5286 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5287 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5288 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5289 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5291 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5292 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5293 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5293 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5294 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5296 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5297 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5298 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5298 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5299 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5300 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5301 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5302 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5317 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5317 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5319 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5319 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5321 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_463 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx_464 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch9 | channel_fifo_p2__parameterized17 | 1706(0.49%) | 1694(0.49%) | 0(0.00%) | 12(0.01%) | 3493(0.50%) | 27(2.29%) | 0(0.00%) | 0(0.00%) | | (ch9) | channel_fifo_p2__parameterized17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | fex_chan_regs_p2 | 908(0.26%) | 908(0.26%) | 0(0.00%) | 0(0.00%) | 1616(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | fex_chan_regs_p2 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 97(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_autoreset_disable | ipbus_reg_v_396 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_control_reg | ipbus_reg_v_397 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_status_reg | ipbus_syncreg_v_398 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_status_reg) | ipbus_syncreg_v_398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_461 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_channel_up_timer_reg | ipbus_syncreg_v_399 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_channel_up_timer_reg) | ipbus_syncreg_v_399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_460 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Aurora_self_reset_count_reg | ipbus_syncreg_v_400 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Aurora_self_reset_count_reg) | ipbus_syncreg_v_400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_459 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_control_reg | ipbus_reg_v_401 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FEX_Busy_timer_reset_reg | ipbus_reg_v_402 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_busy_status_reg | ipbus_syncreg_v_403 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_busy_status_reg) | ipbus_syncreg_v_403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_458 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_raw_busy_timer_reg | ipbus_syncreg_v_404 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_raw_busy_timer_reg) | ipbus_syncreg_v_404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_457 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Fex_tob_busy_timer_reg | ipbus_syncreg_v_405 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Fex_tob_busy_timer_reg) | ipbus_syncreg_v_405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_456 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frame_error_counter | error_counter__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_rcv_timer_reg | ipbus_syncreg_v_406 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_rcv_timer_reg) | ipbus_syncreg_v_406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_455 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_busy_Count_reg | ipbus_syncreg_v_407 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_busy_Count_reg) | ipbus_syncreg_v_407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_454 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_fill_level_reg | ipbus_syncreg_v_408 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_fill_level_reg) | ipbus_syncreg_v_408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_453 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_1_fifo_xoff_Count_reg | ipbus_syncreg_v_409 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_1_fifo_xoff_Count_reg) | ipbus_syncreg_v_409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_452 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_Count_reg | ipbus_syncreg_v_410 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_busy_Count_reg) | ipbus_syncreg_v_410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_451 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_control_reg | ipbus_reg_v_411 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_fill_level_reg | ipbus_syncreg_v_412 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_fill_level_reg) | ipbus_syncreg_v_412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_450 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_reset_reg | ipbus_reg_v_413 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_status_reg | ipbus_syncreg_v_414 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_status_reg) | ipbus_syncreg_v_414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_449 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_Count_reg | ipbus_syncreg_v_415 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_fifo_xoff_Count_reg) | ipbus_syncreg_v_415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_448 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_l1id_repeat_reg | ipbus_syncreg_v_416 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_l1id_repeat_reg) | ipbus_syncreg_v_416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_447 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_packets_read_reg | ipbus_syncreg_v_417 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Tob_packets_read_reg) | ipbus_syncreg_v_417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_446 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_Busy_control_reg | ipbus_reg_v_418 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | UFC_parity_error_count_reg | ipbus_syncreg_v_419 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (UFC_parity_error_count_reg) | ipbus_syncreg_v_419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_445 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_reset_pulse | pulse_stretch__parameterized5 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_Count_reg | ipbus_syncreg_v_420 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_busy_Count_reg) | ipbus_syncreg_v_420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_444 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_busy_counter | threshold_counter_421 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_fill_level_reg | ipbus_syncreg_v_422 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_fill_level_reg) | ipbus_syncreg_v_422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_443 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_reset_reg | ipbus_reg_v_423 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_status_reg | ipbus_syncreg_v_424 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_status_reg) | ipbus_syncreg_v_424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_442 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_watermark | watermark_425 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_Count_reg | ipbus_syncreg_v_426 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bulk_fifo_xoff_Count_reg) | ipbus_syncreg_v_426 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_441 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_fifo_xoff_counter | threshold_counter_427 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_len_err_counter | edge_error_counter | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_reset | channel_init | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | self_reset_inst | self_reset | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 88(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretcher | pulse_stretch__parameterized5_440 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_integrity_status_reg | ipbus_syncreg_v_428 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_integrity_status_reg) | ipbus_syncreg_v_428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_439 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hard_error_counter | error_counter__parameterized0_429 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc_err_counter | error_counter__parameterized0_430 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_error_counter | error_counter__parameterized0_431 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | soft_error_counter | error_counter__parameterized0_432 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob1_fifo_xoff_counter | threshold_counter_433 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_busy_counter | threshold_counter_434 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_1_fifo_watermark | watermark_435 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_busy_counter | threshold_counter_436 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_watermark | watermark_437 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_fifo_xoff_counter | threshold_counter_438 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_rcv_timer | tob_rx_timer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_pipe | aurora_pipe_p2__parameterized17 | 114(0.03%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 416(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_pipe) | aurora_pipe_p2__parameterized17 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 384(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_gen | CRC__parameterized1_394 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3_395 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.calo_fifo | dual_input_fifo_4k__xdcDup__30 | 238(0.07%) | 234(0.07%) | 0(0.00%) | 4(0.01%) | 423(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.calo_fifo) | dual_input_fifo_4k__xdcDup__30 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4157 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4158 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4159 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4160 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4161 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4162 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4162 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4163 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4164 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4165 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4166 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4168 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4169 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4171 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4172 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4174 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4174 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4176 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4177 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4178 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4179 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4180 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4181 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4182 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4183 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4183 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4185 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4185 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5491 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5492 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5493 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 185(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5493 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5494 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5495 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 157(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5496 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5497 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5498 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5501 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5502 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5503 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5503 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5504 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5507 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5508 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 72(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5508 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5509 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5510 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5511 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5512 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5527 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5527 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5529 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5529 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5531 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob1_fifo | dual_input_fifo_4k__xdcDup__29 | 207(0.06%) | 203(0.06%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob1_fifo) | dual_input_fifo_4k__xdcDup__29 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4124 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4125 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4126 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4127 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4128 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4129 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4129 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4130 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4131 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4132 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4133 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4138 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4139 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4141 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4141 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4143 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4144 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4145 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4146 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4147 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4148 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4149 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4150 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4150 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4152 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4152 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5449 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5450 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5451 | 94(0.03%) | 93(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5451 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5452 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5453 | 89(0.03%) | 88(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5454 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5455 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5456 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5457 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5459 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5460 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5461 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5461 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5462 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5464 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5465 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5466 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5466 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5467 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5468 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5469 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5470 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5485 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5485 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5486 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5487 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5487 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5489 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | norm_fifo.no_fifo_ila.clk_cross_tob_fifo | dual_input_fifo_4k__xdcDup__28 | 232(0.07%) | 228(0.07%) | 0(0.00%) | 4(0.01%) | 424(0.06%) | 9(0.76%) | 0(0.00%) | 0(0.00%) | | (norm_fifo.no_fifo_ila.clk_cross_tob_fifo) | dual_input_fifo_4k__xdcDup__28 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_cross_fifo | aurora_in_fifo_HD4091 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | aurora_in_fifo_fifo_generator_v13_2_7_HD4092 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | aurora_in_fifo_fifo_generator_v13_2_7_synth_HD4093 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | aurora_in_fifo_fifo_generator_top_HD4094 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | aurora_in_fifo_fifo_generator_ramfifo_HD4095 | 87(0.03%) | 84(0.02%) | 0(0.00%) | 3(0.01%) | 238(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | aurora_in_fifo_clk_x_pntrs_HD4096 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | aurora_in_fifo_clk_x_pntrs_HD4096 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray_HD4097 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | aurora_in_fifo_xpm_cdc_gray__2_HD4098 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | aurora_in_fifo_rd_logic_HD4099 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | aurora_in_fifo_rd_fwft_HD4100 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.grdc2.rdc | aurora_in_fifo_rd_dc_fwft_ext_as_HD4101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | aurora_in_fifo_rd_status_flags_as_HD4102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | aurora_in_fifo_rd_status_flags_as_HD4102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | aurora_in_fifo_compare_1_HD4103 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_2_HD4104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | aurora_in_fifo_rd_bin_cntr_HD4105 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | aurora_in_fifo_wr_logic_HD4106 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | aurora_in_fifo_wr_status_flags_as_HD4108 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | aurora_in_fifo_wr_status_flags_as_HD4108 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | aurora_in_fifo_compare_HD4109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | aurora_in_fifo_compare_0_HD4110 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | aurora_in_fifo_wr_bin_cntr_HD4111 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | aurora_in_fifo_memory_HD4112 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 77(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | aurora_in_fifo_memory_HD4112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | aurora_in_fifo_blk_mem_gen_v8_4_5_HD4113 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | aurora_in_fifo_blk_mem_gen_v8_4_5_synth_HD4114 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | aurora_in_fifo_blk_mem_gen_top_HD4115 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | aurora_in_fifo_blk_mem_gen_generic_cstr_HD4116 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | aurora_in_fifo_blk_mem_gen_prim_width_HD4117 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | aurora_in_fifo_blk_mem_gen_prim_width_HD4117 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | aurora_in_fifo_blk_mem_gen_prim_wrapper_HD4118 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | aurora_in_fifo_reset_blk_ramfifo_HD4119 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | aurora_in_fifo_reset_blk_ramfifo_HD4119 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | aurora_in_fifo_xpm_cdc_single_HD4120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | aurora_in_fifo_xpm_cdc_single__2_HD4121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst_HD4122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | aurora_in_fifo_xpm_cdc_sync_rst__2_HD4123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_fifo | processor_in_fifo_HD5407 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | processor_in_fifo_fifo_generator_v13_2_7_HD5408 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5409 | 95(0.03%) | 94(0.03%) | 0(0.00%) | 1(0.01%) | 186(0.03%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | processor_in_fifo_fifo_generator_v13_2_7_synth_HD5409 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | processor_in_fifo_fifo_generator_top_HD5410 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | grf.rf | processor_in_fifo_fifo_generator_ramfifo_HD5411 | 90(0.03%) | 89(0.03%) | 0(0.00%) | 1(0.01%) | 158(0.02%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | processor_in_fifo_rd_logic_HD5412 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | processor_in_fifo_rd_fwft_HD5413 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | processor_in_fifo_rd_status_flags_ss_HD5414 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | processor_in_fifo_rd_status_flags_ss_HD5414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_2_HD5415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | processor_in_fifo_compare_3_HD5416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | processor_in_fifo_rd_bin_cntr_HD5417 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | processor_in_fifo_wr_logic_HD5418 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | processor_in_fifo_wr_status_flags_ss_HD5419 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | processor_in_fifo_wr_status_flags_ss_HD5419 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | processor_in_fifo_compare_HD5420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | processor_in_fifo_compare_0_HD5421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | processor_in_fifo_compare_1_HD5422 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | processor_in_fifo_wr_bin_cntr_HD5423 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | processor_in_fifo_memory_HD5424 | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | processor_in_fifo_memory_HD5424 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | processor_in_fifo_blk_mem_gen_v8_4_5_HD5425 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | processor_in_fifo_blk_mem_gen_v8_4_5_synth_HD5426 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | processor_in_fifo_blk_mem_gen_top_HD5427 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | processor_in_fifo_blk_mem_gen_generic_cstr_HD5428 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | processor_in_fifo_blk_mem_gen_prim_width_HD5429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper_HD5430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized0_HD5431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD5432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized1_HD5433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD5434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized2_HD5435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized2_HD5436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized3_HD5437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized3_HD5438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized4_HD5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized4_HD5440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized5_HD5441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized5_HD5442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5443 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[7].ram.r) | processor_in_fifo_blk_mem_gen_prim_width__parameterized6_HD5443 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | processor_in_fifo_blk_mem_gen_prim_wrapper__parameterized6_HD5444 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5445 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | processor_in_fifo_reset_blk_ramfifo__parameterized0_HD5445 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | processor_in_fifo_xpm_cdc_sync_rst_HD5446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_cc.rstblk_cc | processor_in_fifo_reset_blk_ramfifo_HD5447 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized1_393 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ufc_receiver | ufc_rx | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.registers | backplane_regs | 2070(0.60%) | 2070(0.60%) | 0(0.00%) | 0(0.00%) | 595(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.registers) | backplane_regs | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Backplane_control_reg_2_reg | ipbus_reg_v_374 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_busy_threshold_reg | ipbus_reg_v_375 | 314(0.09%) | 314(0.09%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_fifo_xoff_threshold_reg | ipbus_reg_v_376 | 314(0.09%) | 314(0.09%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Time_count_value | ipbus_syncreg_v_377 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Time_count_value) | ipbus_syncreg_v_377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_392 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_busy_threshold_reg | ipbus_reg_v_378 | 315(0.09%) | 315(0.09%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Tob_fifo_xoff_threshold_reg | ipbus_reg_v_379 | 845(0.24%) | 845(0.24%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | backplane_control_reg | ipbus_reg_v_380 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_active_time_reg | ipbus_syncreg_v_381 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (busy_active_time_reg) | ipbus_syncreg_v_381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_391 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_disable | ipbus_reg_v_382 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_map | ipbus_syncreg_v_383 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (channel_map) | ipbus_syncreg_v_383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_390 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_tester | clock_test_ipbus | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_status | ipbus_syncreg_v_384 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clock_status) | ipbus_syncreg_v_384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_389 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | first_last_chan | ipbus_syncreg_v_385 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (first_last_chan) | ipbus_syncreg_v_385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_388 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | first_last_encode | priority_encoder | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ro_ctrl_status | ipbus_syncreg_v_386 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ro_ctrl_status) | ipbus_syncreg_v_386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_387 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.ttc_regs | ttc_chan_regs | 522(0.15%) | 522(0.15%) | 0(0.00%) | 0(0.00%) | 888(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_reg.ttc_regs) | ttc_chan_regs | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BCN_reg | ipbus_syncreg_v_330 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (BCN_reg) | ipbus_syncreg_v_330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_373 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CTTC_link_stat_reg | ipbus_syncreg_v_331 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (CTTC_link_stat_reg) | ipbus_syncreg_v_331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_372 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Duplicate_L1ID_Count_reg | ipbus_syncreg_v_332 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Duplicate_L1ID_Count_reg) | ipbus_syncreg_v_332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_371 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_Value_reg | ipbus_syncreg_v_333 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (L1ID_Value_reg) | ipbus_syncreg_v_333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_370 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1id_Capture_Status_reg | ipbus_syncreg_v_334 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (L1id_Capture_Status_reg) | ipbus_syncreg_v_334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_369 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1id_Continuity_Capture_Control | ipbus_reg_v_335 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Local_Counter_Miss_reg | ipbus_syncreg_v_336 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Local_Counter_Miss_reg) | ipbus_syncreg_v_336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_368 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Mismatch_err_reg | ipbus_syncreg_v_337 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Mismatch_err_reg) | ipbus_syncreg_v_337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_367 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_Miss_reg | ipbus_syncreg_v_338 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_Miss_reg) | ipbus_syncreg_v_338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_366 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_control_reg | ipbus_reg_v_339 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_busy_Count_reg | ipbus_syncreg_v_340 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_fifo_busy_Count_reg) | ipbus_syncreg_v_340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_365 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_busy_threshold_reg | ipbus_reg_v_341 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_control_reg | ipbus_reg_v_342 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_fill_level_reg | ipbus_syncreg_v_343 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_fifo_fill_level_reg) | ipbus_syncreg_v_343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_364 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_fifo_status_reg | ipbus_syncreg_v_344 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TTC_fifo_status_reg) | ipbus_syncreg_v_344 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_363 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TTC_reset_register | ipbus_reg_v_345 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Timeout_threshold_reg | ipbus_reg_v_346 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_adjust_reg | ipbus_reg_v_347 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_err_counter | error_counter | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | disperity_err_counter | error_counter_348 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_count_reg | ipbus_syncreg_v_349 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_count_reg) | ipbus_syncreg_v_349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_362 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | felix_backpressure_reg | ipbus_syncreg_v_350 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (felix_backpressure_reg) | ipbus_syncreg_v_350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_361 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_reg | ipbus_syncreg_v_351 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (orbit_reg) | ipbus_syncreg_v_351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_360 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_header_info | ipbus_reg_v_352 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | table_err_counter | error_counter_353 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | total_event_count_msb | ipbus_syncreg_v_354 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (total_event_count_msb) | ipbus_syncreg_v_354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_359 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | total_event_count_reg | ipbus_syncreg_v_355 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (total_event_count_reg) | ipbus_syncreg_v_355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_358 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_busy_counter | threshold_counter_356 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_watermark | watermark_357 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | readout_controller | ro_controller | 1324(0.38%) | 1090(0.31%) | 0(0.00%) | 234(0.13%) | 2146(0.31%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (readout_controller) | ro_controller | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | readout_ctrl_ila2 | rod_ROctrl_mux_ila | 1136(0.33%) | 902(0.26%) | 0(0.00%) | 234(0.13%) | 1973(0.28%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (readout_ctrl_ila2) | rod_ROctrl_mux_ila | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | rod_ROctrl_mux_ila_ila_v6_2_12_ila | 1136(0.33%) | 902(0.26%) | 0(0.00%) | 234(0.13%) | 1973(0.28%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | rod_ROctrl_mux_ila_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | rod_ROctrl_mux_ila_ila_v6_2_12_ila_core | 1135(0.33%) | 901(0.26%) | 0(0.00%) | 234(0.13%) | 1967(0.28%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_core | 84(0.02%) | 0(0.00%) | 0(0.00%) | 84(0.05%) | 209(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | rod_ROctrl_mux_ila_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | rod_ROctrl_mux_ila_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_52 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_53 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_53 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_54 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | rod_ROctrl_mux_ila_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | rod_ROctrl_mux_ila_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | rod_ROctrl_mux_ila_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_48 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA_nodelay_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_49 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized1_49 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized1_50 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized2_51 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | rod_ROctrl_mux_ila_ila_v6_2_12_ila_register | 685(0.20%) | 684(0.20%) | 0(0.00%) | 1(0.01%) | 1050(0.15%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_register | 284(0.08%) | 283(0.08%) | 0(0.00%) | 1(0.01%) | 160(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | rod_ROctrl_mux_ila_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized23 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized24 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized1_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl_34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized51 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_33 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg__parameterized26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | rod_ROctrl_mux_ila_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | rod_ROctrl_mux_ila_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trigger | 184(0.05%) | 84(0.02%) | 0(0.00%) | 100(0.06%) | 356(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | rod_ROctrl_mux_ila_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trig_match | 178(0.05%) | 83(0.02%) | 0(0.00%) | 95(0.05%) | 346(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | rod_ROctrl_mux_ila_ila_v6_2_12_ila_trig_match | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_21 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_14 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_15 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_15 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_8 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | rod_ROctrl_mux_ila_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | rod_ROctrl_mux_ila_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | rod_ROctrl_mux_ila_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | rod_ROctrl_mux_ila_ltlib_v1_0_0_generic_memrd | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 191(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ro_crc | CRC__parameterized1__18 | 93(0.03%) | 93(0.03%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_processor_0 | tob_processor__xdcDup__1 | 6283(1.81%) | 5894(1.70%) | 0(0.00%) | 389(0.22%) | 7923(1.14%) | 17(1.44%) | 1(0.04%) | 0(0.00%) | | chan_in_gen | dummy_chan_in_188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_builder_0 | ev_builder__xdcDup__1 | 3998(1.15%) | 3609(1.04%) | 0(0.00%) | 389(0.22%) | 4396(0.63%) | 14(1.19%) | 1(0.04%) | 0(0.00%) | | (event_builder_0) | ev_builder__xdcDup__1 | 509(0.15%) | 509(0.15%) | 0(0.00%) | 0(0.00%) | 547(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | State_machine_ILA | ila_ev_builder_HD6290 | 2159(0.62%) | 1770(0.51%) | 0(0.00%) | 389(0.22%) | 3238(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (State_machine_ILA) | ila_ev_builder_HD6290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ev_builder_ila_v6_2_12_ila_HD6291 | 2159(0.62%) | 1770(0.51%) | 0(0.00%) | 389(0.22%) | 3238(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_ev_builder_ila_v6_2_12_ila_HD6291 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ev_builder_ila_v6_2_12_ila_core_HD6292 | 2158(0.62%) | 1769(0.51%) | 0(0.00%) | 389(0.22%) | 3232(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_ev_builder_ila_v6_2_12_ila_core_HD6292 | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 259(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ev_builder_ila_v6_2_12_ila_trace_memory_HD6293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ev_builder_blk_mem_gen_v8_4_5_HD6294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_ev_builder_blk_mem_gen_v8_4_5_synth_HD6295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD6296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD6297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD6298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD6299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD6300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD6301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD6302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD6303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD6304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD6305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD6306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD6307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4_HD6308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4_HD6309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5_HD6310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5_HD6311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ev_builder_ila_v6_2_12_ila_cap_ctrl_legacy_HD6312 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ev_builder_ila_v6_2_12_ila_cap_ctrl_legacy_HD6312 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ev_builder_ltlib_v1_0_0_cfglut6__parameterized0_HD6313 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ev_builder_ltlib_v1_0_0_cfglut7_HD6314 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ev_builder_ltlib_v1_0_0_cfglut7__1_HD6315 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ev_builder_ila_v6_2_12_ila_cap_addrgen_HD6316 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ev_builder_ila_v6_2_12_ila_cap_addrgen_HD6316 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ev_builder_ltlib_v1_0_0_cfglut6__1_HD6317 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ev_builder_ila_v6_2_12_ila_cap_sample_counter_HD6318 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ev_builder_ila_v6_2_12_ila_cap_sample_counter_HD6318 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ev_builder_ltlib_v1_0_0_cfglut4__1_HD6319 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5__1_HD6320 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ev_builder_ltlib_v1_0_0_cfglut6_HD6321 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay__1_HD6322 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_117_HD6323 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_117_HD6323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_118_HD6324 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_118_HD6324 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1_119_HD6325 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2_120_HD6326 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ev_builder_ila_v6_2_12_ila_cap_window_counter_HD6327 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ev_builder_ila_v6_2_12_ila_cap_window_counter_HD6327 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ev_builder_ltlib_v1_0_0_cfglut4_HD6328 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5_HD6329 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5__2_HD6330 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay_HD6331 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_HD6332 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_HD6332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_HD6333 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_HD6333 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD6334 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD6335 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay__2_HD6336 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_113_HD6337 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_113_HD6337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_114_HD6338 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_114_HD6338 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1_115_HD6339 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2_116_HD6340 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ev_builder_ila_v6_2_12_ila_register_HD6341 | 1520(0.44%) | 1519(0.44%) | 0(0.00%) | 1(0.01%) | 2046(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ev_builder_ila_v6_2_12_ila_register_HD6341 | 417(0.12%) | 416(0.12%) | 0(0.00%) | 1(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s_HD6342 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized9_HD6343 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized10_HD6344 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized11_HD6345 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized12_HD6346 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized13_HD6347 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized14_HD6348 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized15_HD6349 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[17].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized16_HD6350 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[18].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized17_HD6351 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[19].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized18_HD6352 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized0_HD6353 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[20].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized19_HD6354 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[21].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized20_HD6355 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[22].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized21_HD6356 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[23].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized22_HD6357 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[24].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized23_HD6358 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[25].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized24_HD6359 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[26].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized25_HD6360 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[27].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized26_HD6361 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[28].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized27_HD6362 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[29].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized28_HD6363 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized1_HD6364 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized2_HD6365 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized3_HD6366 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized4_HD6367 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized5_HD6368 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized6_HD6369 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized7_HD6370 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized8_HD6371 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized29_HD6372 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ev_builder_xsdbs_v1_0_2_xsdbs_HD6373 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized84_HD6374 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_109_HD6375 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized85_HD6376 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_108_HD6377 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized86_HD6378 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_107_HD6379 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized87_HD6380 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_106_HD6381 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized88_HD6382 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_105_HD6383 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized89_HD6384 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1_104_HD6385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized69_HD6386 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_112_HD6387 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized70_HD6388 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized0_HD6389 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized71_HD6390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_111_HD6391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized90_HD6392 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1_103_HD6393 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized91_HD6394 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_102_HD6395 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized92_HD6396 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1_HD6397 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized93_HD6398 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_101_HD6399 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized94_HD6400 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_100_HD6401 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized95_HD6402 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_99_HD6403 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized97_HD6404 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_98_HD6405 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized99_HD6406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_97_HD6407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized102_HD6408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized102_HD6408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_96_HD6409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized72_HD6410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_110_HD6411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized30_HD6412 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ev_builder_xsdbs_v1_0_2_reg_stream_HD6413 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_HD6414 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ev_builder_xsdbs_v1_0_2_reg_stream__parameterized0_HD6415 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_ev_builder_xsdbs_v1_0_2_reg_stream__parameterized0_HD6415 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_HD6416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ev_builder_ila_v6_2_12_ila_reset_ctrl_HD6417 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ev_builder_ila_v6_2_12_ila_reset_ctrl_HD6417 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ev_builder_ltlib_v1_0_0_rising_edge_detection_HD6418 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__2_HD6419 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__3_HD6420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__1_HD6421 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer_HD6422 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ev_builder_ltlib_v1_0_0_rising_edge_detection__1_HD6423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ev_builder_ila_v6_2_12_ila_trigger_HD6424 | 340(0.10%) | 109(0.03%) | 0(0.00%) | 231(0.13%) | 525(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ev_builder_ila_v6_2_12_ila_trigger_HD6424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ev_builder_ltlib_v1_0_0_match_HD6425 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ev_builder_ltlib_v1_0_0_match_HD6425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_HD6426 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_HD6426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA_91_HD6427 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA_91_HD6427 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_92_HD6428 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_93_HD6429 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_94_HD6430 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_95_HD6431 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ev_builder_ila_v6_2_12_ila_trig_match_HD6432 | 322(0.09%) | 108(0.03%) | 0(0.00%) | 214(0.12%) | 492(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_ev_builder_ila_v6_2_12_ila_trig_match_HD6432 | 108(0.03%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized0_HD6433 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized0_HD6433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized0_HD6434 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized0_HD6434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_89_HD6435 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_89_HD6435 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_90_HD6436 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__8_HD6437 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__8_HD6437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_60_HD6438 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_60_HD6438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_61_HD6439 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_61_HD6439 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_62_HD6440 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__9_HD6441 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__9_HD6441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_57_HD6442 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_57_HD6442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_58_HD6443 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_58_HD6443 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_59_HD6444 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__10_HD6445 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__10_HD6445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_54_HD6446 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_54_HD6446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_55_HD6447 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_55_HD6447 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_56_HD6448 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__11_HD6449 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__11_HD6449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_51_HD6450 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_51_HD6450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_52_HD6451 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_52_HD6451 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_53_HD6452 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized3_HD6453 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized3_HD6453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized3_HD6454 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized3_HD6454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized1_HD6455 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized1_HD6455 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_48_HD6456 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_49_HD6457 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_50_HD6458 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__12_HD6459 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__12_HD6459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_45_HD6460 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_45_HD6460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_46_HD6461 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_46_HD6461 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_47_HD6462 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized4_HD6463 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized4_HD6463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized4_HD6464 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized4_HD6464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_42_HD6465 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_42_HD6465 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_43_HD6466 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_44_HD6467 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[17].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__13_HD6468 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[17].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__13_HD6468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_39_HD6469 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_39_HD6469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_40_HD6470 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_40_HD6470 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_41_HD6471 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[18].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__14_HD6472 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[18].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__14_HD6472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_36_HD6473 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_36_HD6473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_37_HD6474 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_37_HD6474 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD6475 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[19].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__1_HD6476 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[19].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__1_HD6476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_32_HD6477 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_32_HD6477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_33_HD6478 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_33_HD6478 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_34_HD6479 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD6480 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized1__1_HD6481 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized1__1_HD6481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_86_HD6482 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_86_HD6482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_87_HD6483 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_87_HD6483 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_88_HD6484 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[20].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__15_HD6485 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[20].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__15_HD6485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_29_HD6486 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_29_HD6486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_30_HD6487 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_30_HD6487 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_31_HD6488 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[21].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__16_HD6489 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[21].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__16_HD6489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_26_HD6490 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_26_HD6490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_27_HD6491 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_27_HD6491 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD6492 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[22].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__17_HD6493 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[22].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__17_HD6493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_23_HD6494 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_23_HD6494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_24_HD6495 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_24_HD6495 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD6496 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[23].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__18_HD6497 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[23].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__18_HD6497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_20_HD6498 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_20_HD6498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_21_HD6499 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_21_HD6499 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD6500 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[24].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__2_HD6501 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[24].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__2_HD6501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_16_HD6502 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_16_HD6502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_17_HD6503 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_17_HD6503 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_18_HD6504 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_19_HD6505 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[25].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized6_HD6506 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[25].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized6_HD6506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized6_HD6507 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized6_HD6507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized3_HD6508 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized3_HD6508 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_8_HD6509 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_9_HD6510 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_10_HD6511 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_11_HD6512 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_12_HD6513 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_13_HD6514 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_14_HD6515 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_15_HD6516 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[26].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__19_HD6517 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[26].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__19_HD6517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_5_HD6518 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_5_HD6518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_6_HD6519 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_6_HD6519 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_7_HD6520 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[27].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2_HD6521 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[27].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2_HD6521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_HD6522 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_HD6522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_HD6523 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_HD6523 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD6524 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[28].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5_HD6525 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[28].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5_HD6525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_HD6526 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_HD6526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_HD6527 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_HD6527 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_2_HD6528 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_3_HD6529 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[29].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized7_HD6530 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[29].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized7_HD6530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized7_HD6531 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized7_HD6531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA_HD6532 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA_HD6532 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_HD6533 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_0_HD6534 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_1_HD6535 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD6536 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized1_HD6537 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized1_HD6537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_HD6538 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_HD6538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_84_HD6539 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_84_HD6539 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_85_HD6540 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__1_HD6541 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__1_HD6541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_81_HD6542 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_81_HD6542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_82_HD6543 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_82_HD6543 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_83_HD6544 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__2_HD6545 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__2_HD6545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_78_HD6546 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_78_HD6546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_79_HD6547 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_79_HD6547 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_80_HD6548 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__3_HD6549 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__3_HD6549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_75_HD6550 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_75_HD6550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_76_HD6551 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_76_HD6551 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_77_HD6552 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__4_HD6553 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__4_HD6553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_72_HD6554 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_72_HD6554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_73_HD6555 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_73_HD6555 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_74_HD6556 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__5_HD6557 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__5_HD6557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_69_HD6558 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_69_HD6558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_70_HD6559 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_70_HD6559 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_71_HD6560 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__6_HD6561 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__6_HD6561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_66_HD6562 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_66_HD6562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_67_HD6563 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_67_HD6563 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_68_HD6564 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__7_HD6565 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__7_HD6565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_63_HD6566 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_63_HD6566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_64_HD6567 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_64_HD6567 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_65_HD6568 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ev_builder_ltlib_v1_0_0_generic_memrd_HD6569 | 103(0.03%) | 101(0.03%) | 0(0.00%) | 2(0.01%) | 241(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_trailer_crc | event_trailer_CRC20__3 | 197(0.06%) | 197(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_block | flx_CRC_327 | 197(0.06%) | 197(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_header_crc | hdr_in_crc9__2 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (channel_header_crc) | hdr_in_crc9__2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_329 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_crc20_gen | CRC_322 | 244(0.07%) | 244(0.07%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_crc9_gen | CRC__parameterized1_323 | 117(0.03%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_trailer_err_map | trailer_map__3 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dbg_trailer_err_map) | trailer_map__3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_efex_map.chan_selector | onehot_dec__parameterized1_326 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | debug_fifo | event_builder_fifo_HD6587 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | event_builder_fifo_axis_data_fifo_v2_0_8_top_HD6588 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | event_builder_fifo_xpm_fifo_axis_HD6589 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | event_builder_fifo_xpm_fifo_axis_HD6589 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | event_builder_fifo_xpm_cdc_sync_rst_HD6590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | event_builder_fifo_xpm_fifo_base_HD6591 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | event_builder_fifo_xpm_fifo_base_HD6591 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized1_HD6592 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | event_builder_fifo_xpm_memory_base_HD6593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_HD6594 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_HD6595 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | event_builder_fifo_xpm_fifo_reg_bit_HD6596 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_0_HD6597 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_1_HD6598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | event_builder_fifo_xpm_counter_updn__parameterized0_HD6599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | event_builder_fifo_xpm_fifo_rst_HD6600 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_fifo | event_builder_fifo_HD6601 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | event_builder_fifo_axis_data_fifo_v2_0_8_top_HD6602 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | event_builder_fifo_xpm_fifo_axis_HD6603 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | event_builder_fifo_xpm_fifo_axis_HD6603 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | event_builder_fifo_xpm_cdc_sync_rst_HD6604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | event_builder_fifo_xpm_fifo_base_HD6605 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | event_builder_fifo_xpm_fifo_base_HD6605 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized1_HD6606 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | event_builder_fifo_xpm_memory_base_HD6607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_HD6608 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_HD6609 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | event_builder_fifo_xpm_fifo_reg_bit_HD6610 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_0_HD6611 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_1_HD6612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | event_builder_fifo_xpm_counter_updn__parameterized0_HD6613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | event_builder_fifo_xpm_fifo_rst_HD6614 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9__4 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9__4 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_328 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_trailer_crc | event_trailer_CRC20_324 | 369(0.11%) | 369(0.11%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_block | flx_CRC_325 | 369(0.11%) | 369(0.11%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | evnt_trailer_err_map | trailer_map__2 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | timeout | tob_timeout__2 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wdog_timer | watchdog__2 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | tob_proc_regs_189 | 1715(0.50%) | 1715(0.50%) | 0(0.00%) | 0(0.00%) | 3442(0.50%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | tob_proc_regs_189 | 784(0.23%) | 784(0.23%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_capt | l1id_capture_191 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 426(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (l1id_capt) | l1id_capture_191 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.L1ID_Capture_Control_reg | ipbus_reg_v_311 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.L1ID_Capture_status_reg | ipbus_syncreg_v_312 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.L1ID_Capture_status_reg) | ipbus_syncreg_v_312 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_321 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_miss_reg | ipbus_syncreg_v_313 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_miss_reg) | ipbus_syncreg_v_313 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_320 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_last_reg | ipbus_syncreg_v_314 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_last_reg) | ipbus_syncreg_v_314 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_319 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_miss_reg | ipbus_syncreg_v_315 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_miss_reg) | ipbus_syncreg_v_315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_318 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_penultimate_reg | ipbus_syncreg_v_316 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_penultimate_reg) | ipbus_syncreg_v_316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_317 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Event_fifo_control_reg | ipbus_reg_v_192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Event_fifo_reset_reg | ipbus_reg_v_193 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Full_mode_control_reg | ipbus_reg_v_194 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_busy_Count_reg | ipbus_syncreg_v_195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_busy_Count_reg) | ipbus_syncreg_v_195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_fifo_status_reg | ipbus_syncreg_v_196 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_fifo_status_reg) | ipbus_syncreg_v_196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_309 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_xoff_Count_reg | ipbus_syncreg_v_197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_xoff_Count_reg) | ipbus_syncreg_v_197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_staging_fifo_resets_reg | ipbus_reg_v_198 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_timeout_reg | ipbus_ctrlreg_v__parameterized0_199 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.avg_event_time_reg | ipbus_syncreg_v_200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.avg_event_time_reg) | ipbus_syncreg_v_200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.bcn_mismatch_map_reg | ipbus_syncreg_v_201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.bcn_mismatch_map_reg) | ipbus_syncreg_v_201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.chan_error_mapper | chan_err_map_202 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.crc20_error_map_reg | ipbus_syncreg_v_203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.crc20_error_map_reg) | ipbus_syncreg_v_203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.crc9_error_map_reg | ipbus_syncreg_v_204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.crc9_error_map_reg) | ipbus_syncreg_v_204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.dbg_pkt_count_reg | ipbus_syncreg_v_205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.dbg_pkt_count_reg) | ipbus_syncreg_v_205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.debug_fifo_fill_level_reg | ipbus_syncreg_v_206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.debug_fifo_fill_level_reg) | ipbus_syncreg_v_206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.debug_fifo_watermark | watermark_207 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.error_count_register | ipbus_syncreg_v_208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.error_count_register) | ipbus_syncreg_v_208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_fifo_watermark | watermark_210 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_proc_timer | event_timer_211 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_time_reg | ipbus_syncreg_v_212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.event_time_reg) | ipbus_syncreg_v_212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.flx_bp_time_reg | ipbus_syncreg_v_213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.flx_bp_time_reg) | ipbus_syncreg_v_213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fm_L1id_reg | ipbus_syncreg_v_214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.fm_L1id_reg) | ipbus_syncreg_v_214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fm_fifo_watermark | watermark_215 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.full_mode_status_reg | ipbus_syncreg_v_216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.full_mode_status_reg) | ipbus_syncreg_v_216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.input_capture | input_capture_regs_218 | 308(0.09%) | 308(0.09%) | 0(0.00%) | 0(0.00%) | 650(0.09%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | Capture_Control_reg | ipbus_reg_v_275 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Capture_status_reg | ipbus_syncreg_v_276 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Capture_status_reg) | ipbus_syncreg_v_276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_294 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Header_0_reg | ipbus_syncreg_v_277 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Header_0_reg) | ipbus_syncreg_v_277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_293 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Header_1_reg | ipbus_syncreg_v_278 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Header_1_reg) | ipbus_syncreg_v_278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_292 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Input_channel_select_reg | ipbus_reg_v_279 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | capture_lsw | ipbus_dpram_280 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | capture_msw | ipbus_dpram_281 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | input_capture_mech | input_capture_282 | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 350(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_capture_mech) | input_capture_282 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 177(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | packet_crc_289 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | packet_crc_289 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_290 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_291 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pkt_count_reg | ipbus_syncreg_v_283 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (pkt_count_reg) | ipbus_syncreg_v_283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_288 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trailer_0_reg | ipbus_syncreg_v_284 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trailer_0_reg) | ipbus_syncreg_v_284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_287 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trailer_1_reg | ipbus_syncreg_v_285 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trailer_1_reg) | ipbus_syncreg_v_285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_286 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.l1id_mismatch_map_reg | ipbus_syncreg_v_219 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.l1id_mismatch_map_reg) | ipbus_syncreg_v_219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_274 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.max_timeout_reg | ipbus_syncreg_v_220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.max_timeout_reg) | ipbus_syncreg_v_220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.packet_capture | pkt_capture_regs_221 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.packet_capture) | pkt_capture_regs_221 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_258 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_259 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_272 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_260 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_271 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_261 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_270 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_262 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_269 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_263 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_263 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_268 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_264 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_267 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_265 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_266 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_max_wait_time_L1id_reg | ipbus_syncreg_v_222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_max_wait_time_L1id_reg) | ipbus_syncreg_v_222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_wait_time_last_reg | ipbus_syncreg_v_223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_wait_time_last_reg) | ipbus_syncreg_v_223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_wait_time_max_reg | ipbus_syncreg_v_224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_wait_time_max_reg) | ipbus_syncreg_v_224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.stage_fifo_watermark | watermark_226 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.timeout_error_map_reg | ipbus_syncreg_v_227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.timeout_error_map_reg) | ipbus_syncreg_v_227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_proc_reset_reg | ipbus_reg_v_228 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_proc_status | ipbus_syncreg_v_229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.tob_proc_status) | ipbus_syncreg_v_229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_staging_control_reg | ipbus_reg_v_230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_staging_thresholds_reg | ipbus_reg_v_231 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trace_module | Processor_trace_module_232 | 117(0.03%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 144(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | Trace_Control_reg | ipbus_reg_v_242 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Trigger_pattern_reg | ipbus_reg_v_243 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | proc_trace_244 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trace_mem | ipbus_dpram__parameterized2_245 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | trace_words_reg | ipbus_syncreg_v_246 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trace_words_reg) | ipbus_syncreg_v_246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_251 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trigger_pointer_reg | ipbus_syncreg_v_247 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trigger_pointer_reg) | ipbus_syncreg_v_247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_250 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trigger_status_reg | ipbus_syncreg_v_248 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trigger_status_reg) | ipbus_syncreg_v_248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_249 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.watchdog_control_reg | ipbus_reg_v_233 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.watchdog_overflow_count_reg | ipbus_syncreg_v_234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.watchdog_overflow_count_reg) | ipbus_syncreg_v_234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.wdog_overflow_counter | edge_error_counter__parameterized1_235 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.wdog_threshold_reg | ipbus_ctrlreg_v__parameterized1_236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_busy_counter | threshold_counter_237 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_busy_flag | threshold_counter__parameterized0_238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_xoff_counter | threshold_counter_239 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_xoff_flag | threshold_counter__parameterized0_240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | channel_mux_190 | 577(0.17%) | 577(0.17%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pulse_stretcher | pulse_stretch__parameterized3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_processor_1 | tob_processor | 6250(1.80%) | 5861(1.69%) | 0(0.00%) | 389(0.22%) | 7918(1.14%) | 17(1.44%) | 1(0.04%) | 0(0.00%) | | chan_in_gen | dummy_chan_in | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_builder_0 | ev_builder | 3994(1.15%) | 3605(1.04%) | 0(0.00%) | 389(0.22%) | 4396(0.63%) | 14(1.19%) | 1(0.04%) | 0(0.00%) | | (event_builder_0) | ev_builder | 510(0.15%) | 510(0.15%) | 0(0.00%) | 0(0.00%) | 547(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | State_machine_ILA | ila_ev_builder | 2158(0.62%) | 1769(0.51%) | 0(0.00%) | 389(0.22%) | 3238(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (State_machine_ILA) | ila_ev_builder | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ev_builder_ila_v6_2_12_ila | 2158(0.62%) | 1769(0.51%) | 0(0.00%) | 389(0.22%) | 3238(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_ev_builder_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ev_builder_ila_v6_2_12_ila_core | 2157(0.62%) | 1768(0.51%) | 0(0.00%) | 389(0.22%) | 3232(0.47%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_ev_builder_ila_v6_2_12_ila_core | 108(0.03%) | 0(0.00%) | 0(0.00%) | 108(0.06%) | 259(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ev_builder_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ev_builder_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_ev_builder_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.51%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ev_builder_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ev_builder_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ev_builder_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ev_builder_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ev_builder_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ev_builder_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ev_builder_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ev_builder_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ev_builder_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ev_builder_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ev_builder_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ev_builder_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ev_builder_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_117 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_118 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_118 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1_119 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2_120 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ev_builder_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ev_builder_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ev_builder_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ev_builder_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ev_builder_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_113 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA_nodelay_113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_114 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized4_114 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized1_115 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized2_116 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ev_builder_ila_v6_2_12_ila_register | 1519(0.44%) | 1518(0.44%) | 0(0.00%) | 1(0.01%) | 2046(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ev_builder_ila_v6_2_12_ila_register | 417(0.12%) | 416(0.12%) | 0(0.00%) | 1(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[17].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[18].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized17 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[19].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized18 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[20].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized19 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[21].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized20 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[22].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized21 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[23].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized22 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[24].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized23 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[25].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized24 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[26].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized25 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[27].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized26 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[28].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized27 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[29].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized28 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized29 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ev_builder_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized84 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_109 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized85 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_108 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized86 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized87 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized88 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_105 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized89 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1_104 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_112 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized90 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1_103 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized91 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_102 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized92 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized93 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_101 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized94 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_100 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized95 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl_99 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized97 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_98 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ev_builder_xsdbs_v1_0_2_reg__parameterized72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat_110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ev_builder_xsdbs_v1_0_2_reg_p2s__parameterized30 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ev_builder_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ev_builder_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ev_builder_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_ev_builder_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ev_builder_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ev_builder_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ev_builder_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ev_builder_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ev_builder_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ev_builder_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ev_builder_ila_v6_2_12_ila_trigger | 340(0.10%) | 109(0.03%) | 0(0.00%) | 231(0.13%) | 525(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ev_builder_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ev_builder_ltlib_v1_0_0_match | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ev_builder_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA_91 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA_91 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_92 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_93 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_94 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_95 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ev_builder_ila_v6_2_12_ila_trig_match | 322(0.09%) | 108(0.03%) | 0(0.00%) | 214(0.12%) | 492(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_ev_builder_ila_v6_2_12_ila_trig_match | 108(0.03%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_89 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_89 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_90 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_60 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_61 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_61 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_62 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_57 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_58 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_58 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_54 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_55 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_55 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_56 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_51 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_52 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_52 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_53 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized3 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized3 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized1 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_50 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_45 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_46 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_46 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_42 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_42 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[17].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[17].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_39 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_40 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_40 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[18].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__14 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[18].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_36 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_37 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_37 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[19].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[19].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_32 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_33 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_33 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_86 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1_86 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_87 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_87 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_88 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[20].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[20].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_30 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[21].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[21].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_27 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_27 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[22].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__17 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[22].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_24 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[23].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[23].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[24].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[24].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_16 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_17 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2_17 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[25].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized6 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[25].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized6 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized3 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[26].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[26].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_6 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[27].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[27].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[28].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[28].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[29].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized7 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[29].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized7 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_84 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_84 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_85 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_81 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_82 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_82 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_83 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_78 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_79 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_79 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_80 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_75 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_76 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_76 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_77 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_72 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_73 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_73 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_74 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_69 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_70 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_70 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_71 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_66 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_67 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_67 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_68 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_ev_builder_ltlib_v1_0_0_match__parameterized2__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_63 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ev_builder_ltlib_v1_0_0_allx_typeA__parameterized2_63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_64 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ev_builder_ltlib_v1_0_0_all_typeA__parameterized0_64 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ev_builder_ltlib_v1_0_0_all_typeA_slice__parameterized0_65 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ev_builder_ltlib_v1_0_0_generic_memrd | 103(0.03%) | 101(0.03%) | 0(0.00%) | 2(0.01%) | 241(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_trailer_crc | event_trailer_CRC20 | 198(0.06%) | 198(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_block | flx_CRC_186 | 198(0.06%) | 198(0.06%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | channel_header_crc | hdr_in_crc9 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (channel_header_crc) | hdr_in_crc9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32_187 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_crc20_gen | CRC_184 | 243(0.07%) | 243(0.07%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_crc9_gen | CRC__parameterized1_185 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_trailer_err_map | trailer_map | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dbg_trailer_err_map) | trailer_map | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_efex_map.chan_selector | onehot_dec__parameterized1 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | debug_fifo | event_builder_fifo | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | event_builder_fifo_axis_data_fifo_v2_0_8_top | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | event_builder_fifo_xpm_fifo_axis | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | event_builder_fifo_xpm_fifo_axis | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | event_builder_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | event_builder_fifo_xpm_fifo_base | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | event_builder_fifo_xpm_fifo_base | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | event_builder_fifo_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | event_builder_fifo_xpm_counter_updn__parameterized2 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | event_builder_fifo_xpm_fifo_reg_bit | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | event_builder_fifo_xpm_counter_updn__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | event_builder_fifo_xpm_fifo_rst | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_fifo | event_builder_fifo_HD6573 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | inst | event_builder_fifo_axis_data_fifo_v2_0_8_top_HD6574 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | event_builder_fifo_xpm_fifo_axis_HD6575 | 106(0.03%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 123(0.02%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | event_builder_fifo_xpm_fifo_axis_HD6575 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | event_builder_fifo_xpm_cdc_sync_rst_HD6576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | event_builder_fifo_xpm_fifo_base_HD6577 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 85(0.01%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_base_inst) | event_builder_fifo_xpm_fifo_base_HD6577 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized1_HD6578 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | event_builder_fifo_xpm_memory_base_HD6579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.34%) | 0(0.00%) | 0(0.00%) | | rdp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_HD6580 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_HD6581 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | event_builder_fifo_xpm_fifo_reg_bit_HD6582 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | event_builder_fifo_xpm_counter_updn__parameterized2_0_HD6583 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | event_builder_fifo_xpm_counter_updn__parameterized3_1_HD6584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | event_builder_fifo_xpm_counter_updn__parameterized0_HD6585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | event_builder_fifo_xpm_fifo_rst_HD6586 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_header_crc | event_hdr_crc9__5 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (event_header_crc) | event_hdr_crc9__5 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | hdr_chk_crc | osum_crc9d32 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | event_trailer_crc | event_trailer_CRC20__5 | 373(0.11%) | 373(0.11%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_block | flx_CRC | 373(0.11%) | 373(0.11%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | evnt_trailer_err_map | trailer_map__4 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_reg | vDFF | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | timeout | tob_timeout | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wdog_timer | watchdog | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_reg.status_regs | tob_proc_regs | 1713(0.49%) | 1713(0.49%) | 0(0.00%) | 0(0.00%) | 3442(0.50%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | (gen_reg.status_regs) | tob_proc_regs | 766(0.22%) | 766(0.22%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_capt | l1id_capture | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 426(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (l1id_capt) | l1id_capture | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.L1ID_Capture_Control_reg | ipbus_reg_v_173 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.L1ID_Capture_status_reg | ipbus_syncreg_v_174 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.L1ID_Capture_status_reg) | ipbus_syncreg_v_174 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_183 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_miss_reg | ipbus_syncreg_v_175 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_miss_reg) | ipbus_syncreg_v_175 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_182 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_last_reg | ipbus_syncreg_v_176 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_last_reg) | ipbus_syncreg_v_176 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_181 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_miss_reg | ipbus_syncreg_v_177 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_miss_reg) | ipbus_syncreg_v_177 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_180 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.ttc_penultimate_reg | ipbus_syncreg_v_178 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.ttc_penultimate_reg) | ipbus_syncreg_v_178 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_179 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Event_fifo_control_reg | ipbus_reg_v | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Event_fifo_reset_reg | ipbus_reg_v_73 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Full_mode_control_reg | ipbus_reg_v_74 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_busy_Count_reg | ipbus_syncreg_v | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_busy_Count_reg) | ipbus_syncreg_v | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_fifo_status_reg | ipbus_syncreg_v_75 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_fifo_status_reg) | ipbus_syncreg_v_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_171 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_stage_xoff_Count_reg | ipbus_syncreg_v_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Tob_stage_xoff_Count_reg) | ipbus_syncreg_v_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_staging_fifo_resets_reg | ipbus_reg_v_77 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Tob_timeout_reg | ipbus_ctrlreg_v__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.avg_event_time_reg | ipbus_syncreg_v_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.avg_event_time_reg) | ipbus_syncreg_v_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.bcn_mismatch_map_reg | ipbus_syncreg_v_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.bcn_mismatch_map_reg) | ipbus_syncreg_v_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.chan_error_mapper | chan_err_map | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.crc20_error_map_reg | ipbus_syncreg_v_80 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.crc20_error_map_reg) | ipbus_syncreg_v_80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_167 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.crc9_error_map_reg | ipbus_syncreg_v_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.crc9_error_map_reg) | ipbus_syncreg_v_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.dbg_pkt_count_reg | ipbus_syncreg_v_82 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.dbg_pkt_count_reg) | ipbus_syncreg_v_82 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.debug_fifo_fill_level_reg | ipbus_syncreg_v_83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.debug_fifo_fill_level_reg) | ipbus_syncreg_v_83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.debug_fifo_watermark | watermark | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.error_count_register | ipbus_syncreg_v_84 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.error_count_register) | ipbus_syncreg_v_84 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_fifo_fill_level_reg | ipbus_syncreg_v_85 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.event_fifo_fill_level_reg) | ipbus_syncreg_v_85 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_fifo_watermark | watermark_86 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_proc_timer | event_timer | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.event_time_reg | ipbus_syncreg_v_87 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.event_time_reg) | ipbus_syncreg_v_87 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.flx_bp_time_reg | ipbus_syncreg_v_88 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.flx_bp_time_reg) | ipbus_syncreg_v_88 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fm_L1id_reg | ipbus_syncreg_v_89 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.fm_L1id_reg) | ipbus_syncreg_v_89 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_159 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fm_fifo_watermark | watermark_90 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.full_mode_status_reg | ipbus_syncreg_v_91 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.full_mode_status_reg) | ipbus_syncreg_v_91 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.fullmode_fifo_fill_level_reg | ipbus_syncreg_v_92 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.fullmode_fifo_fill_level_reg) | ipbus_syncreg_v_92 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_157 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.input_capture | input_capture_regs | 314(0.09%) | 314(0.09%) | 0(0.00%) | 0(0.00%) | 650(0.09%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | Capture_Control_reg | ipbus_reg_v_140 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Capture_status_reg | ipbus_syncreg_v_141 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Capture_status_reg) | ipbus_syncreg_v_141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_156 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Header_0_reg | ipbus_syncreg_v_142 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Header_0_reg) | ipbus_syncreg_v_142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_155 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Header_1_reg | ipbus_syncreg_v_143 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Header_1_reg) | ipbus_syncreg_v_143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_154 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Input_channel_select_reg | ipbus_reg_v_144 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | capture_lsw | ipbus_dpram | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | capture_msw | ipbus_dpram_145 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | input_capture_mech | input_capture | 141(0.04%) | 141(0.04%) | 0(0.00%) | 0(0.00%) | 350(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (input_capture_mech) | input_capture | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 177(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_checker | packet_crc | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (crc_checker) | packet_crc | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | header_crc | CRC__parameterized1_152 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | payload_crc | CRC_153 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pkt_count_reg | ipbus_syncreg_v_146 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (pkt_count_reg) | ipbus_syncreg_v_146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_151 | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trailer_0_reg | ipbus_syncreg_v_147 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trailer_0_reg) | ipbus_syncreg_v_147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_150 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trailer_1_reg | ipbus_syncreg_v_148 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trailer_1_reg) | ipbus_syncreg_v_148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_149 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.l1id_mismatch_map_reg | ipbus_syncreg_v_93 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.l1id_mismatch_map_reg) | ipbus_syncreg_v_93 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_139 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.max_timeout_reg | ipbus_syncreg_v_94 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.max_timeout_reg) | ipbus_syncreg_v_94 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.packet_capture | pkt_capture_regs | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 506(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.packet_capture) | pkt_capture_regs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_Control_reg | ipbus_reg_v_123 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Capture_status_reg | ipbus_syncreg_v_124 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Capture_status_reg) | ipbus_syncreg_v_124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_137 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_0_reg | ipbus_syncreg_v_125 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_0_reg) | ipbus_syncreg_v_125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_136 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_1_reg | ipbus_syncreg_v_126 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_1_reg) | ipbus_syncreg_v_126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_135 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.Header_2_reg | ipbus_syncreg_v_127 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.Header_2_reg) | ipbus_syncreg_v_127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_134 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_count_reg | ipbus_syncreg_v_128 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_count_reg) | ipbus_syncreg_v_128 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_133 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_0_reg | ipbus_syncreg_v_129 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_0_reg) | ipbus_syncreg_v_129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_132 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trailer_1_reg | ipbus_syncreg_v_130 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.trailer_1_reg) | ipbus_syncreg_v_130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_131 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_max_wait_time_L1id_reg | ipbus_syncreg_v_95 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_max_wait_time_L1id_reg) | ipbus_syncreg_v_95 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_wait_time_last_reg | ipbus_syncreg_v_96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_wait_time_last_reg) | ipbus_syncreg_v_96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.pkt_wait_time_max_reg | ipbus_syncreg_v_97 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.pkt_wait_time_max_reg) | ipbus_syncreg_v_97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_120 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.stage_fifo_fill_level_reg | ipbus_syncreg_v_98 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.stage_fifo_fill_level_reg) | ipbus_syncreg_v_98 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_119 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.stage_fifo_watermark | watermark_99 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.timeout_error_map_reg | ipbus_syncreg_v_100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.timeout_error_map_reg) | ipbus_syncreg_v_100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_proc_reset_reg | ipbus_reg_v_101 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_proc_status | ipbus_syncreg_v_102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.tob_proc_status) | ipbus_syncreg_v_102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_staging_control_reg | ipbus_reg_v_103 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.tob_staging_thresholds_reg | ipbus_reg_v_104 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.trace_module | Processor_trace_module | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 144(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | Trace_Control_reg | ipbus_reg_v_109 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Trigger_pattern_reg | ipbus_reg_v_110 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | controller | proc_trace | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trace_mem | ipbus_dpram__parameterized2 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | trace_words_reg | ipbus_syncreg_v_111 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trace_words_reg) | ipbus_syncreg_v_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_116 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trigger_pointer_reg | ipbus_syncreg_v_112 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trigger_pointer_reg) | ipbus_syncreg_v_112 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_115 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trigger_status_reg | ipbus_syncreg_v_113 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trigger_status_reg) | ipbus_syncreg_v_113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_114 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.watchdog_control_reg | ipbus_reg_v_105 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.watchdog_overflow_count_reg | ipbus_syncreg_v_106 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (no_sim_regs.watchdog_overflow_count_reg) | ipbus_syncreg_v_106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.wdog_overflow_counter | edge_error_counter__parameterized1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_sim_regs.wdog_threshold_reg | ipbus_ctrlreg_v__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_busy_counter | threshold_counter | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_busy_flag | threshold_counter__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_xoff_counter | threshold_counter_107 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_stage_xoff_flag | threshold_counter__parameterized0_108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | input_mux | channel_mux | 555(0.16%) | 555(0.16%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_input | ttc_info_p2 | 7021(2.03%) | 4259(1.23%) | 1968(1.13%) | 794(0.46%) | 8110(1.17%) | 14(1.19%) | 1(0.04%) | 0(0.00%) | | (ttc_input) | ttc_info_p2 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 131(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bulk_ttc_fifo | ttc_header_fifo | 840(0.24%) | 200(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ttc_header_fifo_fifo_generator_v13_2_7 | 840(0.24%) | 200(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | ttc_header_fifo_fifo_generator_v13_2_7_synth | 840(0.24%) | 200(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | ttc_header_fifo_fifo_generator_top | 840(0.24%) | 200(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | ttc_header_fifo_fifo_generator_ramfifo | 840(0.24%) | 200(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | ttc_header_fifo_clk_x_pntrs | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | ttc_header_fifo_clk_x_pntrs | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | ttc_header_fifo_rd_logic | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | ttc_header_fifo_rd_fwft | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | ttc_header_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | ttc_header_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | ttc_header_fifo_compare_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | ttc_header_fifo_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | ttc_header_fifo_wr_logic | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | ttc_header_fifo_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | ttc_header_fifo_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | ttc_header_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | ttc_header_fifo_compare_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | ttc_header_fifo_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | ttc_header_fifo_memory | 760(0.22%) | 120(0.03%) | 640(0.37%) | 0(0.00%) | 120(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | ttc_header_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | ttc_header_fifo_dmem | 760(0.22%) | 120(0.03%) | 640(0.37%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | ttc_header_fifo_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | ttc_header_fifo_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | ttc_header_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | ttc_header_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cttc_crc | osum_crc9d32__14 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_ttc_fifo_in | ila_ttc_in | 1669(0.48%) | 1313(0.38%) | 0(0.00%) | 356(0.20%) | 2755(0.40%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | (ila_ttc_fifo_in) | ila_ttc_in | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ttc_in_ila_v6_2_12_ila | 1669(0.48%) | 1313(0.38%) | 0(0.00%) | 356(0.20%) | 2755(0.40%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_ttc_in_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ttc_in_ila_v6_2_12_ila_core | 1668(0.48%) | 1312(0.38%) | 0(0.00%) | 356(0.20%) | 2749(0.40%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_ttc_in_ila_v6_2_12_ila_core | 124(0.04%) | 0(0.00%) | 0(0.00%) | 124(0.07%) | 288(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ttc_in_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ttc_in_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_ttc_in_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_in_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ttc_in_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ttc_in_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ttc_in_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ttc_in_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ttc_in_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ttc_in_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ttc_in_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ttc_in_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ttc_in_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ttc_in_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ttc_in_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ttc_in_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ttc_in_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ttc_in_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_83 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_84 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_84 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized1_85 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized2_86 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ttc_in_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ttc_in_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ttc_in_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ttc_in_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ttc_in_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ttc_in_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ttc_in_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_79 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA_nodelay_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_80 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized3_80 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized1_81 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized2_82 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ttc_in_ila_v6_2_12_ila_register | 1056(0.30%) | 1055(0.30%) | 0(0.00%) | 1(0.01%) | 1486(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ttc_in_ila_v6_2_12_ila_register | 351(0.10%) | 350(0.10%) | 0(0.00%) | 1(0.01%) | 166(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[15].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[16].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized16 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ttc_in_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_75 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_74 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_73 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_72 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized1_70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_78 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized1_69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ttc_in_xsdbs_v1_0_2_reg__parameterized46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ttc_in_xsdbs_v1_0_2_reg_p2s__parameterized17 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ttc_in_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_in_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ttc_in_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_ttc_in_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_in_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ttc_in_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ttc_in_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ttc_in_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ttc_in_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ttc_in_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ttc_in_ila_v6_2_12_ila_trigger | 306(0.09%) | 124(0.04%) | 0(0.00%) | 182(0.10%) | 544(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ttc_in_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ttc_in_ltlib_v1_0_0_match | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ttc_in_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA_58 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA_58 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_59 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_60 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_61 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ttc_in_ila_v6_2_12_ila_trig_match | 292(0.08%) | 123(0.04%) | 0(0.00%) | 169(0.10%) | 524(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_ttc_in_ila_v6_2_12_ila_trig_match | 123(0.04%) | 123(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_56 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_56 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_57 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_15 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_16 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_18 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_19 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized7__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized7__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7_4 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized7 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[15].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[15].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[16].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[16].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_53 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_54 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_54 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_55 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_50 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized1_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_51 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_51 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_52 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_44 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_44 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_42 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized0_42 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized5 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_39 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized1_39 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_33 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_34 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_34 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_27 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_28 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_ttc_in_ltlib_v1_0_0_match__parameterized6__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_21 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_in_ltlib_v1_0_0_allx_typeA__parameterized6_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_22 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_in_ltlib_v1_0_0_all_typeA__parameterized2_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_in_ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ttc_in_ltlib_v1_0_0_generic_memrd | 95(0.03%) | 93(0.03%) | 0(0.00%) | 2(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_ttc_fifo_out | ila_ttc_out | 1024(0.30%) | 857(0.25%) | 0(0.00%) | 167(0.10%) | 1675(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_ttc_fifo_out) | ila_ttc_out | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ttc_out_ila_v6_2_12_ila | 1024(0.30%) | 857(0.25%) | 0(0.00%) | 167(0.10%) | 1675(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_ttc_out_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ttc_out_ila_v6_2_12_ila_core | 1023(0.30%) | 856(0.25%) | 0(0.00%) | 167(0.10%) | 1669(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_ttc_out_ila_v6_2_12_ila_core | 40(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.02%) | 123(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ttc_out_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ttc_out_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_ttc_out_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ttc_out_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ttc_out_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ttc_out_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ttc_out_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ttc_out_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ttc_out_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ttc_out_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ttc_out_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ttc_out_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ttc_out_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ttc_out_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ttc_out_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ttc_out_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ttc_out_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ttc_out_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_46 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_47 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_47 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized1_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized2_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ttc_out_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ttc_out_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ttc_out_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ttc_out_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ttc_out_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ttc_out_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ttc_out_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_42 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA_nodelay_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_43 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized2_43 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized1_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized2_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ttc_out_ila_v6_2_12_ila_register | 714(0.21%) | 713(0.21%) | 0(0.00%) | 1(0.01%) | 1094(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ttc_out_ila_v6_2_12_ila_register | 284(0.08%) | 283(0.08%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ttc_out_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized1_33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized1_32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl_28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized53 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ttc_out_xsdbs_v1_0_2_reg__parameterized28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ttc_out_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ttc_out_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ttc_out_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ttc_out_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_ttc_out_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ttc_out_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ttc_out_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ttc_out_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ttc_out_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ttc_out_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ttc_out_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ttc_out_ila_v6_2_12_ila_trigger | 118(0.03%) | 41(0.01%) | 0(0.00%) | 77(0.04%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ttc_out_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ttc_out_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ttc_out_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_23 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ttc_out_ila_v6_2_12_ila_trig_match | 112(0.03%) | 40(0.01%) | 0(0.00%) | 72(0.04%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_ttc_out_ila_v6_2_12_ila_trig_match | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized0 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA_8 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_9 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized3 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized3 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized1 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ttc_out_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ttc_out_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ttc_out_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ttc_out_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ttc_out_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ttc_out_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ttc_out_ltlib_v1_0_0_generic_memrd | 64(0.02%) | 62(0.02%) | 0(0.00%) | 2(0.01%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_continuity_checker | l1id_cont_check | 1618(0.47%) | 1347(0.39%) | 0(0.00%) | 271(0.16%) | 2623(0.38%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (l1id_continuity_checker) | l1id_cont_check | 141(0.04%) | 141(0.04%) | 0(0.00%) | 0(0.00%) | 268(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_l1id_cont_check | ila_l1id_cont | 1477(0.43%) | 1206(0.35%) | 0(0.00%) | 271(0.16%) | 2355(0.34%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_l1id_cont_check) | ila_l1id_cont | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_l1id_cont_ila_v6_2_12_ila | 1477(0.43%) | 1206(0.35%) | 0(0.00%) | 271(0.16%) | 2355(0.34%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_l1id_cont_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_l1id_cont_ila_v6_2_12_ila_core | 1476(0.43%) | 1205(0.35%) | 0(0.00%) | 271(0.16%) | 2349(0.34%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_l1id_cont_ila_v6_2_12_ila_core | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_l1id_cont_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_l1id_cont_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_l1id_cont_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_l1id_cont_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_l1id_cont_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_l1id_cont_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_l1id_cont_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_l1id_cont_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_l1id_cont_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_l1id_cont_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_l1id_cont_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_l1id_cont_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_l1id_cont_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_l1id_cont_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_l1id_cont_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_l1id_cont_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_l1id_cont_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_l1id_cont_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_71 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_72 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_72 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized1_73 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized2_74 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_l1id_cont_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_l1id_cont_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_l1id_cont_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_l1id_cont_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_l1id_cont_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_l1id_cont_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_l1id_cont_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_67 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA_nodelay_67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_68 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized3_68 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized1_69 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized2_70 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_l1id_cont_ila_v6_2_12_ila_register | 990(0.29%) | 989(0.29%) | 0(0.00%) | 1(0.01%) | 1396(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_l1id_cont_ila_v6_2_12_ila_register | 346(0.10%) | 345(0.10%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized10 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized11 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[13].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized12 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[14].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized13 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized14 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_l1id_cont_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized1_58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized1_57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized63 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized64 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl_53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_52 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_l1id_cont_xsdbs_v1_0_2_reg__parameterized42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat_64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_l1id_cont_xsdbs_v1_0_2_reg_p2s__parameterized15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_l1id_cont_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_l1id_cont_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_l1id_cont_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_l1id_cont_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_l1id_cont_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_l1id_cont_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_l1id_cont_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_l1id_cont_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_l1id_cont_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_l1id_cont_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_l1id_cont_ila_v6_2_12_ila_trigger | 222(0.06%) | 86(0.02%) | 0(0.00%) | 136(0.08%) | 386(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_l1id_cont_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_l1id_cont_ltlib_v1_0_0_match | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_l1id_cont_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_l1id_cont_ila_v6_2_12_ila_trig_match | 212(0.06%) | 85(0.02%) | 0(0.00%) | 127(0.07%) | 368(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_l1id_cont_ila_v6_2_12_ila_trig_match | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_46 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_46 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__1 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_8 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_9 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_12 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[13].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[13].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_3 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2_3 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[14].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[14].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_43 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_44 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_44 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_40 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_41 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_37 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_38 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_38 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_34 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_35 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_35 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_32 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2__1 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized2__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1_22 | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized1_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_25 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_l1id_cont_ltlib_v1_0_0_match__parameterized3__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_l1id_cont_ltlib_v1_0_0_allx_typeA__parameterized3_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_l1id_cont_ltlib_v1_0_0_all_typeA__parameterized0_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_l1id_cont_ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_l1id_cont_ltlib_v1_0_0_generic_memrd | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_0 | ttc_header_fifo_HD6617 | 904(0.26%) | 216(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ttc_header_fifo_fifo_generator_v13_2_7_HD6618 | 904(0.26%) | 216(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | ttc_header_fifo_fifo_generator_v13_2_7_synth_HD6619 | 904(0.26%) | 216(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | ttc_header_fifo_fifo_generator_top_HD6620 | 904(0.26%) | 216(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | ttc_header_fifo_fifo_generator_ramfifo_HD6621 | 904(0.26%) | 216(0.06%) | 688(0.39%) | 0(0.00%) | 317(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | ttc_header_fifo_clk_x_pntrs_HD6622 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | ttc_header_fifo_clk_x_pntrs_HD6622 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray_HD6623 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray__2_HD6624 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | ttc_header_fifo_rd_logic_HD6625 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | ttc_header_fifo_rd_fwft_HD6626 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | ttc_header_fifo_rd_dc_as_HD6627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | ttc_header_fifo_rd_status_flags_as_HD6628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | ttc_header_fifo_rd_status_flags_as_HD6628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | ttc_header_fifo_compare_2_HD6629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_3_HD6630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | ttc_header_fifo_rd_bin_cntr_HD6632 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | ttc_header_fifo_wr_logic_HD6633 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | ttc_header_fifo_wr_status_flags_as_HD6634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | ttc_header_fifo_wr_status_flags_as_HD6634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_HD6635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | ttc_header_fifo_compare_0_HD6636 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | ttc_header_fifo_compare_1_HD6637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | ttc_header_fifo_wr_bin_cntr_HD6638 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | ttc_header_fifo_memory_HD6639 | 816(0.24%) | 128(0.04%) | 688(0.39%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | ttc_header_fifo_memory_HD6639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | ttc_header_fifo_dmem_HD6640 | 816(0.24%) | 128(0.04%) | 688(0.39%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | ttc_header_fifo_reset_blk_ramfifo_HD6641 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | ttc_header_fifo_reset_blk_ramfifo_HD6641 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst_HD6642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | ttc_header_fifo_xpm_cdc_single_HD6643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | ttc_header_fifo_xpm_cdc_single__2_HD6644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst__1_HD6645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_1 | ttc_header_fifo_HD6646 | 839(0.24%) | 199(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ttc_header_fifo_fifo_generator_v13_2_7_HD6647 | 839(0.24%) | 199(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | ttc_header_fifo_fifo_generator_v13_2_7_synth_HD6648 | 839(0.24%) | 199(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | ttc_header_fifo_fifo_generator_top_HD6649 | 839(0.24%) | 199(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | ttc_header_fifo_fifo_generator_ramfifo_HD6650 | 839(0.24%) | 199(0.06%) | 640(0.37%) | 0(0.00%) | 300(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | ttc_header_fifo_clk_x_pntrs_HD6651 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | ttc_header_fifo_clk_x_pntrs_HD6651 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray_HD6652 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | ttc_header_fifo_xpm_cdc_gray__2_HD6653 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | ttc_header_fifo_rd_logic_HD6654 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | ttc_header_fifo_rd_fwft_HD6655 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | ttc_header_fifo_rd_status_flags_as_HD6657 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | ttc_header_fifo_rd_status_flags_as_HD6657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | ttc_header_fifo_compare_2_HD6658 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_3_HD6659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | ttc_header_fifo_rd_bin_cntr_HD6661 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | ttc_header_fifo_wr_logic_HD6662 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | ttc_header_fifo_wr_status_flags_as_HD6663 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | ttc_header_fifo_wr_status_flags_as_HD6663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | ttc_header_fifo_compare_HD6664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | ttc_header_fifo_compare_0_HD6665 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | ttc_header_fifo_compare_1_HD6666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | ttc_header_fifo_wr_bin_cntr_HD6667 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | ttc_header_fifo_memory_HD6668 | 760(0.22%) | 120(0.03%) | 640(0.37%) | 0(0.00%) | 120(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | ttc_header_fifo_memory_HD6668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | ttc_header_fifo_dmem_HD6669 | 760(0.22%) | 120(0.03%) | 640(0.37%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | ttc_header_fifo_reset_blk_ramfifo_HD6670 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | ttc_header_fifo_reset_blk_ramfifo_HD6670 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst_HD6671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | ttc_header_fifo_xpm_cdc_single_HD6672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | ttc_header_fifo_xpm_cdc_single__2_HD6673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | ttc_header_fifo_xpm_cdc_async_rst__1_HD6674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fm_interface_1 | Full_Mode_Tx__xdcDup__1 | 4805(1.39%) | 4285(1.24%) | 64(0.04%) | 456(0.26%) | 7379(1.07%) | 4(0.34%) | 5(0.21%) | 0(0.00%) | | (fm_interface_1) | Full_Mode_Tx__xdcDup__1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_stretcher | pulse_stretch__parameterized7_40 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_0 | FM_channel__xdcDup__1 | 1814(0.52%) | 1607(0.46%) | 32(0.02%) | 175(0.10%) | 2787(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_0) | FM_channel__xdcDup__1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD1595 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD1596 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD1597 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD1598 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD1599 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD1600 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD1600 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD1601 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD1602 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD1603 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD1605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD1606 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD1607 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD1608 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD1609 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory_HD1610 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem_HD1611 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD1612 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD1612 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD1613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD1614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD1615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD1616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi_68 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux_69 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD2166 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD2166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD2167 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD2167 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD2168 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD2168 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD2169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD2170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD2171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD2172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD2173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD2174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD2175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD2176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD2177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2178 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2178 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD2179 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD2180 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD2181 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2182 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2182 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD2183 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2184 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2184 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD2185 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD2186 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD2187 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD2188 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2189 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2190 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2190 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD2191 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD2192 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2193 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2193 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD2194 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD2195 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD2196 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD2197 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2198 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2199 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2199 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD2200 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD2201 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD2202 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2203 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2204 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2204 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD2205 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD2206 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD2207 | 914(0.26%) | 913(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD2207 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD2208 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD2209 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD2210 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD2211 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD2212 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD2213 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD2214 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD2215 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD2216 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD2217 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD2218 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD2219 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD2220 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD2221 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD2222 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD2223 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD2224 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD2225 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD2226 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD2227 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD2228 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD2229 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD2230 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD2231 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD2232 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD2233 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD2234 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD2235 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD2236 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD2237 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD2238 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD2239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD2240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD2241 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD2242 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD2243 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD2244 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD2245 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD2246 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD2247 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD2248 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD2249 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD2250 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD2251 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD2252 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD2253 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD2254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD2255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD2256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD2258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD2259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD2260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD2261 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD2262 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD2263 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2264 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2264 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD2265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2266 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2266 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD2267 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD2268 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD2269 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD2270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD2271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD2272 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD2273 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD2273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD2274 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD2274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2275 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2276 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2276 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD2277 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD2278 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD2279 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD2279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2280 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2281 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2281 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD2282 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD2283 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2284 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2284 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2285 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2286 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2287 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2287 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD2288 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD2289 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD2290 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD2291 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2292 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2293 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2294 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2294 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD2295 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2296 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2297 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2298 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2298 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD2299 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2300 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2301 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2302 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2302 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD2303 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD2304 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD2305 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD2306 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2307 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2308 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2309 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2309 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD2310 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2311 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2312 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2313 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2313 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD2314 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2315 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2316 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2317 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2317 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD2318 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2319 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2320 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2321 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2321 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD2322 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2323 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2324 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2325 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2325 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD2326 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2327 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2328 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2329 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2329 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD2330 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2331 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2332 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2333 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2333 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD2334 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2335 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2336 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2337 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2337 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD2338 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD2339 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__1 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__1 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl | 170(0.05%) | 170(0.05%) | 0(0.00%) | 0(0.00%) | 168(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_70 | 153(0.04%) | 153(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_72 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__1 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2698 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2699 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2700 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2701 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2702 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2703 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2703 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2704 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2705 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2706 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2708 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2709 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2710 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as_HD2711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2712 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2713 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2714 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2715 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2716 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2717 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2718 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2719 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2719 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2720 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2721 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2721 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2549 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2550 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2551 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2552 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2553 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2553 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2554 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2555 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2557 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2558 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_1 | FM_channel__xdcDup__2 | 1820(0.53%) | 1613(0.47%) | 32(0.02%) | 175(0.10%) | 2793(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_1) | FM_channel__xdcDup__2 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD1617 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD1618 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD1619 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD1620 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD1621 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD1622 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD1622 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD1623 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD1624 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD1625 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD1627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD1628 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD1629 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD1630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD1631 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory_HD1632 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem_HD1633 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD1634 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD1634 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD1635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD1636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD1637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD1638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi_61 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__10 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux_62 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD2340 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD2340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD2341 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD2341 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD2342 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD2342 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD2343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD2344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD2345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD2346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD2347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD2348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD2349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD2350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD2351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2352 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2352 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD2353 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD2354 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD2355 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2356 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2356 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD2357 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2358 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2358 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD2359 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD2360 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD2361 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD2362 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2363 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2364 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2364 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD2365 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD2366 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2367 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2367 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD2368 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD2369 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD2370 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD2371 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2372 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2373 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2373 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD2374 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD2375 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD2376 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2377 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2378 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2378 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD2379 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD2380 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD2381 | 914(0.26%) | 913(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD2381 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD2382 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD2383 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD2384 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD2385 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD2386 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD2387 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD2388 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD2389 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD2390 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD2391 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD2392 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD2393 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD2394 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD2395 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD2396 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD2397 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD2398 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD2399 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD2400 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD2401 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD2402 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD2403 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD2404 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD2405 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD2406 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD2407 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD2408 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD2409 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD2410 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD2411 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD2412 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD2413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD2414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD2415 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD2416 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD2417 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD2418 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD2419 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD2420 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD2421 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD2422 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD2423 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD2424 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD2425 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD2426 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD2427 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD2428 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD2429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD2430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD2432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD2433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD2435 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD2436 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD2437 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2438 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2438 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD2439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2440 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2440 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD2441 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD2442 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD2443 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD2444 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD2445 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD2446 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD2447 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD2447 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD2448 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD2448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2449 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2450 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2450 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD2451 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD2452 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD2453 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD2453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2454 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2455 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2455 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD2456 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD2457 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2458 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2458 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2459 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2460 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2461 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2461 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD2462 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD2463 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD2464 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD2465 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2466 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2467 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2468 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2468 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD2469 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2470 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2471 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2472 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2472 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD2473 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2474 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2475 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2476 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2476 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD2477 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD2478 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD2479 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD2480 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2481 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2482 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2483 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2483 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD2484 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2485 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2486 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2487 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2487 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD2488 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2489 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2490 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2491 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2491 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD2492 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2493 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2494 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2495 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2495 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD2496 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2497 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2498 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2499 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2499 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD2500 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2501 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2502 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2503 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2503 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD2504 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2505 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2506 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2507 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2507 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD2508 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2509 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2510 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2511 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2511 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD2512 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD2513 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__2 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__2 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__10 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__10 | 176(0.05%) | 176(0.05%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__10 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_63 | 152(0.04%) | 152(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eob_space_trig | pulse_pdxx_pwxx_64 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sob_space_trig | pulse_pdxx_pwxx_66 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_67 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__2 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2726 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2727 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2728 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2729 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2730 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2731 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2731 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2732 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2733 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2734 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2736 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2737 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2738 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as_HD2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2740 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2741 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2742 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2743 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2744 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2745 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2746 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2747 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2747 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2748 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2749 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2749 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2559 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2560 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2561 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2562 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2563 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2563 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2564 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2565 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2566 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2567 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2568 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_blk | clk_wiz_240_HD1080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_240_clk_wiz_HD1081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u0 | FullModeTransceiver__xdcDup__1 | 1166(0.34%) | 1060(0.31%) | 0(0.00%) | 106(0.06%) | 1793(0.26%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (u0) | FullModeTransceiver__xdcDup__1 | 40(0.01%) | 33(0.01%) | 0(0.00%) | 7(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | g_gt_channel[0].rxresetfsm_i | FullModeTransceiver_RX_STARTUP_FSM__4 | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (g_gt_channel[0].rxresetfsm_i) | FullModeTransceiver_RX_STARTUP_FSM__4 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullModeTransceiver_sync_block_54 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullModeTransceiver_sync_block_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullModeTransceiver_sync_block_56 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_57 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullModeTransceiver_sync_block_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | g_gt_channel[1].rxresetfsm_i | FullModeTransceiver_RX_STARTUP_FSM | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (g_gt_channel[1].rxresetfsm_i) | FullModeTransceiver_RX_STARTUP_FSM | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullModeTransceiver_sync_block_47 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullModeTransceiver_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullModeTransceiver_sync_block_49 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_50 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullModeTransceiver_sync_block_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_resetfsm | ila_mgtfsm_HD6676 | 876(0.25%) | 777(0.22%) | 0(0.00%) | 99(0.06%) | 1358(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_resetfsm) | ila_mgtfsm_HD6676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_mgtfsm_ila_v6_2_12_ila_HD6677 | 876(0.25%) | 777(0.22%) | 0(0.00%) | 99(0.06%) | 1358(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_mgtfsm_ila_v6_2_12_ila_HD6677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_mgtfsm_ila_v6_2_12_ila_core_HD6678 | 875(0.25%) | 776(0.22%) | 0(0.00%) | 99(0.06%) | 1352(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_mgtfsm_ila_v6_2_12_ila_core_HD6678 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_mgtfsm_ila_v6_2_12_ila_trace_memory_HD6679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_mgtfsm_blk_mem_gen_v8_4_5_HD6680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_mgtfsm_blk_mem_gen_v8_4_5_synth_HD6681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD6682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD6683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD6684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD6685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | u_ila_cap_ctrl | ila_mgtfsm_ila_v6_2_12_ila_cap_ctrl_legacy_HD6686 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_mgtfsm_ila_v6_2_12_ila_cap_ctrl_legacy_HD6686 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_mgtfsm_ltlib_v1_0_0_cfglut6__parameterized0_HD6687 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_mgtfsm_ltlib_v1_0_0_cfglut7_HD6688 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_mgtfsm_ltlib_v1_0_0_cfglut7__1_HD6689 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_mgtfsm_ila_v6_2_12_ila_cap_addrgen_HD6690 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_mgtfsm_ila_v6_2_12_ila_cap_addrgen_HD6690 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_mgtfsm_ltlib_v1_0_0_cfglut6__1_HD6691 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_mgtfsm_ila_v6_2_12_ila_cap_sample_counter_HD6692 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_mgtfsm_ila_v6_2_12_ila_cap_sample_counter_HD6692 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_mgtfsm_ltlib_v1_0_0_cfglut4__1_HD6693 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5__1_HD6694 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_mgtfsm_ltlib_v1_0_0_cfglut6_HD6695 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay__1_HD6696 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_44_HD6697 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_44_HD6697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_45_HD6698 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_45_HD6698 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD6699 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1_47_HD6700 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_mgtfsm_ila_v6_2_12_ila_cap_window_counter_HD6701 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_mgtfsm_ila_v6_2_12_ila_cap_window_counter_HD6701 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_mgtfsm_ltlib_v1_0_0_cfglut4_HD6702 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5_HD6703 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5__2_HD6704 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay_HD6705 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_HD6706 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_HD6706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_HD6707 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_HD6707 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD6708 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD6709 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay__2_HD6710 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_40_HD6711 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_40_HD6711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_41_HD6712 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_41_HD6712 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0_42_HD6713 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1_43_HD6714 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_mgtfsm_ila_v6_2_12_ila_register_HD6715 | 708(0.20%) | 707(0.20%) | 0(0.00%) | 1(0.01%) | 1085(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_mgtfsm_ila_v6_2_12_ila_register_HD6715 | 278(0.08%) | 277(0.08%) | 0(0.00%) | 1(0.01%) | 159(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s_HD6716 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized0_HD6717 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized1_HD6718 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized2_HD6719 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized3_HD6720 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized4_HD6721 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized5_HD6722 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized6_HD6723 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized7_HD6724 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_mgtfsm_xsdbs_v1_0_2_xsdbs_HD6725 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized40_HD6726 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_36_HD6727 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized41_HD6728 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_35_HD6729 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized42_HD6730 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_34_HD6731 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized43_HD6732 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_33_HD6733 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized44_HD6734 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_32_HD6735 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized45_HD6736 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1_31_HD6737 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized25_HD6738 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_39_HD6739 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized26_HD6740 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized0_HD6741 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized27_HD6742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_38_HD6743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized46_HD6744 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1_30_HD6745 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized47_HD6746 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_29_HD6747 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized48_HD6748 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1_HD6749 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized49_HD6750 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_28_HD6751 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized50_HD6752 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_27_HD6753 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized51_HD6754 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_26_HD6755 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized53_HD6756 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_25_HD6757 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized55_HD6758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_24_HD6759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized58_HD6760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized58_HD6760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_23_HD6761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized28_HD6762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_37_HD6763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized8_HD6764 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_mgtfsm_xsdbs_v1_0_2_reg_stream_HD6765 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_HD6766 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_mgtfsm_xsdbs_v1_0_2_reg_stream__parameterized0_HD6767 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_mgtfsm_xsdbs_v1_0_2_reg_stream__parameterized0_HD6767 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_HD6768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_mgtfsm_ila_v6_2_12_ila_reset_ctrl_HD6769 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_mgtfsm_ila_v6_2_12_ila_reset_ctrl_HD6769 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_mgtfsm_ltlib_v1_0_0_rising_edge_detection_HD6770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__2_HD6771 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__3_HD6772 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__1_HD6773 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer_HD6774 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_mgtfsm_ltlib_v1_0_0_rising_edge_detection__1_HD6775 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_mgtfsm_ila_v6_2_12_ila_trigger_HD6776 | 50(0.01%) | 5(0.01%) | 0(0.00%) | 45(0.03%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_mgtfsm_ila_v6_2_12_ila_trigger_HD6776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_mgtfsm_ltlib_v1_0_0_match_HD6777 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_mgtfsm_ltlib_v1_0_0_match_HD6777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_HD6778 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_HD6778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_21_HD6779 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_21_HD6779 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_22_HD6780 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_mgtfsm_ila_v6_2_12_ila_trig_match_HD6781 | 44(0.01%) | 4(0.01%) | 0(0.00%) | 40(0.02%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_mgtfsm_ila_v6_2_12_ila_trig_match_HD6781 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__1_HD6782 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__1_HD6782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_18_HD6783 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_18_HD6783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_19_HD6784 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_19_HD6784 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_20_HD6785 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__2_HD6786 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__2_HD6786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_15_HD6787 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_15_HD6787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_16_HD6788 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_16_HD6788 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_17_HD6789 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__3_HD6790 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__3_HD6790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_12_HD6791 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_12_HD6791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_13_HD6792 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_13_HD6792 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_14_HD6793 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__4_HD6794 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__4_HD6794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_9_HD6795 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_9_HD6795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_10_HD6796 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_10_HD6796 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_11_HD6797 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__5_HD6798 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__5_HD6798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_6_HD6799 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_6_HD6799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_7_HD6800 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_7_HD6800 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_8_HD6801 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__6_HD6802 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__6_HD6802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_3_HD6803 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_3_HD6803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_4_HD6804 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_4_HD6804 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_5_HD6805 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__7_HD6806 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__7_HD6806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_0_HD6807 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_0_HD6807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_1_HD6808 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_1_HD6808 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_2_HD6809 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0_HD6810 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0_HD6810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_HD6811 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_HD6811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_HD6812 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_HD6812 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_HD6813 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_mgtfsm_ltlib_v1_0_0_generic_memrd_HD6814 | 26(0.01%) | 24(0.01%) | 0(0.00%) | 2(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txresetfsm_i | FullModeTransceiver_TX_STARTUP_FSM | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txresetfsm_i) | FullModeTransceiver_TX_STARTUP_FSM | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | FullModeTransceiver_sync_block_41 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | FullModeTransceiver_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_43 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | FullModeTransceiver_sync_block_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fm_interface_tob1 | Full_Mode_Tx | 4747(1.37%) | 4259(1.23%) | 32(0.02%) | 456(0.26%) | 7292(1.05%) | 4(0.34%) | 5(0.21%) | 0(0.00%) | | (fm_interface_tob1) | Full_Mode_Tx | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_stretcher | pulse_stretch__parameterized7 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_0 | FM_channel__xdcDup__5 | 1814(0.52%) | 1607(0.46%) | 32(0.02%) | 175(0.10%) | 2787(0.40%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_0) | FM_channel__xdcDup__5 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD1573 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD1574 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD1575 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD1576 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD1577 | 69(0.02%) | 37(0.01%) | 32(0.02%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD1578 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD1578 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD1579 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD1580 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD1581 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD1583 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD1584 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD1585 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD1586 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD1587 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fm_status_fifo_memory_HD1588 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | fm_status_fifo_dmem_HD1589 | 32(0.01%) | 0(0.00%) | 32(0.02%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD1590 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD1590 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD1591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD1592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD1593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD1594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interface | fm_axi | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__7 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_mux | tx_data_mux | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD1992 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD1992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD1993 | 1192(0.34%) | 1020(0.29%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD1993 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD1994 | 1191(0.34%) | 1019(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD1994 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD1995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD1996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD1997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD2000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD2001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD2002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD2003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2004 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD2004 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD2005 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD2006 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD2007 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2008 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD2008 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD2009 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2010 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD2010 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD2011 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD2012 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD2013 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD2014 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2015 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD2015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2016 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD2016 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD2017 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD2018 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2019 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD2019 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD2020 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD2021 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD2022 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD2023 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2024 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD2024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2025 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD2025 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD2026 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD2027 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD2028 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2029 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD2029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2030 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD2030 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD2031 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD2032 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD2033 | 913(0.26%) | 912(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD2033 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD2034 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD2035 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD2036 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD2037 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD2038 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD2039 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD2040 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD2041 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD2042 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD2043 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD2044 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD2045 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD2046 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD2047 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD2048 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD2049 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD2050 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD2051 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD2052 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD2053 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD2054 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD2055 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD2056 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD2057 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD2058 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD2059 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD2060 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD2061 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD2062 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD2063 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD2064 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD2065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD2066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD2067 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD2068 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD2069 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD2070 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD2071 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD2072 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD2073 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD2074 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD2075 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD2076 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD2077 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD2078 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD2079 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD2080 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD2081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD2082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD2083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD2084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD2085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD2086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD2087 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD2088 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD2089 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2090 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD2090 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD2091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2092 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD2092 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD2093 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD2094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD2095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD2096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD2097 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD2098 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD2099 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD2099 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD2100 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD2100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2101 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD2101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2102 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD2102 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD2103 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD2104 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD2105 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD2105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2106 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD2106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2107 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD2107 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD2108 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD2109 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2110 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD2110 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2111 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD2111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2112 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD2112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2113 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD2113 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD2114 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD2115 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD2116 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD2117 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2118 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD2118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2119 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD2119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2120 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD2120 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD2121 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2122 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD2122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2123 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD2123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2124 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD2124 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD2125 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2126 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD2126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2127 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD2127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2128 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD2128 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD2129 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD2130 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD2131 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD2132 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2133 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD2133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2134 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD2134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2135 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD2135 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD2136 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2137 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD2137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2138 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD2138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2139 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD2139 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD2140 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2141 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD2141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2142 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD2142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2143 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD2143 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD2144 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2145 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD2145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2146 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD2146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2147 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD2147 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD2148 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2149 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD2149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2150 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD2150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2151 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD2151 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD2152 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2153 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD2153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2154 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD2154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2155 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD2155 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD2156 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2157 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD2157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2158 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD2158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2159 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD2159 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD2160 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2161 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD2161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2162 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD2162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2163 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD2163 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD2164 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD2165 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram__xdcDup__5 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram__xdcDup__5 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__7 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__7 | 170(0.05%) | 170(0.05%) | 0(0.00%) | 0(0.00%) | 168(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__7 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4_24 | 153(0.04%) | 153(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_26 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b__xdcDup__5 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2670 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2671 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2672 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2673 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2674 | 58(0.02%) | 55(0.02%) | 0(0.00%) | 3(0.01%) | 120(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2675 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2675 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2676 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2677 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2678 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2680 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2681 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2682 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | fifo1KB_34bit_wr_dc_as_HD2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2684 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2685 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2686 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2687 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2688 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2689 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2690 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2691 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2691 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2692 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2693 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2693 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2539 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2540 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2541 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2542 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2543 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2543 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2545 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2548 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chan_1 | FM_channel | 1767(0.51%) | 1592(0.46%) | 0(0.00%) | 175(0.10%) | 2706(0.39%) | 2(0.17%) | 2(0.08%) | 0(0.00%) | | (chan_1) | FM_channel | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1ID_fifo | fm_status_fifo_HD1551 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | fm_status_fifo_fifo_generator_v13_2_7_HD1552 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fm_status_fifo_fifo_generator_v13_2_7_synth_HD1553 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fm_status_fifo_fifo_generator_top_HD1554 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fm_status_fifo_fifo_generator_ramfifo_HD1555 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fm_status_fifo_clk_x_pntrs_HD1556 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fm_status_fifo_clk_x_pntrs_HD1556 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray_HD1557 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fm_status_fifo_xpm_cdc_gray__2_HD1558 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fm_status_fifo_rd_logic_HD1559 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fm_status_fifo_rd_status_flags_as_HD1561 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fm_status_fifo_rd_bin_cntr_HD1562 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fm_status_fifo_wr_logic_HD1563 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fm_status_fifo_wr_status_flags_as_HD1564 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fm_status_fifo_wr_bin_cntr_HD1565 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | fm_status_fifo_reset_blk_ramfifo_HD1568 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fm_status_fifo_reset_blk_ramfifo_HD1568 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | fm_status_fifo_xpm_cdc_async_rst_HD1569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fm_status_fifo_xpm_cdc_single_HD1570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fm_status_fifo_xpm_cdc_single__2_HD1571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | fm_status_fifo_xpm_cdc_async_rst__1_HD1572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ctl0 | FM_example_FIFOctrl__6 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_fm | ila_fullmode_HD1818 | 1194(0.34%) | 1022(0.30%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_fm) | ila_fullmode_HD1818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fullmode_ila_v6_2_12_ila_HD1819 | 1194(0.34%) | 1022(0.30%) | 0(0.00%) | 172(0.10%) | 1852(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_fullmode_ila_v6_2_12_ila_HD1819 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fullmode_ila_v6_2_12_ila_core_HD1820 | 1193(0.34%) | 1021(0.29%) | 0(0.00%) | 172(0.10%) | 1846(0.27%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_fullmode_ila_v6_2_12_ila_core_HD1820 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fullmode_ila_v6_2_12_ila_trace_memory_HD1821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fullmode_blk_mem_gen_v8_4_5_HD1822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_synth_HD1823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD1824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD1825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD1826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD1827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD1828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fullmode_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD1829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD1830 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fullmode_ila_v6_2_12_ila_cap_ctrl_legacy_HD1830 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fullmode_ltlib_v1_0_0_cfglut6__parameterized0_HD1831 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fullmode_ltlib_v1_0_0_cfglut7_HD1832 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fullmode_ltlib_v1_0_0_cfglut7__1_HD1833 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD1834 | 62(0.02%) | 25(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fullmode_ila_v6_2_12_ila_cap_addrgen_HD1834 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fullmode_ltlib_v1_0_0_cfglut6__1_HD1835 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD1836 | 30(0.01%) | 17(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fullmode_ila_v6_2_12_ila_cap_sample_counter_HD1836 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fullmode_ltlib_v1_0_0_cfglut4__1_HD1837 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__1_HD1838 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fullmode_ltlib_v1_0_0_cfglut6_HD1839 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__1_HD1840 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD1841 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_62_HD1841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD1842 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_63_HD1842 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_64_HD1843 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_65_HD1844 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD1845 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fullmode_ila_v6_2_12_ila_cap_window_counter_HD1845 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fullmode_ltlib_v1_0_0_cfglut4_HD1846 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5_HD1847 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fullmode_ltlib_v1_0_0_cfglut5__2_HD1848 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay_HD1849 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD1850 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_HD1850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD1851 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_HD1851 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD1852 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD1853 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fullmode_ltlib_v1_0_0_match_nodelay__2_HD1854 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD1855 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_nodelay_58_HD1855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD1856 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized2_59_HD1856 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized1_60_HD1857 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized2_61_HD1858 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fullmode_ila_v6_2_12_ila_register_HD1859 | 915(0.26%) | 914(0.26%) | 0(0.00%) | 1(0.01%) | 1324(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fullmode_ila_v6_2_12_ila_register_HD1859 | 330(0.10%) | 329(0.09%) | 0(0.00%) | 1(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s_HD1860 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized9_HD1861 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized10_HD1862 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized0_HD1863 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized1_HD1864 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized2_HD1865 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized3_HD1866 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized4_HD1867 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized5_HD1868 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized6_HD1869 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized7_HD1870 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized8_HD1871 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.qual_strg_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized12_HD1872 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized11_HD1873 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fullmode_xsdbs_v1_0_2_xsdbs_HD1874 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized42_HD1875 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_54_HD1876 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized43_HD1877 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_53_HD1878 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized44_HD1879 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_52_HD1880 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized45_HD1881 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_51_HD1882 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized46_HD1883 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_50_HD1884 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fullmode_xsdbs_v1_0_2_reg__parameterized47_HD1885 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_49_HD1886 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized27_HD1887 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_57_HD1888 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized28_HD1889 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized0_HD1890 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized29_HD1891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_56_HD1892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized48_HD1893 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_48_HD1894 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized49_HD1895 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_47_HD1896 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized50_HD1897 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl__parameterized1_HD1898 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized51_HD1899 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_46_HD1900 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized52_HD1901 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_45_HD1902 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized53_HD1903 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_44_HD1904 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized55_HD1905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_43_HD1906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fullmode_xsdbs_v1_0_2_reg__parameterized57_HD1907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_42_HD1908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD1909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fullmode_xsdbs_v1_0_2_reg__parameterized60_HD1909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_41_HD1910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fullmode_xsdbs_v1_0_2_reg__parameterized30_HD1911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_55_HD1912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fullmode_xsdbs_v1_0_2_reg_p2s__parameterized13_HD1913 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fullmode_xsdbs_v1_0_2_reg_stream_HD1914 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fullmode_xsdbs_v1_0_2_reg_ctl_HD1915 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD1916 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fullmode_xsdbs_v1_0_2_reg_stream__parameterized0_HD1916 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fullmode_xsdbs_v1_0_2_reg_stat_HD1917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD1918 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fullmode_ila_v6_2_12_ila_reset_ctrl_HD1918 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection_HD1919 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__2_HD1920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__3_HD1921 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer__1_HD1922 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fullmode_ltlib_v1_0_0_async_edge_xfer_HD1923 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fullmode_ltlib_v1_0_0_rising_edge_detection__1_HD1924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fullmode_ila_v6_2_12_ila_trigger_HD1925 | 123(0.04%) | 21(0.01%) | 0(0.00%) | 102(0.06%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fullmode_ila_v6_2_12_ila_trigger_HD1925 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fullmode_ltlib_v1_0_0_match__1_HD1926 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fullmode_ltlib_v1_0_0_match__1_HD1926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD1927 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_37_HD1927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD1928 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_38_HD1928 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_39_HD1929 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_40_HD1930 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STRG_QUAL.U_STRG_QUAL | ila_fullmode_ltlib_v1_0_0_match_HD1931 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (STRG_QUAL.U_STRG_QUAL) | ila_fullmode_ltlib_v1_0_0_match_HD1931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD1932 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA_HD1932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA_HD1933 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA_HD1933 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_35_HD1934 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_36_HD1935 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fullmode_ila_v6_2_12_ila_trig_match_HD1936 | 104(0.03%) | 20(0.01%) | 0(0.00%) | 84(0.05%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fullmode_ila_v6_2_12_ila_trig_match_HD1936 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD1937 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0__1_HD1937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD1938 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_29_HD1938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD1939 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_30_HD1939 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_31_HD1940 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_32_HD1941 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_33_HD1942 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_34_HD1943 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD1944 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__7_HD1944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD1945 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_0_HD1945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1946 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_1_HD1946 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD1947 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD1948 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2_HD1948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD1949 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_HD1949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD1950 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_HD1950 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD1951 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD1952 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized0_HD1952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD1953 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized0_HD1953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD1954 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized0_HD1954 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_HD1955 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_26_HD1956 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice_27_HD1957 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_28_HD1958 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD1959 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1__1_HD1959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD1960 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_23_HD1960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1961 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_24_HD1961 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_25_HD1962 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD1963 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized1_HD1963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD1964 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized1_HD1964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1965 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_21_HD1965 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_22_HD1966 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD1967 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__1_HD1967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD1968 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_18_HD1968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1969 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_19_HD1969 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD1970 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD1971 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__2_HD1971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD1972 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD1972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1973 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_16_HD1973 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_17_HD1974 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD1975 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__3_HD1975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD1976 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_12_HD1976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1977 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_13_HD1977 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD1978 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD1979 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__4_HD1979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD1980 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_9_HD1980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1981 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_10_HD1981 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD1982 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD1983 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__5_HD1983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD1984 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_6_HD1984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1985 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_7_HD1985 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD1986 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD1987 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fullmode_ltlib_v1_0_0_match__parameterized2__6_HD1987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD1988 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fullmode_ltlib_v1_0_0_allx_typeA__parameterized2_3_HD1988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1989 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fullmode_ltlib_v1_0_0_all_typeA__parameterized1_4_HD1989 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fullmode_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD1990 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fullmode_ltlib_v1_0_0_generic_memrd_HD1991 | 48(0.01%) | 46(0.01%) | 0(0.00%) | 2(0.01%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ram0 | FM_example_emuram | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ram0) | FM_example_emuram | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM_0 | DPram_32b_HD2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPram_32b_blk_mem_gen_v8_4_5_HD2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPram_32b_blk_mem_gen_v8_4_5_synth_HD2583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPram_32b_blk_mem_gen_top_HD2584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPram_32b_blk_mem_gen_generic_cstr_HD2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPram_32b_blk_mem_gen_prim_width_HD2586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_init.ram | DPram_32b_blk_mem_gen_prim_wrapper_init_HD2587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | reset_timer | rst_tmr__6 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u5 | FMchannelTXctrl__6 | 177(0.05%) | 177(0.05%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u5) | FMchannelTXctrl__6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_0 | CRC__parameterized4 | 153(0.04%) | 153(0.04%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eob_space_trig | pulse_pdxx_pwxx | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eop_space_trig | pulse_pdxx_pwxx_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sob_space_trig | pulse_pdxx_pwxx_22 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sop_space_trig | pulse_pdxx_pwxx_23 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u7 | FIFO34to34b | 53(0.02%) | 50(0.01%) | 0(0.00%) | 3(0.01%) | 115(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | FIFO34b | fifo1KB_34bit_HD2642 | 53(0.02%) | 50(0.01%) | 0(0.00%) | 3(0.01%) | 115(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | fifo1KB_34bit_fifo_generator_v13_2_7_HD2643 | 53(0.02%) | 50(0.01%) | 0(0.00%) | 3(0.01%) | 115(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo1KB_34bit_fifo_generator_v13_2_7_synth_HD2644 | 53(0.02%) | 50(0.01%) | 0(0.00%) | 3(0.01%) | 115(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo1KB_34bit_fifo_generator_top_HD2645 | 53(0.02%) | 50(0.01%) | 0(0.00%) | 3(0.01%) | 115(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo1KB_34bit_fifo_generator_ramfifo_HD2646 | 53(0.02%) | 50(0.01%) | 0(0.00%) | 3(0.01%) | 115(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | fifo1KB_34bit_clk_x_pntrs_HD2647 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | fifo1KB_34bit_clk_x_pntrs_HD2647 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray_HD2648 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | fifo1KB_34bit_xpm_cdc_gray__2_HD2649 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | fifo1KB_34bit_rd_logic_HD2650 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | fifo1KB_34bit_rd_status_flags_as_HD2651 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | fifo1KB_34bit_rd_bin_cntr_HD2652 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | fifo1KB_34bit_wr_logic_HD2653 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | fifo1KB_34bit_wr_pf_as_HD2654 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | fifo1KB_34bit_wr_status_flags_as_HD2656 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | fifo1KB_34bit_wr_bin_cntr_HD2657 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | fifo1KB_34bit_memory_HD2658 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | fifo1KB_34bit_blk_mem_gen_v8_4_5_HD2659 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_v8_4_5_synth_HD2660 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | fifo1KB_34bit_blk_mem_gen_top_HD2661 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | fifo1KB_34bit_blk_mem_gen_generic_cstr_HD2662 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | fifo1KB_34bit_blk_mem_gen_prim_width_HD2663 | 8(0.01%) | 5(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | fifo1KB_34bit_blk_mem_gen_prim_width_HD2663 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | fifo1KB_34bit_blk_mem_gen_prim_wrapper_HD2664 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rstblk | fifo1KB_34bit_reset_blk_ramfifo_HD2665 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | fifo1KB_34bit_reset_blk_ramfifo_HD2665 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | fifo1KB_34bit_xpm_cdc_single_HD2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | fifo1KB_34bit_xpm_cdc_single__2_HD2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst_HD2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | fifo1KB_34bit_xpm_cdc_sync_rst__2_HD2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vio_fm_reset | vio_fullmode_reset_HD2529 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (vio_fm_reset) | vio_fullmode_reset_HD2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_fullmode_reset_vio_v3_0_22_vio_HD2530 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 308(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_fullmode_reset_vio_v3_0_22_vio_HD2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_fullmode_reset_vio_v3_0_22_decoder_HD2531 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_fullmode_reset_vio_v3_0_22_probe_in_one_HD2532 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2533 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_fullmode_reset_vio_v3_0_22_probe_out_all_HD2533 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_HD2534 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one__parameterized0_HD2535 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_fullmode_reset_vio_v3_0_22_probe_out_one_0_HD2536 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_WIDTH_INST | vio_fullmode_reset_vio_v3_0_22_probe_width__parameterized0_HD2537 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_fullmode_reset_xsdbs_v1_0_2_xsdbs_HD2538 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk_blk | clk_wiz_240_HD1078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_240_clk_wiz_HD1079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u0 | FullModeTransceiver | 1166(0.34%) | 1060(0.31%) | 0(0.00%) | 106(0.06%) | 1793(0.26%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (u0) | FullModeTransceiver | 40(0.01%) | 33(0.01%) | 0(0.00%) | 7(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | g_gt_channel[0].rxresetfsm_i | FullModeTransceiver_RX_STARTUP_FSM__2 | 87(0.03%) | 87(0.03%) | 0(0.00%) | 0(0.00%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (g_gt_channel[0].rxresetfsm_i) | FullModeTransceiver_RX_STARTUP_FSM__2 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullModeTransceiver_sync_block_14 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullModeTransceiver_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullModeTransceiver_sync_block_16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullModeTransceiver_sync_block_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | g_gt_channel[1].rxresetfsm_i | FullModeTransceiver_RX_STARTUP_FSM__3 | 86(0.02%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (g_gt_channel[1].rxresetfsm_i) | FullModeTransceiver_RX_STARTUP_FSM__3 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | FullModeTransceiver_sync_block_7 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | FullModeTransceiver_sync_block_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | FullModeTransceiver_sync_block_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_10 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | FullModeTransceiver_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_resetfsm | ila_mgtfsm | 875(0.25%) | 776(0.22%) | 0(0.00%) | 99(0.06%) | 1358(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_resetfsm) | ila_mgtfsm | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_mgtfsm_ila_v6_2_12_ila | 875(0.25%) | 776(0.22%) | 0(0.00%) | 99(0.06%) | 1358(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_mgtfsm_ila_v6_2_12_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_mgtfsm_ila_v6_2_12_ila_core | 874(0.25%) | 775(0.22%) | 0(0.00%) | 99(0.06%) | 1352(0.20%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_mgtfsm_ila_v6_2_12_ila_core | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_mgtfsm_ila_v6_2_12_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_mgtfsm_blk_mem_gen_v8_4_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_mgtfsm_blk_mem_gen_v8_4_5_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_mgtfsm_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | u_ila_cap_ctrl | ila_mgtfsm_ila_v6_2_12_ila_cap_ctrl_legacy | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_mgtfsm_ila_v6_2_12_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_mgtfsm_ltlib_v1_0_0_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_mgtfsm_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_mgtfsm_ltlib_v1_0_0_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_mgtfsm_ila_v6_2_12_ila_cap_addrgen | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_mgtfsm_ila_v6_2_12_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_mgtfsm_ltlib_v1_0_0_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_mgtfsm_ila_v6_2_12_ila_cap_sample_counter | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_mgtfsm_ila_v6_2_12_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_mgtfsm_ltlib_v1_0_0_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_mgtfsm_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_44 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_45 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_45 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_mgtfsm_ila_v6_2_12_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_mgtfsm_ila_v6_2_12_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_mgtfsm_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_mgtfsm_ltlib_v1_0_0_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_mgtfsm_ltlib_v1_0_0_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_40 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA_nodelay_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_41 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA__parameterized0_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized0_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice__parameterized1_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_mgtfsm_ila_v6_2_12_ila_register | 707(0.20%) | 706(0.20%) | 0(0.00%) | 1(0.01%) | 1085(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_mgtfsm_ila_v6_2_12_ila_register | 278(0.08%) | 277(0.08%) | 0(0.00%) | 1(0.01%) | 159(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized2 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized3 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized5 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized6 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized7 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_mgtfsm_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized41 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized42 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized43 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized44 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized45 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1_31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_39 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized46 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1_30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl_26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized53 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_mgtfsm_xsdbs_v1_0_2_reg__parameterized28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_mgtfsm_xsdbs_v1_0_2_reg_p2s__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_mgtfsm_xsdbs_v1_0_2_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_mgtfsm_xsdbs_v1_0_2_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_mgtfsm_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_mgtfsm_xsdbs_v1_0_2_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_mgtfsm_xsdbs_v1_0_2_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_mgtfsm_ila_v6_2_12_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_mgtfsm_ila_v6_2_12_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_mgtfsm_ltlib_v1_0_0_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_mgtfsm_ltlib_v1_0_0_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_mgtfsm_ltlib_v1_0_0_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_mgtfsm_ila_v6_2_12_ila_trigger | 50(0.01%) | 5(0.01%) | 0(0.00%) | 45(0.03%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_mgtfsm_ila_v6_2_12_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_mgtfsm_ltlib_v1_0_0_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_mgtfsm_ltlib_v1_0_0_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_21 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_mgtfsm_ila_v6_2_12_ila_trig_match | 44(0.01%) | 4(0.01%) | 0(0.00%) | 40(0.02%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_mgtfsm_ila_v6_2_12_ila_trig_match | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_18 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_19 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_15 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_16 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_16 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_13 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_13 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_10 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_10 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_11 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_7 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_8 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_3 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_4 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA_1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_mgtfsm_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_mgtfsm_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_mgtfsm_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_mgtfsm_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_mgtfsm_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_mgtfsm_ltlib_v1_0_0_generic_memrd | 26(0.01%) | 24(0.01%) | 0(0.00%) | 2(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txresetfsm_i | FullModeTransceiver_TX_STARTUP_FSM__2 | 78(0.02%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txresetfsm_i) | FullModeTransceiver_TX_STARTUP_FSM__2 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | FullModeTransceiver_sync_block | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | FullModeTransceiver_sync_block_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | FullModeTransceiver_sync_block_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | FullModeTransceiver_sync_block_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | FullModeTransceiver_sync_block_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | FullModeTransceiver_sync_block_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_blk | ROD_system | 12206(3.52%) | 11491(3.32%) | 345(0.20%) | 370(0.21%) | 15874(2.29%) | 19(1.61%) | 4(0.17%) | 0(0.00%) | | (ipbus_blk) | ROD_system | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi4_subsys | axi4_subsys_wrapper | 6771(1.95%) | 6222(1.80%) | 220(0.13%) | 329(0.19%) | 8263(1.19%) | 2(0.17%) | 3(0.13%) | 0(0.00%) | | (axi4_subsys) | axi4_subsys_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi4_subsys_i | axi4_subsys | 6771(1.95%) | 6222(1.80%) | 220(0.13%) | 329(0.19%) | 8263(1.19%) | 2(0.17%) | 3(0.13%) | 0(0.00%) | | axi_emc_0 | axi4_subsys_axi_emc_0_0 | 451(0.13%) | 315(0.09%) | 0(0.00%) | 136(0.08%) | 266(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_emc | 451(0.13%) | 315(0.09%) | 0(0.00%) | 136(0.08%) | 266(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_emc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_EMC_NATIVE_INTERFACE_I | axi_emc_native_interface | 357(0.10%) | 221(0.06%) | 0(0.00%) | 136(0.08%) | 123(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (AXI_EMC_NATIVE_INTERFACE_I) | axi_emc_native_interface | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 81(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_EMC_ADDRESS_DECODE_INSTANCE_I | axi_emc_address_decode | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_EMC_ADDR_GEN_INSTANCE_I | axi_emc_addr_gen | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RDATA_FIFO_I | srl_fifo_rbu_f | 164(0.05%) | 28(0.01%) | 0(0.00%) | 136(0.08%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RDATA_FIFO_I) | srl_fifo_rbu_f | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CNTR_INCR_DECR_ADDN_F_I | cntr_incr_decr_addn_f | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DYNSHREG_F_I | dynshreg_f | 145(0.04%) | 9(0.01%) | 0(0.00%) | 136(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EMC_CTRL_I | EMC | 104(0.03%) | 104(0.03%) | 0(0.00%) | 0(0.00%) | 142(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDR_COUNTER_MUX_I | addr_counter_mux | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | COUNTERS_I | counters | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | THZCNT_I | ld_arith_reg__parameterized1 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TLZCNT_I | ld_arith_reg__parameterized1_1794 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TRDCNT_I | ld_arith_reg__parameterized0 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TWPHCNT_I | ld_arith_reg__parameterized1_1795 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TWRCNT_I | ld_arith_reg__parameterized0_1796 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IO_REGISTERS_I | io_registers | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPIC_IF_I | emc_common_v3_0_5_ipic_if | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IPIC_IF_I) | emc_common_v3_0_5_ipic_if | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BURST_CNT | ld_arith_reg | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_STATE_MACHINE_I | mem_state_machine | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_STEER_I | mem_steer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_gpio_0 | axi4_subsys_axi_gpio_0_0 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 295(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_gpio | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 295(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | axi_gpio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi_lite_ipif | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_DECODER) | address_decoder | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gpio_core_1 | GPIO_Core | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 202(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gpio_core_1) | GPIO_Core | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 106(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Dual.INPUT_DOUBLE_REGS5 | cdc_sync__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 96(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_hwicap_0 | axi4_subsys_axi_hwicap_0_0 | 489(0.14%) | 489(0.14%) | 0(0.00%) | 0(0.00%) | 1126(0.16%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | U0 | axi_hwicap | 489(0.14%) | 489(0.14%) | 0(0.00%) | 0(0.00%) | 1126(0.16%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | (U0) | axi_hwicap | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP_SHARED.HWICAP_CTRL_I | hwicap_shared | 367(0.11%) | 367(0.11%) | 0(0.00%) | 0(0.00%) | 997(0.14%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | (ICAP_SHARED.HWICAP_CTRL_I) | hwicap_shared | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_BUS2ICAP_RESET | cdc_sync__parameterized3_1771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPIC_IF_I | axi_hwicap_v3_0_30_ipic_if | 285(0.08%) | 285(0.08%) | 0(0.00%) | 0(0.00%) | 813(0.12%) | 0(0.00%) | 2(0.08%) | 0(0.00%) | | (IPIC_IF_I) | axi_hwicap_v3_0_30_ipic_if | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BUS2ICAP_SIZE_REGISTER_PROCESS | cdc_sync__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_RST_CDC_PROCESS | cdc_sync__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2BUS_STATUS_REGISTER_PROCESS | cdc_sync__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH1 | cdc_sync__parameterized3_1772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH2 | cdc_sync__parameterized3_1773 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH3 | cdc_sync__parameterized3_1774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH4 | cdc_sync__parameterized3_1775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ICAP2PLB_SYNCH5 | cdc_sync__parameterized1_1776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLB2ICAP_SYNCH1 | cdc_sync__parameterized3_1777 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLB2ICAP_SYNCH2 | cdc_sync__parameterized3_1778 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLB2ICAP_SYNCH3 | cdc_sync__parameterized3_1779 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD_FIFO.RDDATA_FIFO_I | async_fifo_fg__parameterized0 | 156(0.05%) | 156(0.05%) | 0(0.00%) | 0(0.00%) | 259(0.04%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (RD_FIFO.RDDATA_FIFO_I) | async_fifo_fg__parameterized0 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_instance.xpm_fifo_async_inst | xpm_fifo_async__parameterized1 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 259(0.04%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base__parameterized0 | 145(0.04%) | 145(0.04%) | 0(0.00%) | 0(0.00%) | 259(0.04%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized1 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray__parameterized0__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec__parameterized0_1787 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | xpm_fifo_reg_vec__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec__parameterized0_1788 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | xpm_fifo_reg_vec__parameterized1_1789 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized1__1 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__parameterized0__1 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized5 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit_1790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized5_1791 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized6_1792 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized4_1793 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD_FIFO.RDFULL_SYNCH | cdc_sync__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRFIFO.WRDATA_FIFO_I | async_fifo_fg | 115(0.03%) | 115(0.03%) | 0(0.00%) | 0(0.00%) | 179(0.03%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (WRFIFO.WRDATA_FIFO_I) | async_fifo_fg | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_instance.xpm_fifo_async_inst | xpm_fifo_async | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 179(0.03%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 179(0.03%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized0 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | xpm_fifo_reg_vec__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec_1781 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized2 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit_1783 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized1_1784 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized2_1785 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized0_1786 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst__xdcDup__1 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst__xdcDup__1 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRFIFO.WREMPTY_SYNCH | cdc_sync__parameterized3_1780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | icap_statemachine_I1 | icap_statemachine_shared | 83(0.02%) | 83(0.02%) | 0(0.00%) | 0(0.00%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INTERRUPT_CONTROL_I | interrupt_control | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | XI4_LITE_I | axi_lite_ipif__parameterized0 | 119(0.03%) | 119(0.03%) | 0(0.00%) | 0(0.00%) | 82(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized0 | 119(0.03%) | 119(0.03%) | 0(0.00%) | 0(0.00%) | 82(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized0 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 57(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized0 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_iic_0 | axi4_subsys_axi_iic_0_0 | 414(0.12%) | 404(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_iic__1 | 414(0.12%) | 404(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_IIC | iic | 414(0.12%) | 404(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_IIC) | iic | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DYN_MASTER_I | dynamic_master | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FILTER_I | filter | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SCL_DEBOUNCE | debounce | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3_1526 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SDA_DEBOUNCE | debounce_1525 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IIC_CONTROL_I | iic_control | 173(0.05%) | 173(0.05%) | 0(0.00%) | 0(0.00%) | 119(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IIC_CONTROL_I) | iic_control | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BITCNT | upcnt_n__parameterized0 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CLKCNT | upcnt_n | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CDATA_REG | shift8 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CHEADER_REG | shift8_1523 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SETUP_CNT | upcnt_n_1524 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READ_FIFO_I | SRL_FIFO | 12(0.01%) | 8(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | REG_INTERFACE_I | reg_interface | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 126(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_CTRL_I | SRL_FIFO__parameterized0 | 9(0.01%) | 7(0.01%) | 0(0.00%) | 2(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_I | SRL_FIFO_1522 | 16(0.01%) | 12(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_AXI_IPIF_SSP1 | axi_ipif_ssp1 | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_AXI_IPIF_SSP1) | axi_ipif_ssp1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi_lite_ipif__parameterized1 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized1 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized1 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized1 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_INTERRUPT_CONTROL | interrupt_control__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_SOFT_RESET | axi_iic_v2_1_2_soft_reset | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_iic_1 | axi4_subsys_axi_iic_1_0 | 415(0.12%) | 405(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_iic | 415(0.12%) | 405(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_IIC | iic_1548 | 415(0.12%) | 405(0.12%) | 0(0.00%) | 10(0.01%) | 381(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_IIC) | iic_1548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DYN_MASTER_I | dynamic_master_1549 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FILTER_I | filter_1550 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SCL_DEBOUNCE | debounce_1567 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3_1570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SDA_DEBOUNCE | debounce_1568 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_DOUBLE_REGS | cdc_sync__parameterized3_1569 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IIC_CONTROL_I | iic_control_1551 | 173(0.05%) | 173(0.05%) | 0(0.00%) | 0(0.00%) | 119(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IIC_CONTROL_I) | iic_control_1551 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BITCNT | upcnt_n__parameterized0_1562 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CLKCNT | upcnt_n_1563 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CDATA_REG | shift8_1564 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I2CHEADER_REG | shift8_1565 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SETUP_CNT | upcnt_n_1566 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READ_FIFO_I | SRL_FIFO_1552 | 12(0.01%) | 8(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | REG_INTERFACE_I | reg_interface_1553 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 126(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_CTRL_I | SRL_FIFO__parameterized0_1554 | 9(0.01%) | 7(0.01%) | 0(0.00%) | 2(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WRITE_FIFO_I | SRL_FIFO_1555 | 16(0.01%) | 12(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_AXI_IPIF_SSP1 | axi_ipif_ssp1_1556 | 151(0.04%) | 151(0.04%) | 0(0.00%) | 0(0.00%) | 93(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (X_AXI_IPIF_SSP1) | axi_ipif_ssp1_1556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi_lite_ipif__parameterized1_1557 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized1_1560 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized1_1560 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized1_1561 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_INTERRUPT_CONTROL | interrupt_control__parameterized0_1558 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | X_SOFT_RESET | axi_iic_v2_1_2_soft_reset_1559 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_interconnect_0 | axi4_subsys_axi_interconnect_0_0 | 3416(0.99%) | 3243(0.94%) | 0(0.00%) | 173(0.10%) | 3099(0.45%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m01_couplers | m01_couplers_imp_FF3AZQ | 392(0.11%) | 357(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_0 | 392(0.11%) | 357(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_1667 | 392(0.11%) | 357(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_1668 | 392(0.11%) | 357(0.10%) | 0(0.00%) | 35(0.02%) | 391(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_1668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_1669 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_1669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_1686 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1687 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1687 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1688 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1689 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_1670 | 53(0.02%) | 18(0.01%) | 0(0.00%) | 35(0.02%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_1670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_1684 | 43(0.01%) | 11(0.01%) | 0(0.00%) | 32(0.02%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_1685 | 10(0.01%) | 7(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_1671 | 166(0.05%) | 166(0.05%) | 0(0.00%) | 0(0.00%) | 182(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_1680 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_1681 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_1682 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_1683 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_1672 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_1672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_1676 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1677 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1677 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1678 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1679 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_1673 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_1673 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_1674 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_1675 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m02_couplers | m02_couplers_imp_L8N2BP | 362(0.10%) | 347(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_1 | 362(0.10%) | 347(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_1644 | 362(0.10%) | 347(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_1645 | 362(0.10%) | 347(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_1645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_1646 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_1646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_1663 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1664 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1664 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1665 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1666 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_1647 | 35(0.01%) | 20(0.01%) | 0(0.00%) | 15(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_1647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_1661 | 21(0.01%) | 9(0.01%) | 0(0.00%) | 12(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_1662 | 15(0.01%) | 12(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_1648 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_1657 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_1658 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_1659 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_1660 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_1649 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_1649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_1653 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1654 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1654 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1655 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1656 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_1650 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_1650 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_1651 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_1652 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m03_couplers | m03_couplers_imp_1MMZOD7 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_2 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_1621 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_1622 | 363(0.10%) | 348(0.10%) | 0(0.00%) | 15(0.01%) | 359(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_1622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_1623 | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_1623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_1640 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1641 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1641 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1642 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1643 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_1624 | 35(0.01%) | 20(0.01%) | 0(0.00%) | 15(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_1624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_1638 | 21(0.01%) | 9(0.01%) | 0(0.00%) | 12(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_1639 | 15(0.01%) | 12(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_1625 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 144(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_1634 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_1635 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_1636 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_1637 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_1626 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_1626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_1630 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1631 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1631 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1632 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1633 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_1627 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_1627 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_1628 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_1629 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m04_couplers | m04_couplers_imp_1FSUCEB | 394(0.11%) | 358(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_3 | 394(0.11%) | 358(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_1598 | 394(0.11%) | 358(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_1599 | 394(0.11%) | 358(0.10%) | 0(0.00%) | 36(0.02%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_1599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_1600 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_1600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_1617 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1618 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1618 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1619 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1620 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_1601 | 54(0.02%) | 18(0.01%) | 0(0.00%) | 36(0.02%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_1601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_1615 | 44(0.01%) | 11(0.01%) | 0(0.00%) | 33(0.02%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_1616 | 10(0.01%) | 7(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_1602 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_1611 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_1612 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_1613 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_1614 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_1603 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_1603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_1607 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1608 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1608 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1609 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1610 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_1604 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_1604 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_1605 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_1606 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m05_couplers | m05_couplers_imp_ADRT99 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_4 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter_1575 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s_1576 | 394(0.11%) | 359(0.10%) | 0(0.00%) | 35(0.02%) | 392(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s_1576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel_1577 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel_1577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm_1594 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1595 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1595 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1596 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1597 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel_1578 | 54(0.02%) | 19(0.01%) | 0(0.00%) | 35(0.02%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel_1578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1_1592 | 41(0.01%) | 9(0.01%) | 0(0.00%) | 32(0.02%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2_1593 | 14(0.01%) | 11(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice_1579 | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 182(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice_1588 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_1589 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1_1590 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2_1591 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel_1580 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel_1580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm_1584 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1585 | 67(0.02%) | 67(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1585 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1586 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1587 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel_1581 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel_1581 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo_1582 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0_1583 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | m06_couplers | m06_couplers_imp_Q7JFB2 | 389(0.11%) | 366(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_5 | 389(0.11%) | 366(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_protocol_converter_v2_1_26_axi_protocol_converter | 389(0.11%) | 366(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_axilite.gen_b2s_conv.axilite_b2s | axi_protocol_converter_v2_1_26_b2s | 389(0.11%) | 366(0.11%) | 0(0.00%) | 23(0.01%) | 395(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_axilite.gen_b2s_conv.axilite_b2s) | axi_protocol_converter_v2_1_26_b2s | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.ar_channel_0 | axi_protocol_converter_v2_1_26_b2s_ar_channel | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.ar_channel_0) | axi_protocol_converter_v2_1_26_b2s_ar_channel | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_rd_cmd_fsm | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1572 | 74(0.02%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator_1572 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd_1573 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd_1574 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RD.r_channel_0 | axi_protocol_converter_v2_1_26_b2s_r_channel | 43(0.01%) | 20(0.01%) | 0(0.00%) | 23(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RD.r_channel_0) | axi_protocol_converter_v2_1_26_b2s_r_channel | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_data_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized1 | 29(0.01%) | 9(0.01%) | 0(0.00%) | 20(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | transaction_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized2 | 15(0.01%) | 12(0.01%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SI_REG | axi_register_slice_v2_1_26_axi_register_slice | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 168(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ar.ar_pipe | axi_register_slice_v2_1_26_axic_register_slice | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw.aw_pipe | axi_register_slice_v2_1_26_axic_register_slice_1571 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized2 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.aw_channel_0 | axi_protocol_converter_v2_1_26_b2s_aw_channel | 82(0.02%) | 82(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.aw_channel_0) | axi_protocol_converter_v2_1_26_b2s_aw_channel | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aw_cmd_fsm_0 | axi_protocol_converter_v2_1_26_b2s_wr_cmd_fsm | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_translator_0 | axi_protocol_converter_v2_1_26_b2s_cmd_translator | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (cmd_translator_0) | axi_protocol_converter_v2_1_26_b2s_cmd_translator | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | incr_cmd_0 | axi_protocol_converter_v2_1_26_b2s_incr_cmd | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrap_cmd_0 | axi_protocol_converter_v2_1_26_b2s_wrap_cmd | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WR.b_channel_0 | axi_protocol_converter_v2_1_26_b2s_b_channel | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (WR.b_channel_0) | axi_protocol_converter_v2_1_26_b2s_b_channel | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bid_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bresp_fifo_0 | axi_protocol_converter_v2_1_26_b2s_simple_fifo__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | s00_couplers | s00_couplers_imp_IY3DNS | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | auto_pc | axi4_subsys_auto_pc_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xbar | axi4_subsys_xbar_0 | 1122(0.32%) | 1108(0.32%) | 0(0.00%) | 14(0.01%) | 823(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axi_crossbar_v2_1_27_axi_crossbar | 1122(0.32%) | 1108(0.32%) | 0(0.00%) | 14(0.01%) | 823(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_samd.crossbar_samd | axi_crossbar_v2_1_27_crossbar | 1122(0.32%) | 1108(0.32%) | 0(0.00%) | 14(0.01%) | 823(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_samd.crossbar_samd) | axi_crossbar_v2_1_27_crossbar | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_arbiter_ar | axi_crossbar_v2_1_27_addr_arbiter | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (addr_arbiter_ar) | axi_crossbar_v2_1_27_addr_arbiter | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_arbiter.mux_mesg | generic_baseblocks_v2_1_0_mux_enc__parameterized2_1746 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_arbiter_aw | axi_crossbar_v2_1_27_addr_arbiter_1690 | 174(0.05%) | 174(0.05%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (addr_arbiter_aw) | axi_crossbar_v2_1_27_addr_arbiter_1690 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_arbiter.mux_mesg | generic_baseblocks_v2_1_0_mux_enc__parameterized2 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_decerr_slave.decerr_slave_inst | axi_crossbar_v2_1_27_decerr_slave | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[0].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux | 26(0.01%) | 25(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[0].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1744 | 25(0.01%) | 24(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1744 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1745 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[0].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_1742 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_1743 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[1].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_1691 | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[1].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_1691 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1740 | 21(0.01%) | 20(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1740 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1741 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[1].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_1692 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_1738 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_1739 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[2].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_1693 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[2].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_1693 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1736 | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1736 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1737 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[2].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_1694 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_1734 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_1735 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[3].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_1695 | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[3].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_1695 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1732 | 15(0.01%) | 14(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1732 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1733 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[3].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_1696 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_1730 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_1731 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[4].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_1697 | 34(0.01%) | 33(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[4].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_1697 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1728 | 32(0.01%) | 31(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1728 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1729 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[4].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_1698 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 83(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_1726 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_1727 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[5].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_1699 | 34(0.01%) | 33(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[5].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_1699 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1724 | 32(0.01%) | 31(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0_1724 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1725 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[5].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_1700 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_1722 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_1723 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[6].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux_1701 | 20(0.01%) | 19(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[6].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux_1701 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0 | 18(0.01%) | 17(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized0 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1721 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[6].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_1702 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 57(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9_1719 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10_1720 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[7].gen_mi_write.wdata_mux_w | axi_crossbar_v2_1_27_wdata_mux__parameterized0 | 9(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_master_slots[7].gen_mi_write.wdata_mux_w) | axi_crossbar_v2_1_27_wdata_mux__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_wmux.wmux_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized1 | 8(0.01%) | 7(0.01%) | 0(0.00%) | 1(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_wmux.wmux_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo__parameterized1 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1718 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_master_slots[7].reg_slice_mi | axi_register_slice_v2_1_26_axi_register_slice__parameterized1_1703 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | b.b_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized9 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | r.r_pipe | axi_register_slice_v2_1_26_axic_register_slice__parameterized10 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_read.si_transactor_ar | axi_crossbar_v2_1_27_si_transactor | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_slave_slots[0].gen_si_read.si_transactor_ar) | axi_crossbar_v2_1_27_si_transactor | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_single_thread.mux_resp_single_thread | generic_baseblocks_v2_1_0_mux_enc_1717 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_write.si_transactor_aw | axi_crossbar_v2_1_27_si_transactor__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_write.splitter_aw_si | axi_crossbar_v2_1_27_splitter | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[0].gen_si_write.wdata_router_w | axi_crossbar_v2_1_27_wdata_router | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrouter_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo_1711 | 32(0.01%) | 29(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (wrouter_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo_1711 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1712 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[1].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1713 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[2].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1714 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[3].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1715 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_read.si_transactor_ar | axi_crossbar_v2_1_27_si_transactor__parameterized1 | 115(0.03%) | 115(0.03%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_slave_slots[1].gen_si_read.si_transactor_ar) | axi_crossbar_v2_1_27_si_transactor__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.arbiter_resp_inst | axi_crossbar_v2_1_27_arbiter_resp_1710 | 101(0.03%) | 101(0.03%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.mux_resp_multi_thread | generic_baseblocks_v2_1_0_mux_enc | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_write.si_transactor_aw | axi_crossbar_v2_1_27_si_transactor__parameterized2 | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gen_slave_slots[1].gen_si_write.si_transactor_aw) | axi_crossbar_v2_1_27_si_transactor__parameterized2 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.arbiter_resp_inst | axi_crossbar_v2_1_27_arbiter_resp | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_multi_thread.mux_resp_multi_thread | generic_baseblocks_v2_1_0_mux_enc__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_write.splitter_aw_si | axi_crossbar_v2_1_27_splitter_1704 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_slave_slots[1].gen_si_write.wdata_router_w | axi_crossbar_v2_1_27_wdata_router_1705 | 27(0.01%) | 24(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrouter_aw_fifo | axi_data_fifo_v2_1_25_axic_reg_srl_fifo | 27(0.01%) | 24(0.01%) | 0(0.00%) | 3(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (wrouter_aw_fifo) | axi_data_fifo_v2_1_25_axic_reg_srl_fifo | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[0].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[1].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1707 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[2].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1708 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_srls[0].gen_rep[3].srl_nx1 | axi_data_fifo_v2_1_25_ndeep_srl_1709 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | splitter_aw_mi | axi_crossbar_v2_1_27_splitter_1706 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_quad_spi_0 | axi4_subsys_axi_quad_spi_0_0 | 545(0.16%) | 501(0.14%) | 44(0.03%) | 0(0.00%) | 793(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_quad_spi | 545(0.16%) | 501(0.14%) | 44(0.03%) | 0(0.00%) | 793(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | NO_DUAL_QUAD_MODE.QSPI_NORMAL | axi_quad_spi_top | 545(0.16%) | 501(0.14%) | 44(0.03%) | 0(0.00%) | 793(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (NO_DUAL_QUAD_MODE.QSPI_NORMAL) | axi_quad_spi_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I | axi_lite_ipif__parameterized2 | 108(0.03%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 91(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | slave_attachment__parameterized2 | 108(0.03%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 91(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | slave_attachment__parameterized2 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | address_decoder__parameterized2 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_DECODER) | address_decoder__parameterized2 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[10].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized14 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[11].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized15 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[12].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[13].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[14].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[15].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[1].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[8].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[0].PER_CE_GEN[9].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized24 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized21_1544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized23_1545 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized24_1546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I | axi_lite_ipif_v3_0_4_pselect_f__parameterized27_1547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I | qspi_core_interface | 438(0.13%) | 394(0.11%) | 44(0.03%) | 0(0.00%) | 701(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I) | qspi_core_interface | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONTROL_REG_I | qspi_cntrl_reg | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.CLK_CROSS_I | cross_clk_sync_fifo_1 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.FIFO_IF_MODULE_I | qspi_fifo_ifmodule | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC | cdc_sync__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC | cdc_sync__parameterized6_1527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.RX_FIFO_II | xpm_fifo_async__parameterized3 | 116(0.03%) | 94(0.03%) | 22(0.01%) | 0(0.00%) | 188(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base__parameterized1 | 116(0.03%) | 94(0.03%) | 22(0.01%) | 0(0.00%) | 188(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf_wptr_p3.wrpp3_inst | xpm_counter_updn__parameterized7_1532 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray__parameterized2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec__parameterized2_1533 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec__parameterized2_1535 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | xpm_fifo_reg_vec__parameterized3_1536 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__parameterized2__3 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | xpm_counter_updn__parameterized9_1537 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base__parameterized1 | 22(0.01%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized10_1538 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized11_1539 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit_1540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized10_1541 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized11_1542 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized8_1543 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst__parameterized0__xdcDup__1 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst__parameterized0__xdcDup__1 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__parameterized0__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I | axi_quad_spi_v3_2_25_counter_f | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FIFO_EXISTS.TX_FIFO_II | async_fifo_fg__parameterized1 | 128(0.04%) | 106(0.03%) | 22(0.01%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (FIFO_EXISTS.TX_FIFO_II) | async_fifo_fg__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_instance.xpm_fifo_async_inst | xpm_fifo_async__parameterized5 | 119(0.03%) | 97(0.03%) | 22(0.01%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnuram_async_fifo.xpm_fifo_base_inst | xpm_fifo_base__parameterized2 | 119(0.03%) | 97(0.03%) | 22(0.01%) | 0(0.00%) | 178(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gnuram_async_fifo.xpm_fifo_base_inst) | xpm_fifo_base__parameterized2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf_wptr_p3.wrpp3_inst | xpm_counter_updn__parameterized7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | xpm_cdc_gray__parameterized4__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | xpm_cdc_gray__parameterized2__2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | xpm_fifo_reg_vec__parameterized2 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | xpm_fifo_reg_vec__parameterized3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | xpm_fifo_reg_vec__parameterized2_1528 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | xpm_cdc_gray__parameterized2__1 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | xpm_counter_updn__parameterized9 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | xpm_memory_base__parameterized1__1 | 22(0.01%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdp_inst | xpm_counter_updn__parameterized10 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | xpm_counter_updn__parameterized11 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | xpm_fifo_reg_bit | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | xpm_counter_updn__parameterized10_1530 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | xpm_counter_updn__parameterized11_1531 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | xpm_counter_updn__parameterized8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | xpm_fifo_rst__parameterized0 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | xpm_fifo_rst__parameterized0 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | xpm_cdc_sync_rst__parameterized0__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | xpm_cdc_sync_rst__parameterized0__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INTERRUPT_CONTROL_I | interrupt_control__parameterized1 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LOGIC_FOR_MD_0_GEN.SPI_MODULE_I | qspi_mode_0_module | 101(0.03%) | 101(0.03%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RESET_SYNC_AXI_SPI_CLK_INST | reset_sync_module | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SOFT_RESET_I | axi_quad_spi_v3_2_25_soft_reset | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I | qspi_status_slave_sel_reg | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | jtag_axi_0 | axi4_subsys_jtag_axi_0_0 | 753(0.22%) | 577(0.17%) | 176(0.10%) | 0(0.00%) | 1680(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | U0 | jtag_axi_v1_2_15_jtag_axi | 753(0.22%) | 577(0.17%) | 176(0.10%) | 0(0.00%) | 1680(0.24%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | axi_bridge_u | jtag_axi_v1_2_15_axi_bridge | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | read_axi_full_u | jtag_axi_v1_2_15_read_axi | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 87(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | write_axi_full_u | jtag_axi_v1_2_15_write_axi | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | jtag_axi_engine_u | jtag_axi_v1_2_15_jtag_axi_engine | 697(0.20%) | 521(0.15%) | 176(0.10%) | 0(0.00%) | 1519(0.22%) | 2(0.17%) | 1(0.04%) | 0(0.00%) | | (jtag_axi_engine_u) | jtag_axi_v1_2_15_jtag_axi_engine | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_decode_rd_channel | jtag_axi_v1_2_15_cmd_decode | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cmd_decode_wr_channel | jtag_axi_v1_2_15_cmd_decode_1747 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_cmd_fifo_i | fifo_generator_v13_2_7__parameterized1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth__parameterized1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top__parameterized1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo__parameterized1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs__parameterized0 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized8__5 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized8__4 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic__parameterized0_1757 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft_1768 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as__parameterized0_1769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr__parameterized0_1770 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic__parameterized0_1758 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as__parameterized0_1766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr__parameterized0_1767 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory__parameterized1_1759 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory__parameterized1_1759 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | blk_mem_gen_v8_4_5__parameterized1_1760 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | blk_mem_gen_v8_4_5_synth__parameterized0_1761 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | blk_mem_gen_top__parameterized0_1762 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | blk_mem_gen_generic_cstr__parameterized0_1763 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | blk_mem_gen_prim_width__parameterized0_1764 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | blk_mem_gen_prim_width__parameterized0_1764 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | blk_mem_gen_prim_wrapper__parameterized0_1765 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rx_fifo_i | fifo_generator_v13_2_7__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo__parameterized0 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized6__5 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized6__4 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic_1750 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft_1754 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as_1755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr_1756 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic_1751 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as_1752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr_1753 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | blk_mem_gen_v8_4_5 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | blk_mem_gen_v8_4_5_synth | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | blk_mem_gen_top | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | blk_mem_gen_generic_cstr | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | blk_mem_gen_prim_width | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (ramloop[0].ram.r) | blk_mem_gen_prim_width | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | tx_fifo_i | fifo_generator_v13_2_7 | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo | 281(0.08%) | 105(0.03%) | 176(0.10%) | 0(0.00%) | 180(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs__xdcDup__1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs__xdcDup__1 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized6 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized6__6 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft_1749 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory | 208(0.06%) | 32(0.01%) | 176(0.10%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dmem | 208(0.06%) | 32(0.01%) | 176(0.10%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_xsdb_fifo_interface | jtag_axi_v1_2_15_xsdb_fifo_interface | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 474(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_xsdb_fifo_interface) | jtag_axi_v1_2_15_xsdb_fifo_interface | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rxfifo2xsdb_i | jtag_axi_v1_2_15_rxfifo2xsdb | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb2read_cmdfifo | jtag_axi_v1_2_15_xsdb2txfifo__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb2txfifo_i | jtag_axi_v1_2_15_xsdb2txfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 69(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb2write_cmdfifo | jtag_axi_v1_2_15_xsdb2txfifo__parameterized0_1748 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_cmd_fifo_i | fifo_generator_v13_2_7__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_generator_v13_2_7_synth__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_generator_top__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | fifo_generator_ramfifo__parameterized1__xdcDup__1 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 129(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | clk_x_pntrs__parameterized0__xdcDup__1 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | clk_x_pntrs__parameterized0__xdcDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | xpm_cdc_gray__parameterized8 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | xpm_cdc_gray__parameterized8__6 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | rd_logic__parameterized0 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | rd_fwft | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | rd_status_flags_as__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | rd_bin_cntr__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | wr_logic__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | wr_status_flags_as__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | wr_bin_cntr__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | memory__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | memory__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | blk_mem_gen_v8_4_5__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | blk_mem_gen_v8_4_5_synth__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | blk_mem_gen_top__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | blk_mem_gen_generic_cstr__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | blk_mem_gen_prim_width__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | blk_mem_gen_prim_width__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | blk_mem_gen_prim_wrapper__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | xadc_wiz_0 | axi4_subsys_xadc_wiz_0_0 | 191(0.06%) | 191(0.06%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi4_subsys_xadc_wiz_0_0_axi_xadc | 191(0.06%) | 191(0.06%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | axi4_subsys_xadc_wiz_0_0_axi_xadc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_LITE_IPIF_I | axi4_subsys_xadc_wiz_0_0_axi_lite_ipif | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | axi4_subsys_xadc_wiz_0_0_slave_attachment | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | axi4_subsys_xadc_wiz_0_0_slave_attachment | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | axi4_subsys_xadc_wiz_0_0_address_decoder | 122(0.04%) | 122(0.04%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | AXI_XADC_CORE_I | axi4_subsys_xadc_wiz_0_0_xadc_core_drp | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I | axi4_subsys_xadc_wiz_0_0_interrupt_control | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SOFT_RESET_I | axi4_subsys_xadc_wiz_0_0_soft_reset | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_regs | common_IdVersion_regs | 241(0.07%) | 241(0.07%) | 0(0.00%) | 0(0.00%) | 208(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (common_regs) | common_IdVersion_regs | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Xmlversion | ipbus_syncreg_v__parameterized0 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Xmlversion) | ipbus_syncreg_v__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1807 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | buildversion | ipbus_syncreg_v__parameterized0_1799 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (buildversion) | ipbus_syncreg_v__parameterized0_1799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1806 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dna_regs | ipbus_syncreg_v__parameterized0_1800 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dna_regs) | ipbus_syncreg_v__parameterized0_1800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1805 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fpga_dna | dna_reader | 162(0.05%) | 162(0.05%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_id_reg | ipbus_syncreg_v_1801 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (module_id_reg) | ipbus_syncreg_v_1801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1804 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | serial_num_reg | ipbus_syncreg_v_1802 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (serial_num_reg) | ipbus_syncreg_v_1802 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rsync | syncreg_r_1803 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ip_addr_probe | vio_ip_address | 399(0.12%) | 399(0.12%) | 0(0.00%) | 0(0.00%) | 733(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ip_addr_probe) | vio_ip_address | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ip_address_vio_v3_0_22_vio | 399(0.12%) | 399(0.12%) | 0(0.00%) | 0(0.00%) | 733(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ip_address_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ip_address_vio_v3_0_22_decoder | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ip_address_vio_v3_0_22_probe_in_one | 294(0.08%) | 294(0.08%) | 0(0.00%) | 0(0.00%) | 504(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_WIDTH_INST | vio_ip_address_vio_v3_0_22_probe_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ip_address_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus | ipbus_rod | 4727(1.36%) | 4561(1.32%) | 125(0.07%) | 41(0.02%) | 6670(0.96%) | 17(1.44%) | 1(0.04%) | 0(0.00%) | | clocks | clocks_7s_extphy | 23(0.01%) | 21(0.01%) | 0(0.00%) | 2(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 6(0.01%) | 5(0.01%) | 0(0.00%) | 1(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stretch | led_stretcher | 17(0.01%) | 16(0.01%) | 0(0.00%) | 1(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stretch) | led_stretcher | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div_1798 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | example_clocks | ethernet_mac_rgmii_example_design_clocks | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (example_clocks) | ethernet_mac_rgmii_example_design_clocks | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_generator | ethernet_mac_rgmii_clk_wiz | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | lock_sync | ethernet_mac_rgmii_sync_block | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mmcm_reset_gen | ethernet_mac_rgmii_reset_sync | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | example_resets | ethernet_mac_rgmii_example_design_resets | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (example_resets) | ethernet_mac_rgmii_example_design_resets | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_lite_reset_gen | ethernet_mac_rgmii_reset_sync__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | chk_reset_gen | ethernet_mac_rgmii_reset_sync__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dcm_sync | ethernet_mac_rgmii_sync_block__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | glbl_reset_gen | ethernet_mac_rgmii_reset_sync__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gtx_reset_gen | ethernet_mac_rgmii_reset_sync__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus | ipbus_ctrl | 3091(0.89%) | 3067(0.89%) | 0(0.00%) | 24(0.01%) | 3942(0.57%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (ipbus) | ipbus_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 396(0.11%) | 396(0.11%) | 0(0.00%) | 0(0.00%) | 319(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cfg | transactor_cfg | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 189(0.05%) | 189(0.05%) | 0(0.00%) | 0(0.00%) | 135(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 208(0.06%) | 208(0.06%) | 0(0.00%) | 0(0.00%) | 183(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 2693(0.78%) | 2669(0.77%) | 0(0.00%) | 24(0.01%) | 3623(0.52%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 246(0.07%) | 245(0.07%) | 0(0.00%) | 1(0.01%) | 336(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 237(0.07%) | 237(0.07%) | 0(0.00%) | 0(0.00%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ARP | udp_build_arp | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.IPAM_block | udp_ipam_block | 214(0.06%) | 212(0.06%) | 0(0.00%) | 2(0.01%) | 199(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ping | udp_build_ping | 164(0.05%) | 164(0.05%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 52(0.02%) | 50(0.01%) | 0(0.00%) | 2(0.01%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 316(0.09%) | 297(0.09%) | 0(0.00%) | 19(0.01%) | 564(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 184(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 370(0.11%) | 370(0.11%) | 0(0.00%) | 0(0.00%) | 470(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_1797 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 392(0.11%) | 392(0.11%) | 0(0.00%) | 0(0.00%) | 393(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 123(0.04%) | 123(0.04%) | 0(0.00%) | 0(0.00%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slaves | ipbus_example | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slave3 | ipbus_axi4_bridge | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trimac_fifo_block | eth_7s_rgmii | 1599(0.46%) | 1459(0.42%) | 125(0.07%) | 15(0.01%) | 2615(0.38%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (trimac_fifo_block) | eth_7s_rgmii | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_lite_controller | ethernet_mac_rgmii_axi_lite_sm | 141(0.04%) | 140(0.04%) | 0(0.00%) | 1(0.01%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (axi_lite_controller) | ethernet_mac_rgmii_axi_lite_sm | 141(0.04%) | 140(0.04%) | 0(0.00%) | 1(0.01%) | 169(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | update_speed_sync_inst | ethernet_mac_rgmii_sync_block__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_mac_reset_gen | ethernet_mac_rgmii_reset_sync__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trimac_read_fifo_2 | rgmii_rx_fifo_2 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 158(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst | rgmii_rx_fifo_2_axis_data_fifo_v2_0_8_top | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 158(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | rgmii_rx_fifo_2_xpm_fifo_axis | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 158(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | rgmii_rx_fifo_2_xpm_fifo_axis | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | rgmii_rx_fifo_2_xpm_cdc_sync_rst__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | rgmii_rx_fifo_2_xpm_fifo_base | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 156(0.02%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | rgmii_rx_fifo_2_xpm_fifo_base | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | rgmii_rx_fifo_2_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | rgmii_rx_fifo_2_xpm_fifo_reg_vec | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | rgmii_rx_fifo_2_xpm_fifo_reg_vec_0 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | rgmii_rx_fifo_2_xpm_cdc_gray__2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | rgmii_rx_fifo_2_xpm_memory_base | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | rdp_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized1 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | rgmii_rx_fifo_2_xpm_fifo_reg_bit | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized0_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized1_3 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | rgmii_rx_fifo_2_xpm_counter_updn__parameterized2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | rgmii_rx_fifo_2_xpm_fifo_rst | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | rgmii_rx_fifo_2_xpm_fifo_rst | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | rgmii_rx_fifo_2_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | rgmii_rx_fifo_2_xpm_cdc_sync_rst__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trimac_sup_block | ethernet_mac_rgmii_support | 1364(0.39%) | 1225(0.35%) | 125(0.07%) | 14(0.01%) | 2273(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trimac_sup_block) | ethernet_mac_rgmii_support | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tri_mode_ethernet_mac_i | ethernet_mac_rgmii | 1359(0.39%) | 1220(0.35%) | 125(0.07%) | 14(0.01%) | 2253(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ethernet_mac_rgmii_block | 1359(0.39%) | 1220(0.35%) | 125(0.07%) | 14(0.01%) | 2253(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi4_lite_ipif | ethernet_mac_rgmii_axi4_lite_ipif_wrapper | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (axi4_lite_ipif) | ethernet_mac_rgmii_axi4_lite_ipif_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_lite_top | ethernet_mac_rgmii_axi_lite_ipif | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_SLAVE_ATTACHMENT | ethernet_mac_rgmii_slave_attachment | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (I_SLAVE_ATTACHMENT) | ethernet_mac_rgmii_slave_attachment | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_DECODER | ethernet_mac_rgmii_address_decoder | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ethernet_mac_rgmii_core | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22 | 1275(0.37%) | 1136(0.33%) | 125(0.07%) | 14(0.01%) | 2110(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ethernet_mac_rgmii_core) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_filter_top | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap | 54(0.02%) | 37(0.01%) | 16(0.01%) | 1(0.01%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (addr_filter_top) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | address_filter_inst | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter | 54(0.02%) | 37(0.01%) | 16(0.01%) | 1(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (address_filter_inst) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_addr_filter | 52(0.02%) | 35(0.01%) | 16(0.01%) | 1(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resync_promiscuous_mode | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_80 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_update | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_81 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | flow | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_control | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 207(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (flow) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_control | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pfc_tx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_pfc_tx_cntl | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx_cntl | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_pause | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx_sync_req | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_enable | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_enable | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_cntl | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 84(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_pause | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_pause | 44(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_pause) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_pause | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_good_rx | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block_79 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_rx_gen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_gmii_mii_rx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_tx_gen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_gmii_mii_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | intc_control.intc | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_int_ctrl | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (intc_control.intc) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_int_ctrl | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sync[0].sync_request | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipic_mux_inst | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_ipic_mux | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 57(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | man_block.managen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_management | 189(0.05%) | 189(0.05%) | 0(0.00%) | 0(0.00%) | 239(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (man_block.managen) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_management | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | conf | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_config | 144(0.04%) | 144(0.04%) | 0(0.00%) | 0(0.00%) | 170(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mdio_enabled.phy | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_miim | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | man_reset.sync_bus2ip_reset_bus2ip_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | man_reset.sync_glbl_rstn_bus2ip_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_avb_tx_axi_intf.tx_axi_shim | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx_axi_intf | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_axi_shim | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx_axi_intf | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rxgen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx | 168(0.05%) | 159(0.05%) | 0(0.00%) | 9(0.01%) | 250(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rxgen) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_rx | 30(0.01%) | 21(0.01%) | 0(0.00%) | 9(0.01%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FCS_CHECK | ethernet_mac_rgmii_CRC32_8 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_CHECKER | ethernet_mac_rgmii_PARAM_CHECK | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_DECODER | ethernet_mac_rgmii_DECODE_FRAME | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX_SM | ethernet_mac_rgmii_STATE_MACHINES | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stats_block.statistics_counters | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_statistics_core | 400(0.12%) | 287(0.08%) | 109(0.06%) | 4(0.01%) | 828(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stats_block.statistics_counters) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_statistics_core | 294(0.08%) | 181(0.05%) | 109(0.06%) | 4(0.01%) | 296(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[0].fast_statistics | ethernet_mac_rgmii_increment_controller__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[0].fast_statistics) | ethernet_mac_rgmii_increment_controller__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_41 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[1].fast_statistics | ethernet_mac_rgmii_increment_controller__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[1].fast_statistics) | ethernet_mac_rgmii_increment_controller__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_40 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[2].fast_statistics | ethernet_mac_rgmii_increment_controller__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[2].fast_statistics) | ethernet_mac_rgmii_increment_controller__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_39 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fast_statistic_control[3].fast_statistics | ethernet_mac_rgmii_increment_controller__4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (fast_statistic_control[3].fast_statistics) | ethernet_mac_rgmii_increment_controller__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_38 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[10].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[10].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_31 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[4].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[4].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_37 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[5].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[5].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_36 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[6].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[6].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[7].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[7].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_34 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[8].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[8].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_33 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control1[9].frame_size_stats1 | ethernet_mac_rgmii_increment_controller__10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control1[9].frame_size_stats1) | ethernet_mac_rgmii_increment_controller__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_32 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[11].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[11].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_30 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[12].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[12].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_29 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[13].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__14 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[13].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[14].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__15 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[14].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[15].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[15].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_26 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[16].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[16].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | frame_size_bin_control2[17].frame_size_stats2 | ethernet_mac_rgmii_increment_controller__18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (frame_size_bin_control2[17].frame_size_stats2) | ethernet_mac_rgmii_increment_controller__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_24 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[18].general_statisics | ethernet_mac_rgmii_increment_controller__19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[18].general_statisics) | ethernet_mac_rgmii_increment_controller__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[19].general_statisics | ethernet_mac_rgmii_increment_controller__20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[19].general_statisics) | ethernet_mac_rgmii_increment_controller__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_22 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[20].general_statisics | ethernet_mac_rgmii_increment_controller__21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[20].general_statisics) | ethernet_mac_rgmii_increment_controller__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[21].general_statisics | ethernet_mac_rgmii_increment_controller__22 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[21].general_statisics) | ethernet_mac_rgmii_increment_controller__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[22].general_statisics | ethernet_mac_rgmii_increment_controller__23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[22].general_statisics) | ethernet_mac_rgmii_increment_controller__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[23].general_statisics | ethernet_mac_rgmii_increment_controller__24 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[23].general_statisics) | ethernet_mac_rgmii_increment_controller__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[24].general_statisics | ethernet_mac_rgmii_increment_controller__25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[24].general_statisics) | ethernet_mac_rgmii_increment_controller__25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[25].general_statisics | ethernet_mac_rgmii_increment_controller__26 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[25].general_statisics) | ethernet_mac_rgmii_increment_controller__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[26].general_statisics | ethernet_mac_rgmii_increment_controller__27 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[26].general_statisics) | ethernet_mac_rgmii_increment_controller__27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_15 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[27].general_statisics | ethernet_mac_rgmii_increment_controller__28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[27].general_statisics) | ethernet_mac_rgmii_increment_controller__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_14 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[28].general_statisics | ethernet_mac_rgmii_increment_controller__29 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[28].general_statisics) | ethernet_mac_rgmii_increment_controller__29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[29].general_statisics | ethernet_mac_rgmii_increment_controller__30 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[29].general_statisics) | ethernet_mac_rgmii_increment_controller__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[30].general_statisics | ethernet_mac_rgmii_increment_controller__31 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[30].general_statisics) | ethernet_mac_rgmii_increment_controller__31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[31].general_statisics | ethernet_mac_rgmii_increment_controller__32 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[31].general_statisics) | ethernet_mac_rgmii_increment_controller__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[32].general_statisics | ethernet_mac_rgmii_increment_controller__33 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[32].general_statisics) | ethernet_mac_rgmii_increment_controller__33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | general_statisic_control[33].general_statisics | ethernet_mac_rgmii_increment_controller | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (general_statisic_control[33].general_statisics) | ethernet_mac_rgmii_increment_controller | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_inc_vector | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_counter | ethernet_mac_rgmii_pre_accumulator__1 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_byte_counter) | ethernet_mac_rgmii_pre_accumulator__1 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2_68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_69 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_72 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_73 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_74 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_75 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_fragment_counter | ethernet_mac_rgmii_pre_accumulator | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_fragment_counter) | ethernet_mac_rgmii_pre_accumulator | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_42 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_44 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_45 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_46 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_47 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_48 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_undersized_counter | ethernet_mac_rgmii_pre_accumulator__3 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rx_undersized_counter) | ethernet_mac_rgmii_pre_accumulator__3 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_51 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_52 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_53 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_54 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_55 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_56 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_57 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_request | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_response | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_7 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_counter | ethernet_mac_rgmii_pre_accumulator__2 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_byte_counter) | ethernet_mac_rgmii_pre_accumulator__2 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SYNC_STATS_RESET | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized2_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[0].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_60 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[1].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_61 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[2].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[3].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_63 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[4].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[5].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[6].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_66 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | accum_gray_resync[7].sync_accum_gray_i | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_block__parameterized1_67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_axi_rx_rstn_rx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_rx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_tx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_rx_rst_mgmt_rx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_tx_rst_mgmt_tx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_stats_reset | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset__parameterized0_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_axi_rstn_tx_clk | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_sync_reset_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txgen | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx | 160(0.05%) | 159(0.05%) | 0(0.00%) | 1(0.01%) | 243(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txgen) | ethernet_mac_rgmii_tri_mode_ethernet_mac_v9_0_22_tx | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TX_SM1 | ethernet_mac_rgmii_TX_STATE_MACH | 158(0.05%) | 158(0.05%) | 0(0.00%) | 0(0.00%) | 236(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TX_SM1) | ethernet_mac_rgmii_TX_STATE_MACH | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 204(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CRCGEN | ethernet_mac_rgmii_CRC32_8__1 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rgmii_interface | ethernet_mac_rgmii_rgmii_v2_0_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | vector_decode_inst | ethernet_mac_rgmii_vector_decode | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 89(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tri_mode_ethernet_mac_support_resets_i | ethernet_mac_rgmii_support_resets | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tri_mode_ethernet_mac_support_resets_i) | ethernet_mac_rgmii_support_resets | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | idelayctrl_reset_gen | ethernet_mac_rgmii_reset_sync__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_mac_reset_gen | ethernet_mac_rgmii_reset_sync__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shelf_addr_sel | ip_dual_decode | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | phy_reset | system_top_reset__parameterized1 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pp_out_fifo_6432 | packet_fifo__xdcDup__4 | 1597(0.46%) | 1324(0.38%) | 0(0.00%) | 273(0.16%) | 2723(0.39%) | 12(1.02%) | 1(0.04%) | 0(0.00%) | | (pp_out_fifo_6432) | packet_fifo__xdcDup__4 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ILA_packet_fifo | ila_fifo_HD604 | 1399(0.40%) | 1126(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ILA_packet_fifo) | ila_fifo_HD604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_fifo_ila_v6_2_12_ila_HD605 | 1399(0.40%) | 1126(0.33%) | 0(0.00%) | 273(0.16%) | 2263(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_fifo_ila_v6_2_12_ila_HD605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_fifo_ila_v6_2_12_ila_core_HD606 | 1398(0.40%) | 1125(0.32%) | 0(0.00%) | 273(0.16%) | 2257(0.33%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_fifo_ila_v6_2_12_ila_core_HD606 | 85(0.02%) | 0(0.00%) | 0(0.00%) | 85(0.05%) | 212(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_fifo_ila_v6_2_12_ila_trace_memory_HD607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_fifo_blk_mem_gen_v8_4_5_HD608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_synth_HD609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_top_HD610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_generic_cstr_HD611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width_HD612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper_HD613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized0_HD614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized0_HD615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized1_HD616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized1_HD617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized2_HD618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized2_HD619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_width__parameterized3_HD620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_fifo_blk_mem_gen_v8_4_5_blk_mem_gen_prim_wrapper__parameterized3_HD621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD622 | 78(0.02%) | 31(0.01%) | 0(0.00%) | 47(0.03%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_fifo_ila_v6_2_12_ila_cap_ctrl_legacy_HD622 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_fifo_ltlib_v1_0_0_cfglut6__parameterized0_HD623 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_fifo_ltlib_v1_0_0_cfglut7_HD624 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_fifo_ltlib_v1_0_0_cfglut7__1_HD625 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD626 | 63(0.02%) | 26(0.01%) | 0(0.00%) | 37(0.02%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_fifo_ila_v6_2_12_ila_cap_addrgen_HD626 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_fifo_ltlib_v1_0_0_cfglut6__1_HD627 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD628 | 31(0.01%) | 18(0.01%) | 0(0.00%) | 13(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_fifo_ila_v6_2_12_ila_cap_sample_counter_HD628 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_fifo_ltlib_v1_0_0_cfglut4__1_HD629 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__1_HD630 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_fifo_ltlib_v1_0_0_cfglut6_HD631 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_fifo_ltlib_v1_0_0_match_nodelay__1_HD632 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD633 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_70_HD633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD634 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_71_HD634 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_72_HD635 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_73_HD636 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD637 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_fifo_ila_v6_2_12_ila_cap_window_counter_HD637 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_fifo_ltlib_v1_0_0_cfglut4_HD638 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5_HD639 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_fifo_ltlib_v1_0_0_cfglut5__2_HD640 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_fifo_ltlib_v1_0_0_match_nodelay_HD641 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD642 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_HD642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD643 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_HD643 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD644 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD645 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_fifo_ltlib_v1_0_0_match_nodelay__2_HD646 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD647 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_nodelay_66_HD647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD648 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized3_67_HD648 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized1_68_HD649 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized2_69_HD650 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_fifo_ila_v6_2_12_ila_register_HD651 | 910(0.26%) | 909(0.26%) | 0(0.00%) | 1(0.01%) | 1310(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_fifo_ila_v6_2_12_ila_register_HD651 | 327(0.09%) | 326(0.09%) | 0(0.00%) | 1(0.01%) | 162(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s_HD652 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[10].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized9_HD653 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[11].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized10_HD654 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[12].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized11_HD655 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized0_HD656 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized1_HD657 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized2_HD658 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized3_HD659 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized4_HD660 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized5_HD661 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized6_HD662 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized7_HD663 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized8_HD664 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized12_HD665 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_fifo_xsdbs_v1_0_2_xsdbs_HD666 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_fifo_xsdbs_v1_0_2_reg__parameterized50_HD667 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_62_HD668 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_fifo_xsdbs_v1_0_2_reg__parameterized51_HD669 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_61_HD670 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_fifo_xsdbs_v1_0_2_reg__parameterized52_HD671 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_60_HD672 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_fifo_xsdbs_v1_0_2_reg__parameterized53_HD673 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_59_HD674 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_fifo_xsdbs_v1_0_2_reg__parameterized54_HD675 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_58_HD676 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_fifo_xsdbs_v1_0_2_reg__parameterized55_HD677 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_57_HD678 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_fifo_xsdbs_v1_0_2_reg__parameterized35_HD679 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_65_HD680 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_fifo_xsdbs_v1_0_2_reg__parameterized36_HD681 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized0_HD682 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_fifo_xsdbs_v1_0_2_reg__parameterized37_HD683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_64_HD684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_fifo_xsdbs_v1_0_2_reg__parameterized56_HD685 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_56_HD686 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_fifo_xsdbs_v1_0_2_reg__parameterized57_HD687 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_55_HD688 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_fifo_xsdbs_v1_0_2_reg__parameterized58_HD689 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl__parameterized1_HD690 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_fifo_xsdbs_v1_0_2_reg__parameterized59_HD691 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_54_HD692 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_fifo_xsdbs_v1_0_2_reg__parameterized60_HD693 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_53_HD694 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_fifo_xsdbs_v1_0_2_reg__parameterized61_HD695 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_52_HD696 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_fifo_xsdbs_v1_0_2_reg__parameterized63_HD697 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_51_HD698 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_fifo_xsdbs_v1_0_2_reg__parameterized65_HD699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_50_HD700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_fifo_xsdbs_v1_0_2_reg__parameterized68_HD701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_49_HD702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_fifo_xsdbs_v1_0_2_reg__parameterized38_HD703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_63_HD704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_fifo_xsdbs_v1_0_2_reg_p2s__parameterized13_HD705 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_fifo_xsdbs_v1_0_2_reg_stream_HD706 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_fifo_xsdbs_v1_0_2_reg_ctl_HD707 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD708 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_fifo_xsdbs_v1_0_2_reg_stream__parameterized0_HD708 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_fifo_xsdbs_v1_0_2_reg_stat_HD709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD710 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_fifo_ila_v6_2_12_ila_reset_ctrl_HD710 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection_HD711 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__2_HD712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__3_HD713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer__1_HD714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_fifo_ltlib_v1_0_0_async_edge_xfer_HD715 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_fifo_ltlib_v1_0_0_rising_edge_detection__1_HD716 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_fifo_ila_v6_2_12_ila_trigger_HD717 | 224(0.06%) | 86(0.02%) | 0(0.00%) | 138(0.08%) | 380(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_fifo_ila_v6_2_12_ila_trigger_HD717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_fifo_ltlib_v1_0_0_match_HD718 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_fifo_ltlib_v1_0_0_match_HD718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA_HD719 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA_HD719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA_HD720 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA_HD720 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_47_HD721 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_48_HD722 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_fifo_ila_v6_2_12_ila_trig_match_HD723 | 214(0.06%) | 85(0.02%) | 0(0.00%) | 129(0.07%) | 364(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_fifo_ila_v6_2_12_ila_trig_match_HD723 | 85(0.02%) | 85(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD724 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized0_HD724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD725 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 129(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized0_HD725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD726 | 33(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.02%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized0_HD726 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_39_HD727 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_40_HD728 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_41_HD729 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_42_HD730 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_43_HD731 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_44_HD732 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_45_HD733 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_46_HD734 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[10].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD735 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[10].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__7_HD735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD736 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_3_HD736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD737 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_4_HD737 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD738 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[11].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD739 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[11].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__8_HD739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD740 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_0_HD740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD741 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_1_HD741 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD742 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[12].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD743 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[12].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1_HD743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD744 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_HD744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD745 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_HD745 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD746 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD747 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__1_HD747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD748 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_36_HD748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD749 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_37_HD749 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_38_HD750 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD751 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__2_HD751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD752 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_33_HD752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD753 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_34_HD753 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_35_HD754 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD755 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__3_HD755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD756 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_30_HD756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD757 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_31_HD757 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_32_HD758 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD759 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__4_HD759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD760 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_27_HD760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD761 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_28_HD761 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_29_HD762 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD763 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__1_HD763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD764 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_21_HD764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD765 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_22_HD765 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_23_HD766 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_24_HD767 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_25_HD768 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_26_HD769 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD770 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2__2_HD770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD771 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_15_HD771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD772 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_16_HD772 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_17_HD773 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_18_HD774 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_19_HD775 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_20_HD776 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD777 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__5_HD777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD778 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_12_HD778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD779 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_13_HD779 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_14_HD780 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD781 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 66(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized2_HD781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD782 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized2_HD782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD783 | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized2_HD783 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_HD784 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_9_HD785 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice_10_HD786 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_11_HD787 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD788 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_fifo_ltlib_v1_0_0_match__parameterized1__6_HD788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD789 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_fifo_ltlib_v1_0_0_allx_typeA__parameterized1_6_HD789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD790 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_fifo_ltlib_v1_0_0_all_typeA__parameterized1_7_HD790 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_fifo_ltlib_v1_0_0_all_typeA_slice__parameterized0_8_HD791 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_fifo_ltlib_v1_0_0_generic_memrd_HD792 | 92(0.03%) | 90(0.03%) | 0(0.00%) | 2(0.01%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_width_conv | axis_dwidth_64_32_HD806 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD807 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 103(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axis_dwidth_converter_HD807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_downsizer_conversion.axisc_downsizer_0 | axis_dwidth_64_32_axis_dwidth_converter_v1_1_25_axisc_downsizer_HD808 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 102(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | main_fifo | axis_data_fifo_0_HD885 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (main_fifo) | axis_data_fifo_0_HD885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | axis_data_fifo_0_axis_data_fifo_v2_0_8_top_HD886 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gen_fifo.xpm_fifo_axis_inst | axis_data_fifo_0_xpm_fifo_axis_HD887 | 172(0.05%) | 172(0.05%) | 0(0.00%) | 0(0.00%) | 355(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (gen_fifo.xpm_fifo_axis_inst) | axis_data_fifo_0_xpm_fifo_axis_HD887 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_rst_sync.xpm_cdc_sync_rst_inst | axis_data_fifo_0_xpm_cdc_sync_rst__3_HD888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_base_inst | axis_data_fifo_0_xpm_fifo_base_HD889 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 353(0.05%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | (xpm_fifo_base_inst) | axis_data_fifo_0_xpm_fifo_base_HD889 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized1_HD890 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rd_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray_HD891 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_HD892 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.rpw_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_HD893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg | axis_data_fifo_0_xpm_fifo_reg_vec_0_HD894 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wpr_gray_reg_dc | axis_data_fifo_0_xpm_fifo_reg_vec__parameterized0_1_HD895 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_dc_inst | axis_data_fifo_0_xpm_cdc_gray__parameterized0_HD896 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_cdc_pntr.wr_pntr_cdc_inst | axis_data_fifo_0_xpm_cdc_gray__2_HD897 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_fwft.rdpp1_inst | axis_data_fifo_0_xpm_counter_updn_HD898 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_sdpram.xpm_memory_base_inst | axis_data_fifo_0_xpm_memory_base_HD899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | rdp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_HD900 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rdpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_HD901 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rst_d1_inst | axis_data_fifo_0_xpm_fifo_reg_bit_HD902 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrp_inst | axis_data_fifo_0_xpm_counter_updn__parameterized0_2_HD903 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp1_inst | axis_data_fifo_0_xpm_counter_updn__parameterized1_3_HD904 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wrpp2_inst | axis_data_fifo_0_xpm_counter_updn__parameterized2_HD905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xpm_fifo_rst_inst | axis_data_fifo_0_xpm_fifo_rst_HD906 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xpm_fifo_rst_inst) | axis_data_fifo_0_xpm_fifo_rst_HD906 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.rrst_wr_inst | axis_data_fifo_0_xpm_cdc_sync_rst_HD907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_rst_ic.wrst_rd_inst | axis_data_fifo_0_xpm_cdc_sync_rst__4_HD908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | proc_clock_gen | packet_processor_clock | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | packet_processor_clock_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_top | system_top_reset | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_pwr | reset_count | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | top_vio | vio_top | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 331(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (top_vio) | vio_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_top_vio_v3_0_22_vio | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 331(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_top_vio_v3_0_22_vio | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_top_vio_v3_0_22_decoder | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_top_vio_v3_0_22_probe_in_one | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 81(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_top_vio_v3_0_22_probe_out_all | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_top_vio_v3_0_22_probe_out_all | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[1].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[2].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[3].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[4].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[5].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[6].PROBE_OUT0_INST | vio_top_vio_v3_0_22_probe_out_one_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_top_xsdbs_v1_0_2_xsdbs | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_source_sel | vio_ttc_HD26 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ttc_source_sel) | vio_ttc_HD26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | vio_ttc_vio_v3_0_22_vio_HD27 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 242(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (inst) | vio_ttc_vio_v3_0_22_vio_HD27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DECODER_INST | vio_ttc_vio_v3_0_22_decoder_HD28 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_IN_INST | vio_ttc_vio_v3_0_22_probe_in_one_HD29 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PROBE_OUT_ALL_INST | vio_ttc_vio_v3_0_22_probe_out_all_HD30 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (PROBE_OUT_ALL_INST) | vio_ttc_vio_v3_0_22_probe_out_all_HD30 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | G_PROBE_OUT[0].PROBE_OUT0_INST | vio_ttc_vio_v3_0_22_probe_out_one_HD31 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | vio_ttc_xsdbs_v1_0_2_xsdbs_HD32 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +---------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+----------------+---------------+-------------+-------------+----------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining