## Repository info
- Merge request number: 124
- Branch name: 113-fifo_experiment_2

## MR Description
Closes #113

The input fifo FWFT (first word fall through) seems to have been malfunctioning.  

Size of the input fifos has been reduced from 4k x 64 to 2k x 64 for the phase-2 versions only.  This seems to allow the fifos to operate properly.


## Changelog


## rod_efex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.102171       |
| TNS:          | 0.000000       |
| WHS:          | 0.028144       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    37061    |    0         |   0              |    346400        |    10.70     |   
| Slice  Registers |    51597    |    81        |   0              |    692800        |    7.45      |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    86366    |   0         |   0              |    346400        |    24.93     |    
| Slice  Registers |    135058   |   0         |   0              |    692800        |    19.49     |    
| Block  RAM       Tile |        393 |         0   |              0    |             1180 |         33.31
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | a819541        | 1.0.2       |
| Constraints       | 4fb58450       | 1.0.1       |
| IPbus XML         | 8f37344        | 1.0.1       |
| Top Directory     | 989ee7c        | 0.5.24      |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_efex | a819541        | 1.0.2       |
| **Lib:** others   | 1850910        | 1.0.2       |



</details>
</p>

 
## rod_jfex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.208195       |
| TNS:          | 0.000000       |
| WHS:          | 0.024629       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    52190    |    0         |   0              |    346400        |    15.07     |   
| Slice  Registers |    76615    |    81        |   0              |    692800        |    11.06     |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex Implementation Utilization report


                                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         --- |              ---  |             ---  |              
| Slice  LUTs      |    129481   |     0         |   0              |    346400        |    37.38     |    
| Slice  Registers |    213212   |     0         |   0              |    692800        |    30.78     |    
| Block  RAM       Tile |        654.5 |         0   |              0    |             1180 |         55.47
| DSPs   |         0    |        0     |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |     111       |   0              |    600           |    18.50     |    
                                                                                                           
## rod_jfex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 4830a12        | 1.0.2       |
| Constraints       | 4fb58450       | 1.0.1       |
| IPbus XML         | 8f37344        | 1.0.1       |
| Top Directory     | 276b635        | 1.0.1       |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_jfex | 4830a12        | 1.0.2       |
| **Lib:** others   | ca73900        | 1.0.2       |



</details>
</p>

 
## rod_efex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.028852       |
| TNS:          | 0.000000       |
| WHS:          | 0.048753       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    44438    |    0         |   0              |    346400        |    12.83     |   
| Slice  Registers |    59583    |    81        |   0              |    692800        |    8.60      |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex_p2 Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    119065   |   0         |   0              |    346400        |    34.37     |    
| Slice  Registers |    168119   |   0         |   0              |    692800        |    24.27     |    
| Block  RAM       Tile |        356 |         0   |              0    |             1180 |         30.17
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | 5dca195        | 1.0.2       |
| Constraints          | bf5742a2       | 1.0.1       |
| IPbus XML            | 8f37344        | 1.0.1       |
| Top Directory        | 4a18e6f        | 1.0.1       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_efex_p2 | 5dca195        | 1.0.2       |
| **Lib:** others      | ca73900        | 1.0.2       |



</details>
</p>

 
## rod_jfex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.004519       |
| TNS:          | 0.000000       |
| WHS:          | 0.049388       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    60440    |    0         |   0              |    346400        |    17.45     |   
| Slice  Registers |    86095    |    81        |   0              |    692800        |    12.43     |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex_p2 Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    170794   |   0         |   0              |    346400        |    49.31     |    
| Slice  Registers |    245471   |   0         |   0              |    692800        |    35.43     |    
| Block  RAM       Tile |        535 |         0   |              0    |             1180 |         45.34
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_jfex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | 5dca195        | 1.0.2       |
| Constraints          | dde9177c       | 1.0.1       |
| IPbus XML            | 8f37344        | 1.0.1       |
| Top Directory        | 276b635        | 1.0.1       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_jfex_p2 | 5dca195        | 1.0.2       |
| **Lib:** others      | ca73900        | 1.0.2       |



</details>
</p>