Index of /efex/firmware/ROD/official/v1.0.3/rod_jfex_p2-v1.0.3/reports

Icon  Name                                                   Last modified      Size  Description
[PARENTDIR] Parent Directory - [   ] fifo1KB_34bit_utilization_synth.rpt 2024-04-09 17:03 8.2K [   ] ila_2_utilization_synth.rpt 2024-04-09 17:03 8.4K [TXT] hierarchical_utilization.txt 2024-04-09 17:03 6.2M [   ] ila_fullmode_utilization_synth.rpt 2024-04-09 17:03 8.5K [   ] ttc_header_fifo_utilization_synth.rpt 2024-04-09 17:03 8.2K [TXT] ila_clk_cross_fifo_synth_1.log 2024-04-09 17:03 232K [TXT] vio_ttc_synth_1.log 2024-04-09 17:03 32K [   ] top_rod_jfex_p2_utilization_synth.rpt 2024-04-09 17:03 11K [TXT] axis_input_fifo_synth_1.log 2024-04-09 17:03 49K [   ] aurora_in_fifo_utilization_synth.rpt 2024-04-09 17:03 8.2K [   ] rod_RO_Tx_utilization_synth.rpt 2024-04-09 17:03 8.3K [   ] ethernet_mac_rgmii_utilization_synth.rpt 2024-04-09 17:03 9.1K [   ] rgmii_rx_fifo_2_utilization_synth.rpt 2024-04-09 17:03 8.0K [TXT] ila_l1id_cont_synth_1.log 2024-04-09 17:03 230K [TXT] axis_dwidth_64_32_synth_1.log 2024-04-09 17:03 32K [   ] ila_ev_builder_utilization_synth.rpt 2024-04-09 17:03 8.5K [   ] MGT_combined_ttc_rx_utilization_synth.rpt 2024-04-09 17:03 8.4K [   ] vio_ttc_utilization_synth.rpt 2024-04-09 17:03 7.8K [TXT] synth_1.log 2024-04-09 17:03 1.1M [   ] packet_processor_clock_utilization_synth.rpt 2024-04-09 17:03 7.7K [   ] aurora_fifo_in_ila_utilization_synth.rpt 2024-04-09 17:03 8.5K [TXT] dwidth_convert_synth_1.log 2024-04-09 17:03 31K [TXT] ila_fullmode_synth_1.log 2024-04-09 17:03 230K [TXT] axis_data_fifo_0_synth_1.log 2024-04-09 17:03 47K [   ] ila_1_utilization_synth.rpt 2024-04-09 17:03 8.3K [   ] vio_ip_address_utilization_synth.rpt 2024-04-09 17:03 7.8K [   ] ila_l1id_cont_utilization_synth.rpt 2024-04-09 17:03 8.4K [TXT] fm_status_fifo_synth_1.log 2024-04-09 17:03 50K [   ] axis_data_fifo_0_utilization_synth.rpt 2024-04-09 17:03 8.2K [TXT] vio_0_synth_1.log 2024-04-09 17:03 531 [TXT] ila_fifo_synth_1.log 2024-04-09 17:03 229K [TXT] ila_ttc_out_synth_1.log 2024-04-09 17:03 223K [   ] dwidth_convert_utilization_synth.rpt 2024-04-09 17:03 7.8K [TXT] vio_top_synth_1.log 2024-04-09 17:03 33K [   ] vio_fullmode_reset_utilization_synth.rpt 2024-04-09 17:03 7.9K [TXT] rod_RO_Tx_synth_1.log 2024-04-09 17:03 51K [   ] ila_mgtfsm_utilization_synth.rpt 2024-04-09 17:03 8.4K [TXT] ila_2_synth_1.log 2024-04-09 17:03 231K [TXT] aurora_1ln_rx_lpm_synth_1.log 2024-04-09 17:03 132K [TXT] ila_1_synth_1.log 2024-04-09 17:03 217K [TXT] MGT_combined_ttc_rx_synth_1.log 2024-04-09 17:03 63K [   ] aurora_1ln_rx_lpm_utilization_synth.rpt 2024-04-09 17:03 8.4K [TXT] rgmii_rx_fifo_2_synth_1.log 2024-04-09 17:03 42K [   ] top_rod_jfex_p2_io_placed.rpt 2024-04-09 17:03 607K [TXT] aurora_fifo_in_ila_synth_1.log 2024-04-09 17:03 233K [TXT] DPram_32b_synth_1.log 2024-04-09 17:03 35K [TXT] bulk_data_fifo_synth_1.log 2024-04-09 17:03 41K [   ] axis_input_fifo_utilization_synth.rpt 2024-04-09 17:03 8.0K [TXT] ttc_header_fifo_synth_1.log 2024-04-09 17:03 52K [   ] ila_fifo_utilization_synth.rpt 2024-04-09 17:03 8.4K [   ] ila_ttc_out_utilization_synth.rpt 2024-04-09 17:03 8.5K [TXT] aurora_fifo_out_ila_synth_1.log 2024-04-09 17:03 226K [   ] fm_status_fifo_utilization_synth.rpt 2024-04-09 17:03 8.2K [   ] aurora_fifo_out_ila_utilization_synth.rpt 2024-04-09 17:03 8.4K [TXT] vio_ip_address_synth_1.log 2024-04-09 17:03 33K [   ] axis_dwidth_64_32_utilization_synth.rpt 2024-04-09 17:03 7.8K [TXT] event_builder_fifo_synth_1.log 2024-04-09 17:03 583 [TXT] ila_ttc_in_synth_1.log 2024-04-09 17:03 232K [TXT] ethernet_mac_rgmii_synth_1.log 2024-04-09 17:03 88K [TXT] fifo1KB_34bit_synth_1.log 2024-04-09 17:03 49K [TXT] ila_mgtfsm_synth_1.log 2024-04-09 17:03 223K [TXT] ila_ev_builder_synth_1.log 2024-04-09 17:03 246K [   ] processor_in_fifo_utilization_synth.rpt 2024-04-09 17:03 8.3K [   ] bulk_data_fifo_utilization_synth.rpt 2024-04-09 17:03 8.0K [   ] clk_wiz_240_utilization_synth.rpt 2024-04-09 17:03 7.6K [   ] ila_ttc_in_utilization_synth.rpt 2024-04-09 17:03 8.4K [   ] rod_ROctrl_mux_ila_utilization_synth.rpt 2024-04-09 17:03 8.4K [   ] ila_clk_cross_fifo_utilization_synth.rpt 2024-04-09 17:03 8.5K [   ] top_rod_jfex_p2_drc_opted.rpt 2024-04-09 17:03 41K [TXT] impl_1.log 2024-04-09 17:03 390K [   ] top_rod_jfex_p2_utilization_placed.rpt 2024-04-09 17:03 15K [   ] vio_top_utilization_synth.rpt 2024-04-09 17:03 7.8K [TXT] rod_ROctrl_mux_ila_synth_1.log 2024-04-09 17:03 223K [TXT] vio_fullmode_reset_synth_1.log 2024-04-09 17:03 33K [   ] DPram_32b_utilization_synth.rpt 2024-04-09 17:03 7.6K [TXT] processor_in_fifo_synth_1.log 2024-04-09 17:03 48K [TXT] aurora_in_fifo_synth_1.log 2024-04-09 17:03 51K [TXT] packet_processor_clock_synth_1.log 2024-04-09 17:03 22K [TXT] clk_wiz_240_synth_1.log 2024-04-09 17:03 21K [   ] top_rod_jfex_p2_control_sets_placed.rpt 2024-04-09 17:03 6.1M