*** Running vivado with args -log ethernet_mac_rgmii.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ethernet_mac_rgmii.tcl WARNING: Default location for XILINX_HLS not found ****** Vivado v2022.1 (64-bit) **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022 **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source ethernet_mac_rgmii.tcl -notrace create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3021.816 ; gain = 2.020 ; free physical = 53267 ; free virtual = 89125 Command: synth_design -top ethernet_mac_rgmii -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 15396 WARNING: [Synth 8-9501] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:4023] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3038.043 ; gain = 0.000 ; free physical = 50215 ; free virtual = 86105 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.vhd:163] WARNING: [Synth 8-3819] Generic 'GLOBAL_DATE' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_TIME' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'ROD_JFEX_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'ROD_JFEX_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'OTHERS_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'OTHERS_SHA' not present in instantiated entity will be ignored INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_block' declared at '/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_block.vhd:123' bound to instance 'U0' of component 'ethernet_mac_rgmii_block' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.vhd:274] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_block' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_block.vhd:220] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_rgmii_v2_0_if' declared at '/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:73' bound to instance 'rgmii_interface' of component 'ethernet_mac_rgmii_rgmii_v2_0_if' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_block.vhd:616] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_rgmii_v2_0_if' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:123] INFO: [Synth 8-113] binding component instance 'mdio_iobuf' to cell 'IOBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:169] INFO: [Synth 8-113] binding component instance 'mdc_obuf_i' to cell 'OBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:178] INFO: [Synth 8-113] binding component instance 'rgmii_txc_obuf_i' to cell 'OBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:188] INFO: [Synth 8-113] binding component instance 'rgmii_tx_ctl_obuf_i' to cell 'OBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:194] INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:201] INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:201] INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:201] INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:201] INFO: [Synth 8-113] binding component instance 'rgmii_rxc_ibuf_i' to cell 'IBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:208] INFO: [Synth 8-113] binding component instance 'rgmii_rx_ctl_ibuf_i' to cell 'IBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:214] INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:221] INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:221] INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:221] INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:221] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string INFO: [Synth 8-113] binding component instance 'rgmii_txc_ddr' to cell 'ODDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:243] Parameter ODELAY_TYPE bound to: FIXED - type: string Parameter ODELAY_VALUE bound to: 12 - type: integer INFO: [Synth 8-113] binding component instance 'delay_rgmii_tx_clk' to cell 'ODELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:259] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string INFO: [Synth 8-113] binding component instance 'rgmii_txd_out' to cell 'ODDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:298] Parameter ODELAY_TYPE bound to: FIXED - type: string Parameter ODELAY_VALUE bound to: 0 - type: integer INFO: [Synth 8-113] binding component instance 'delay_rgmii_txd' to cell 'ODELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:312] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string INFO: [Synth 8-113] binding component instance 'rgmii_txd_out' to cell 'ODDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:298] Parameter ODELAY_TYPE bound to: FIXED - type: string Parameter ODELAY_VALUE bound to: 0 - type: integer INFO: [Synth 8-113] binding component instance 'delay_rgmii_txd' to cell 'ODELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:312] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string INFO: [Synth 8-113] binding component instance 'rgmii_txd_out' to cell 'ODDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:298] Parameter ODELAY_TYPE bound to: FIXED - type: string Parameter ODELAY_VALUE bound to: 0 - type: integer INFO: [Synth 8-113] binding component instance 'delay_rgmii_txd' to cell 'ODELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:312] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string INFO: [Synth 8-113] binding component instance 'rgmii_txd_out' to cell 'ODDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:298] Parameter ODELAY_TYPE bound to: FIXED - type: string Parameter ODELAY_VALUE bound to: 0 - type: integer INFO: [Synth 8-113] binding component instance 'delay_rgmii_txd' to cell 'ODELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:312] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string INFO: [Synth 8-113] binding component instance 'rgmii_tx_ctl_out' to cell 'ODDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:333] Parameter ODELAY_TYPE bound to: FIXED - type: string Parameter ODELAY_VALUE bound to: 0 - type: integer INFO: [Synth 8-113] binding component instance 'delay_rgmii_tx_ctl' to cell 'ODELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:347] INFO: [Synth 8-113] binding component instance 'bufio_rgmii_rx_clk' to cell 'BUFIO' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:372] INFO: [Synth 8-113] binding component instance 'bufr_rgmii_rx_clk' to cell 'BUFR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:379] Parameter IDELAY_TYPE bound to: FIXED - type: string INFO: [Synth 8-113] binding component instance 'delay_rgmii_rx_ctl' to cell 'IDELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:402] Parameter IDELAY_TYPE bound to: FIXED - type: string INFO: [Synth 8-113] binding component instance 'delay_rgmii_rxd' to cell 'IDELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:422] Parameter IDELAY_TYPE bound to: FIXED - type: string INFO: [Synth 8-113] binding component instance 'delay_rgmii_rxd' to cell 'IDELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:422] Parameter IDELAY_TYPE bound to: FIXED - type: string INFO: [Synth 8-113] binding component instance 'delay_rgmii_rxd' to cell 'IDELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:422] Parameter IDELAY_TYPE bound to: FIXED - type: string INFO: [Synth 8-113] binding component instance 'delay_rgmii_rxd' to cell 'IDELAYE2' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:422] Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string INFO: [Synth 8-113] binding component instance 'rgmii_rx_data_in' to cell 'IDDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:447] Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string INFO: [Synth 8-113] binding component instance 'rgmii_rx_data_in' to cell 'IDDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:447] Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string INFO: [Synth 8-113] binding component instance 'rgmii_rx_data_in' to cell 'IDDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:447] Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string INFO: [Synth 8-113] binding component instance 'rgmii_rx_data_in' to cell 'IDDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:447] Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string INFO: [Synth 8-113] binding component instance 'rgmii_rx_ctl_in' to cell 'IDDR' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:463] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_rgmii_v2_0_if' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd:123] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_axi4_lite_ipif_wrapper' declared at '/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_axi4_lite_ipif_wrapper.vhd:62' bound to instance 'axi4_lite_ipif' of component 'ethernet_mac_rgmii_axi4_lite_ipif_wrapper' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_block.vhd:663] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_axi4_lite_ipif_wrapper' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_axi4_lite_ipif_wrapper.vhd:107] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-256] done synthesizing module 'address_decoder' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_axi4_lite_ipif_wrapper' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_axi4_lite_ipif_wrapper.vhd:107] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_vector_decode' declared at '/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:72' bound to instance 'vector_decode_inst' of component 'ethernet_mac_rgmii_vector_decode' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_block.vhd:702] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_vector_decode' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:95] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_vector_decode' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:95] Parameter C_S_AXI_ADDR_WIDTH bound to: 12 - type: integer Parameter C_PHYSICAL_INTERFACE bound to: RGMII - type: string Parameter C_INTERNAL_MODE_TYPE bound to: BASEX - type: string Parameter C_HALF_DUPLEX bound to: 0 - type: integer Parameter C_HAS_HOST bound to: 1 - type: integer Parameter C_ADD_FILTER bound to: 0 - type: integer Parameter C_AT_ENTRIES bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_HAS_2G5 bound to: 0 - type: integer Parameter C_MAC_SPEED bound to: SPEED_1000_MBPS - type: string Parameter C_HAS_STATS bound to: 1 - type: integer Parameter C_NUM_STATS bound to: 34 - type: integer Parameter C_CNTR_RST bound to: 1 - type: integer Parameter C_STATS_WIDTH bound to: 64 - type: integer Parameter C_AVB bound to: 0 - type: integer Parameter C_RX_VEC_WIDTH bound to: 79 - type: integer Parameter C_TX_VEC_WIDTH bound to: 79 - type: integer Parameter C_1588 bound to: 0 - type: integer Parameter C_TX_INBAND_CF_ENABLE bound to: 0 - type: integer Parameter C_RX_INBAND_TS_ENABLE bound to: 0 - type: integer Parameter C_PFC bound to: 0 - type: integer Parameter C_HAS_MDIO bound to: 1 - type: integer Parameter C_DEVICE_FAMILY_US bound to: 0 - type: integer INFO: [Synth 8-3491] module 'tri_mode_ethernet_mac_v9_0_22' declared at '/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/hdl/tri_mode_ethernet_mac_v9_0_rfs.v:18035' bound to instance 'ethernet_mac_rgmii_core' of component 'tri_mode_ethernet_mac_v9_0_22' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_block.vhd:732] INFO: [Synth 8-6157] synthesizing module 'LUT4' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6155] done synthesizing module 'LUT4' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized0' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized0' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized1' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized1' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized2' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized2' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized3' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized3' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62762] INFO: [Synth 8-6157] synthesizing module 'RAM64X1D' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:98539] INFO: [Synth 8-6155] done synthesizing module 'RAM64X1D' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:98539] INFO: [Synth 8-6157] synthesizing module 'LUT3' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6155] done synthesizing module 'LUT3' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized0' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized0' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized1' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized1' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized2' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized2' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:62720] INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:105998] INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (0#1) [/opt/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:105998] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_block' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_block.vhd:220] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.vhd:163] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA WARNING: [Synth 8-6014] Unused sequential element tx_byte_valid_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:226] WARNING: [Synth 8-6014] Unused sequential element tx_attemps_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:227] WARNING: [Synth 8-6014] Unused sequential element tx_excessive_collision_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:228] WARNING: [Synth 8-6014] Unused sequential element tx_late_collision_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:229] WARNING: [Synth 8-6014] Unused sequential element tx_excessive_deferral_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:230] WARNING: [Synth 8-6014] Unused sequential element tx_deferred_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:231] WARNING: [Synth 8-6014] Unused sequential element rx_byte_valid_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:280] WARNING: [Synth 8-6014] Unused sequential element rx_out_of_bounds_error_reg_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:282] WARNING: [Synth 8-6014] Unused sequential element rx_bad_frame_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:287] WARNING: [Synth 8-6014] Unused sequential element rx_bad_frame_reg_reg was removed. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/statistics/ethernet_mac_rgmii_vector_decode.vhd:325] WARNING: [Synth 8-7129] Port rx_filter_enable[0] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port rx_avb_enable[2] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port rx_avb_enable[1] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port rx_avb_enable[0] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[16] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[15] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[14] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[13] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[12] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[11] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[10] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[9] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[8] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[7] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[6] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[1] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[0] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[31] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[30] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[29] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[28] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[27] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[26] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[25] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[24] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[23] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[22] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[21] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[20] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[19] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[18] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[17] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[16] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[15] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[14] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[13] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[12] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[11] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[10] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[9] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[8] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[7] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[6] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[5] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[4] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[3] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[2] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[1] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_data[0] in module tri_mode_ethernet_mac_v9_0_22_addr_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[11] in module tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[10] in module tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[9] in module tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap is either unconnected or has no load WARNING: [Synth 8-7129] Port bus2ip_addr[8] in module tri_mode_ethernet_mac_v9_0_22_addr_filter_wrap is either unconnected or has no load WARNING: [Synth 8-7129] Port ENABLE_HALF_DUPLEX in module PARAM_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port DEST_ADD_FIELD in module PARAM_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port SOURCE_ADD_FIELD in module PARAM_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port LENGTH_FIELD in module PARAM_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port IFG in module PARAM_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port SPEED_IS_10_100 in module PARAM_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port FIELD_COUNTER[5] in module DECODE_FRAME is either unconnected or has no load WARNING: [Synth 8-7129] Port FIELD_COUNTER[4] in module DECODE_FRAME is either unconnected or has no load WARNING: [Synth 8-7129] Port FIELD_COUNTER[3] in module DECODE_FRAME is either unconnected or has no load WARNING: [Synth 8-7129] Port FIELD_COUNTER[2] in module DECODE_FRAME is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET_GMII_MII in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port INBAND_TS_ENABLE in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SPEED[1] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SPEED[0] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port CORE_HAS_SGMII in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port RTC_CLK in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[47] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[46] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[45] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[44] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[43] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[42] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[41] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[40] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[39] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[38] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[37] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[36] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[35] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[34] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[33] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[32] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[31] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[30] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[29] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[28] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[27] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[26] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[25] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[24] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[23] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[22] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[21] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[20] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[19] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[18] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load WARNING: [Synth 8-7129] Port SYSTEMTIMER_S_FIELD[17] in module tri_mode_ethernet_mac_v9_0_22_rx is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 3064.035 ; gain = 25.992 ; free physical = 50388 ; free virtual = 86297 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 3075.906 ; gain = 37.863 ; free physical = 49650 ; free virtual = 85559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 3075.906 ; gain = 37.863 ; free physical = 49647 ; free virtual = 85556 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3078.875 ; gain = 0.000 ; free physical = 49095 ; free virtual = 85004 INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_ooc.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'U0' WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc:93] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc:95] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'U0' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ethernet_mac_rgmii_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ethernet_mac_rgmii_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/ethernet_mac_rgmii_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/ethernet_mac_rgmii_synth_1/dont_touch.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0' of design 'preSynthElab_1' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Vivado 12-3272] Current instance is the top level cell 'U0' of design 'preSynthElab_1' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30] WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:43] WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:44] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:47] INFO: [Vivado 12-3272] Current instance is the top level cell 'U0' of design 'preSynthElab_1' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53] INFO: [Vivado 12-3272] Current instance is the top level cell 'U0' of design 'preSynthElab_1' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54] WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:58] WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:59] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:66] INFO: [Vivado 12-3272] Current instance is the top level cell 'U0' of design 'preSynthElab_1' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:73] INFO: [Vivado 12-3272] Current instance is the top level cell 'U0' of design 'preSynthElab_1' [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:74] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'U0' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ethernet_mac_rgmii_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ethernet_mac_rgmii_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3240.625 ; gain = 0.000 ; free physical = 49521 ; free virtual = 85434 INFO: [Project 1-111] Unisim Transformation Summary: A total of 81 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAM64X1D => RAM64X1D (RAMD64E(x2)): 80 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3240.625 ; gain = 0.000 ; free physical = 49483 ; free virtual = 85400 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 49439 ; free virtual = 85381 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 49444 ; free virtual = 85387 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/ethernet_mac_rgmii_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 49578 ; free virtual = 85520 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' INFO: [Synth 8-802] inferred FSM for state register 'tx_state_reg' in module 'tri_mode_ethernet_mac_v9_0_22_tx_axi_intf' INFO: [Synth 8-802] inferred FSM for state register 'rx_state_reg' in module 'tri_mode_ethernet_mac_v9_0_22_rx_axi_intf' INFO: [Synth 8-802] inferred FSM for state register 'state_count_reg' in module 'tri_mode_ethernet_mac_v9_0_22_tx_cntl' INFO: [Synth 8-802] inferred FSM for state register 'pause_state_reg' in module 'tri_mode_ethernet_mac_v9_0_22_pfc_tx_cntl' INFO: [Synth 8-802] inferred FSM for state register 'legacy_state_reg' in module 'tri_mode_ethernet_mac_v9_0_22_pfc_tx_cntl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' INFO: [Synth 8-6159] Found Keep on FSM register 'tx_state_reg' in module 'tri_mode_ethernet_mac_v9_0_22_tx_axi_intf', re-encoding will not be performed --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * IDLE | 0000 | 0000 LOAD1 | 0001 | 0001 LOAD2 | 0010 | 0010 WAIT | 0011 | 0011 END_LOAD | 0100 | 0100 CLEAR_PIPE | 0101 | 0101 RELOAD1 | 0110 | 0110 RELOAD2 | 0111 | 0111 SEND | 1000 | 1000 BURST | 1001 | 1001 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 01 | 00 PKT | 11 | 01 WAIT | 10 | 10 DONE | 00 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_reg' using encoding 'sequential' in module 'tri_mode_ethernet_mac_v9_0_22_rx_axi_intf' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * IDLE | 001 | 001 TRANSMIT_REQUEST | 010 | 010 TRANSMITTING | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_count_reg' in module 'tri_mode_ethernet_mac_v9_0_22_tx_cntl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0001 | 000 REQ | 1000 | 001 WAIT | 0100 | 010 COUNT | 0010 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'legacy_state_reg' using encoding 'one-hot' in module 'tri_mode_ethernet_mac_v9_0_22_pfc_tx_cntl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- P_IDLE | 00 | 00 P_REQ | 01 | 01 P_WAIT | 10 | 10 P_HOLD | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'pause_state_reg' using encoding 'sequential' in module 'tri_mode_ethernet_mac_v9_0_22_pfc_tx_cntl' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 52781 ; free virtual = 88720 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-3332] Sequential element (gmii_mii_tx_gen/sync_speed_is_10_100/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_tx_gen/sync_speed_is_10_100/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_tx_gen/sync_speed_is_10_100/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_tx_gen/sync_speed_is_10_100/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_tx_gen/sync_speed_is_10_100/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_rx_gen/sync_speed_is_10_100/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_rx_gen/sync_speed_is_10_100/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_rx_gen/sync_speed_is_10_100/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_rx_gen/sync_speed_is_10_100/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (gmii_mii_rx_gen/sync_speed_is_10_100/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[0].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[1].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[2].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[3].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[4].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[5].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[6].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_rx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_rx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_rx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_rx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_rx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_tx_pen/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_tx_pen/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_tx_pen/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_tx_pen/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/ppe_sync[7].sync_tx_pen/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_rx_duplex/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_rx_duplex/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_rx_duplex/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_rx_duplex/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_rx_duplex/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_tx_duplex/data_sync_reg0) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_tx_duplex/data_sync_reg1) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_tx_duplex/data_sync_reg2) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_tx_duplex/data_sync_reg3) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. WARNING: [Synth 8-3332] Sequential element (flow/sync_tx_duplex/data_sync_reg4) is unused and will be removed from module tri_mode_ethernet_mac_v9_0_22. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 53127 ; free virtual = 89083 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:52 ; elapsed = 00:00:57 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 52979 ; free virtual = 88944 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:53 ; elapsed = 00:00:58 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 52885 ; free virtual = 88849 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:56 ; elapsed = 00:01:02 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 52688 ; free virtual = 88653 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-5374] Design tri_mode_ethernet_mac_v9_0_22 has 1 max_fanout requirements that cannot be met. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-3295] tying undriven pin txgen/CRC_CE_inferred:in0 to constant 0 INFO: [Synth 8-3295] tying undriven pin rxgen/CRC_CE_inferred:in0 to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:01 ; elapsed = 00:01:07 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 52097 ; free virtual = 88066 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:01 ; elapsed = 00:01:07 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 52107 ; free virtual = 88077 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:01 ; elapsed = 00:01:07 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 53104 ; free virtual = 89065 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:01 ; elapsed = 00:01:07 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 53100 ; free virtual = 89061 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:02 ; elapsed = 00:01:08 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 53073 ; free virtual = 89035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:02 ; elapsed = 00:01:08 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 53045 ; free virtual = 89007 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFIO | 1| |2 |BUFR | 1| |3 |CARRY4 | 33| |4 |IDDR | 5| |5 |IDELAYE2 | 5| |6 |LUT1 | 615| |7 |LUT2 | 254| |8 |LUT3 | 220| |9 |LUT4 | 302| |10 |LUT5 | 230| |11 |LUT6 | 511| |12 |MUXF7 | 14| |13 |MUXF8 | 2| |14 |ODDR | 6| |15 |ODELAYE2 | 6| |17 |RAM64X1D | 80| |18 |SRL16E | 20| |19 |FDCE | 25| |20 |FDPE | 40| |21 |FDRE | 2213| |22 |FDSE | 157| |23 |IBUF | 6| |24 |IOBUF | 1| |25 |OBUF | 7| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:02 ; elapsed = 00:01:08 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 53026 ; free virtual = 88988 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1178 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:53 ; elapsed = 00:00:59 . Memory (MB): peak = 3240.625 ; gain = 37.863 ; free physical = 52922 ; free virtual = 88883 Synthesis Optimization Complete : Time (s): cpu = 00:01:02 ; elapsed = 00:01:08 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 52914 ; free virtual = 88876 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 37-28] Duplicate attribute 'INIT' found for instance 'update_pause_ad_int_reg' of module 'FDRE'. Resolution: Check your design sources near the definition of the module or any related 'include files, looking for duplicate definitions with different values. Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3240.625 ; gain = 0.000 ; free physical = 53649 ; free virtual = 89599 INFO: [Netlist 29-17] Analyzing 153 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3240.625 ; gain = 0.000 ; free physical = 54061 ; free virtual = 90012 INFO: [Project 1-111] Unisim Transformation Summary: A total of 81 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAM64X1D => RAM64X1D (RAMD64E(x2)): 80 instances Synth Design complete, checksum: d70ff369 INFO: [Common 17-83] Releasing license: Synthesis 125 Infos, 254 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 3240.625 ; gain = 202.582 ; free physical = 53856 ; free virtual = 89806 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/ethernet_mac_rgmii_synth_1/ethernet_mac_rgmii.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ethernet_mac_rgmii, cache-ID = 0d154aca5a166618 INFO: [Coretcl 2-1174] Renamed 155 cell refs. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/1/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/ethernet_mac_rgmii_synth_1/ethernet_mac_rgmii.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file ethernet_mac_rgmii_utilization_synth.rpt -pb ethernet_mac_rgmii_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Mon May 13 11:45:13 2024...