## Repository info
- Merge request number: 128
- Branch name: 117-aurora_init

## MR Description
testing some changes to the Aurora initialisation timers
Closes #117


## Changelog


## rod_efex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.041504       |
| TNS:          | 0.000000       |
| WHS:          | 0.049995       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    37577    |    0         |   0              |    346400        |    10.85     |   
| Slice  Registers |    51532    |    81        |   0              |    692800        |    7.44      |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    101512   |   0         |   0              |    346400        |    29.30     |    
| Slice  Registers |    157749   |   0         |   0              |    692800        |    22.77     |    
| Block  RAM       Tile |        423 |         0   |              0    |             1180 |         35.85
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 5811e1b        | 1.0.5       |
| Constraints       | f7080fad       | 1.0.4       |
| IPbus XML         | 8f37344        | 1.0.1       |
| Top Directory     | 1214d6f        | 1.0.5       |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_efex | 5811e1b        | 1.0.5       |
| **Lib:** others   | 10f1382        | 1.0.5       |



</details>
</p>

 
## rod_jfex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.050475       |
| TNS:          | 0.000000       |
| WHS:          | 0.049509       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    52685    |    0         |   0              |    346400        |    15.21     |   
| Slice  Registers |    76226    |    81        |   0              |    692800        |    11.00     |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex Implementation Utilization report


                                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         --- |              ---  |             ---  |              
| Slice  LUTs      |    140241   |     0         |   0              |    346400        |    40.49     |    
| Slice  Registers |    229466   |     0         |   0              |    692800        |    33.12     |    
| Block  RAM       Tile |        684.5 |         0   |              0    |             1180 |         58.01
| DSPs   |         0    |        0     |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |     111       |   0              |    600           |    18.50     |    
                                                                                                           
## rod_jfex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 5811e1b        | 1.0.5       |
| Constraints       | 2cb141f3       | 1.0.4       |
| IPbus XML         | 8f37344        | 1.0.1       |
| Top Directory     | 1214d6f        | 1.0.5       |
| Hog               | bab6567        | 7.17.7      |
| **Lib:** rod_jfex | 5811e1b        | 1.0.5       |
| **Lib:** others   | 10f1382        | 1.0.5       |



</details>
</p>

 
## rod_efex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | -3.601556      |
| TNS:          | -1384.345581   |
| WHS:          | 0.048640       |
| THS:          | 0.000000       |


Time requirements are **NOT** met.



## rod_efex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    44089    |    0         |   0              |    346400        |    12.73     |   
| Slice  Registers |    59387    |    81        |   0              |    692800        |    8.57      |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex_p2 Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    118929   |   0         |   0              |    346400        |    34.33     |    
| Slice  Registers |    167925   |   0         |   0              |    692800        |    24.24     |    
| Block  RAM       Tile |        356 |         0   |              0    |             1180 |         30.17
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | 214b181        | 1.0.5       |
| Constraints          | c476e040       | 1.0.5       |
| IPbus XML            | 8f37344        | 1.0.1       |
| Top Directory        | c476e04        | 1.0.5       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_efex_p2 | 214b181        | 1.0.5       |
| **Lib:** others      | 5977f70        | 1.0.5       |



</details>
</p>

 
## rod_jfex_p2


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex_p2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | -3.541026      |
| TNS:          | -2131.972168   |
| WHS:          | 0.049794       |
| THS:          | 0.000000       |


Time requirements are **NOT** met.



## rod_jfex_p2 Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    59901    |    0         |   0              |    346400        |    17.29     |   
| Slice  Registers |    85694    |    81        |   0              |    692800        |    12.37     |   
| Block  RAM       Tile |        26.5 |         0   |              0    |             1180 |         2.25
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex_p2 Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    170294   |   0         |   0              |    346400        |    49.16     |    
| Slice  Registers |    245072   |   0         |   0              |    692800        |    35.37     |    
| Block  RAM       Tile |        535 |         0   |              0    |             1180 |         45.34
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_jfex_p2 Version Table

| **File set**         | **Commit SHA** | **Version** |
| ---                  | ---            | ---         |
| Global               | 5811e1b        | 1.0.5       |
| Constraints          | c476e040       | 1.0.5       |
| IPbus XML            | 8f37344        | 1.0.1       |
| Top Directory        | c476e04        | 1.0.5       |
| Hog                  | bab6567        | 7.17.7      |
| **Lib:** rod_jfex_p2 | 5811e1b        | 1.0.5       |
| **Lib:** others      | 10f1382        | 1.0.5       |



</details>
</p>