*** Running vivado with args -log axis_input_fifo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source axis_input_fifo.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source axis_input_fifo.tcl -notrace create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1561.816 ; gain = 5.961 ; free physical = 34920 ; free virtual = 74739 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: axis_input_fifo Command: synth_design -top axis_input_fifo -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1434676 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2506.184 ; gain = 411.801 ; free physical = 35311 ; free virtual = 75146 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'axis_input_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/synth/axis_input_fifo.v:53] INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_v2_0_11_top' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_data_fifo_v2_0_vl_rfs.v:53] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_1_util_aclken_converter_wrapper' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:596] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_1_util_axis2vector' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:805] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_1_util_axis2vector' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:805] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_1_util_vector2axis' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:986] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_1_util_vector2axis' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:986] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_1_util_aclken_converter_wrapper' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:596] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_axis' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2356] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:53] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:54] INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:506] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:54] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized2' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized2' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1214] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1281] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1303] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1914] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1914] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1626] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1626] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:53] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_axis' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2356] INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_v2_0_11_top' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_data_fifo_v2_0_vl_rfs.v:53] INFO: [Synth 8-6155] done synthesizing module 'axis_input_fifo' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/synth/axis_input_fifo.v:53] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_EFEX_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_EFEX_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:3069] WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] WARNING: [Synth 8-6014] Unused sequential element gdvld.data_valid_std_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:544] WARNING: [Synth 8-6014] Unused sequential element gen_pf_ic_rc.gae_ic_std.ram_aempty_i_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:765] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1398] WARNING: [Synth 8-7129] Port ACLK in module axis_infrastructure_v1_1_1_util_aclken_converter_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESETN in module axis_infrastructure_v1_1_1_util_aclken_converter_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port S_ACLKEN in module axis_infrastructure_v1_1_1_util_aclken_converter_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port M_ACLKEN in module axis_infrastructure_v1_1_1_util_aclken_converter_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port sleep in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port rsta in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port regcea in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port injectsbiterra in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port injectdbiterra in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[86] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[85] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[84] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[83] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[82] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[81] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[80] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[79] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[78] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[77] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[76] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[75] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[74] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[73] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[72] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[71] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[70] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[69] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[68] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[67] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[66] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[65] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[64] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[63] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[62] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[61] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[60] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[59] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[58] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[57] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[56] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[55] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[54] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[53] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[52] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[51] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[50] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[49] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[48] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[47] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[46] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[45] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[44] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[43] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[42] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[41] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[40] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[39] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[38] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[37] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[36] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[35] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[34] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[33] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[32] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[31] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[30] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[29] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[28] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[27] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[26] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[25] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[24] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[23] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[22] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[21] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[20] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[19] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[18] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[17] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[16] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[15] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[14] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[13] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[12] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[11] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[10] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[9] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[8] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[7] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[6] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[5] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[4] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[3] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[2] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[1] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port dinb[0] in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port injectsbiterrb in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port injectdbiterrb in module xpm_memory_base is either unconnected or has no load WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2592.121 ; gain = 497.738 ; free physical = 35204 ; free virtual = 75039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2609.934 ; gain = 515.551 ; free physical = 35196 ; free virtual = 75031 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2609.934 ; gain = 515.551 ; free physical = 35196 ; free virtual = 75031 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2609.934 ; gain = 0.000 ; free physical = 35196 ; free virtual = 75031 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo_ooc.xdc] for cell 'inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_input_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axis_input_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_input_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axis_input_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_input_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axis_input_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-1714] 10 XPM XDC files have been applied to the design. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2757.684 ; gain = 0.000 ; free physical = 35067 ; free virtual = 74902 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2757.719 ; gain = 0.000 ; free physical = 35060 ; free virtual = 74896 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 35391 ; free virtual = 75227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 35421 ; free virtual = 75258 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/dont_touch.xdc, line 9). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_pkt_fifo_ic.wpkt_cnt_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_pkt_fifo_ic.af_axis_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_rst_sync.xpm_cdc_sync_rst_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_fifo.xpm_fifo_axis_inst . (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 35420 ; free virtual = 75256 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 35401 ; free virtual = 75239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 4 Input 12 Bit Adders := 3 3 Input 12 Bit Adders := 2 2 Input 12 Bit Adders := 1 4 Input 11 Bit Adders := 5 2 Input 11 Bit Adders := 2 4 Input 2 Bit Adders := 1 +---XORs : 2 Input 12 Bit XORs := 2 2 Input 11 Bit XORs := 3 2 Input 1 Bit XORs := 52 +---Registers : 87 Bit Registers := 2 12 Bit Registers := 17 11 Bit Registers := 22 3 Bit Registers := 4 2 Bit Registers := 2 1 Bit Registers := 17 +---RAMs : 174K Bit (2048 X 87 bit) RAMs := 1 +---Muxes : 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 8 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 33 4 Input 2 Bit Muxes := 7 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port rsta in module xpm_memory_base is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5784] Optimized 18 bits of RAM "gen_wr_a.gen_word_narrow.mem_reg" due to constant propagation. Old ram width 87 bits, new ram width 69 bits. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 35390 ; free virtual = 75231 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 2 K x 87(NO_CHANGE) | W | | 2 K x 87(WRITE_FIRST) | | R | Port A and B | 0 | 4 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 37185 ; free virtual = 77036 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 37179 ; free virtual = 77031 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 2 K x 87(NO_CHANGE) | W | | 2 K x 87(WRITE_FIRST) | | R | Port A and B | 0 | 4 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 37170 ; free virtual = 77022 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |CARRY4 | 35| |2 |LUT1 | 14| |3 |LUT2 | 106| |4 |LUT3 | 24| |5 |LUT4 | 39| |6 |LUT5 | 31| |7 |LUT6 | 43| |8 |RAMB36E1 | 4| |9 |FDRE | 462| |10 |FDSE | 10| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 115 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2757.719 ; gain = 515.551 ; free physical = 36568 ; free virtual = 76420 Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2757.719 ; gain = 663.336 ; free physical = 36568 ; free virtual = 76420 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2757.719 ; gain = 0.000 ; free physical = 36862 ; free virtual = 76713 INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2757.719 ; gain = 0.000 ; free physical = 36861 ; free virtual = 76712 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: 56f89be INFO: [Common 17-83] Releasing license: Synthesis 80 Infos, 124 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2757.719 ; gain = 1181.059 ; free physical = 36861 ; free virtual = 76712 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1998.995; main = 1684.334; forked = 331.539 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4339.078; main = 2757.688; forked = 1613.406 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2781.695 ; gain = 0.000 ; free physical = 36860 ; free virtual = 76712 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/axis_input_fifo.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP axis_input_fifo, cache-ID = ebc0ca9e4a22708b INFO: [Coretcl 2-1174] Renamed 26 cell refs. Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2781.695 ; gain = 0.000 ; free physical = 36859 ; free virtual = 76712 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/axis_input_fifo.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file axis_input_fifo_utilization_synth.rpt -pb axis_input_fifo_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Sat Dec 14 14:50:47 2024...