*** Running vivado
    with args -log top_rod_efex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_efex.tcl -notrace


****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source top_rod_efex.tcl -notrace
create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1562.207 ; gain = 43.805 ; free physical = 41314 ; free virtual = 81306
Command: link_design -top top_rod_efex -part xc7vx550tffg1927-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7vx550tffg1927-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.dcp' for cell 'proc_clock_gen'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.dcp' for cell 'top_vio'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.dcp' for cell 'ttc_source_sel'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo.dcp' for cell 'Bulk_0_64_32/ILA_packet_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32.dcp' for cell 'Bulk_0_64_32/data_width_conv'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0.dcp' for cell 'Bulk_0_64_32/main_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila.dcp' for cell 'ILA_axi_chan_0/ila_crc_check'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.dcp' for cell 'alternate_cttc.fm_interface_3/clk_blk'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2.dcp' for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/ram0/RAM_0'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.dcp' for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.dcp' for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.dcp' for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.dcp' for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.dcp' for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1.dcp' for cell 'backplane/readout_ctrl/ila_tx0_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.dcp' for cell 'backplane/readout_ctrl/vio_gt_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.dcp' for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_CRC.dcp' for cell 'event_builder/alt_cttc_crc/crc_check_ila'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo.dcp' for cell 'event_builder/bulk_0/data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset.dcp' for cell 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila.dcp' for cell 'event_builder/readout_controller/readout_ctrl_ila2'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_ev_builder.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.dcp' for cell 'event_builder/ttc_input/bulk_ttc_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.dcp' for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_in'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_out'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_l1id_cont.dcp' for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm.dcp' for cell 'fm_interface_1/u0/ila_resetfsm'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.dcp' for cell 'ipbus_blk/ip_addr_probe'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/ethernet_mac_rgmii.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i'
Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2815.855 ; gain = 0.000 ; free physical = 40056 ; free virtual = 80049
INFO: [Netlist 29-17] Analyzing 14167 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. proc_clock_gen/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
INFO: [Chipscope 16-324] Core: Bulk_0_64_32/ILA_packet_fifo UUID: 63e7dc4f-a901-5f5e-8f15-f44cac18b816 
INFO: [Chipscope 16-324] Core: Bulk_1_64_32/ILA_packet_fifo UUID: b894b984-cded-5bd0-92d8-292d78f9765a 
INFO: [Chipscope 16-324] Core: Bulk_2_64_32/ILA_packet_fifo UUID: 020d2b63-4e4e-5e2e-aab4-4c5b2d6046e9 
INFO: [Chipscope 16-324] Core: ILA_axi_chan_0/ila_crc_check UUID: a9e8e6ca-2b1f-5fbe-a871-91755a4a7c6e 
INFO: [Chipscope 16-324] Core: ILA_axi_chan_6/ila_crc_check UUID: 41f97370-bc3f-56dd-ab00-76683edcad5a 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst UUID: 80888505-1efc-57ae-9e40-8681b86a5f8c 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst UUID: 7200d9a1-8e3d-5fc2-960c-ca771d9eec86 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_0/ila_fm UUID: 8097e4b8-b92b-5960-a4df-b73ab5d6cd06 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_0/vio_fm_reset UUID: f826ca6e-8cf4-5060-b996-19bb9a7821ab 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_1/ila_fm UUID: b46515df-c8ee-5943-846a-c28f4ef519d1 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_1/vio_fm_reset UUID: 2bb4310a-a09d-5a1b-b55a-16cdaed8d8de 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/polarity UUID: 2cb3aefb-fa06-5db0-8650-9045388eb833 
INFO: [Chipscope 16-324] Core: backplane/combined_ttc/ila_rx2_inst UUID: f60b8007-6bf8-5822-bc32-cdf6ef756575 
INFO: [Chipscope 16-324] Core: backplane/combined_ttc/vio_gt_inst UUID: a6d99938-502c-5867-8e71-028088cb558d 
INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/ila_tx0_inst UUID: 5af42e05-e58f-565e-bd4b-e3caf0b9b4a7 
INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_gt_inst UUID: 0523908b-78fb-555c-8d31-f2c3c610733b 
INFO: [Chipscope 16-324] Core: event_builder/CTTC_receiver/ila_rx2_inst UUID: 9bcc70d8-4c9f-5ec9-860b-cad2fd9e719e 
INFO: [Chipscope 16-324] Core: event_builder/CTTC_receiver/vio_gt_inst UUID: bc513526-9cc8-5253-83cd-9ec640d281c7 
INFO: [Chipscope 16-324] Core: event_builder/alt_cttc_crc/crc_check_ila UUID: d7404ee0-8704-5433-8191-e9b8d11eb7ee 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset UUID: 526aa884-2b3a-5885-860e-a799e122b19e 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset UUID: 592a1374-74f7-5fde-8629-0629a988b160 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset UUID: d0cdf49d-87c1-5fdb-8f36-88ae2767b2fe 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset UUID: a1c73c7d-54dd-5e44-a5cd-6a9ae58e2902 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset UUID: 2148b4a4-6c97-57b7-8bd5-c38db3594514 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset UUID: 82df580b-a348-5d7c-99c6-354d9bef434c 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset UUID: 45d1e92f-20ed-5b07-a76f-32f5fba18f36 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset UUID: 4690a94e-7602-522f-b9dd-52d0ca7f6f31 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset UUID: a892dd09-4899-5545-805e-16189e27c183 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset UUID: 2c0c29b3-c404-506a-9236-de8519e80024 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset UUID: f49143af-facf-56d7-a3e1-924dbc407829 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset UUID: 0fc7f848-5df1-54bb-b6a9-c71167d2a9d4 
INFO: [Chipscope 16-324] Core: event_builder/readout_controller/readout_ctrl_ila2 UUID: 2118af16-197d-5a88-95e6-28dbf9962d95 
INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/State_machine_ILA UUID: b8ade747-7d7c-5fc7-9f63-b2cb50b3a6e1 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_bulk_ttc_fifo UUID: 54b31265-4039-519c-ae13-a6b6c7fda705 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_in UUID: 0d145367-edc8-5440-8a43-c5b7fdc60185 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_out UUID: dea619c4-8196-5fc3-a887-501d70a94797 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check UUID: 0b5e705b-49ad-5d15-9efb-ec02e926d290 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/ila_fm UUID: 39f68e95-8276-57e5-b2ba-d040b8bf414c 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/vio_fm_reset UUID: b602d903-de6d-5e57-92e3-814b1496a830 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_fm UUID: 312b9249-01c3-5825-bad2-86e782be33e1 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/vio_fm_reset UUID: eec5d607-63dd-55c1-a9db-2118e9215856 
INFO: [Chipscope 16-324] Core: fm_interface_1/u0/ila_resetfsm UUID: 82d99aa3-751c-5dfe-85d1-97a24142969c 
INFO: [Chipscope 16-324] Core: ipbus_blk/ip_addr_probe UUID: d3bad9ce-591e-57bb-984d-9f6468850a46 
INFO: [Chipscope 16-324] Core: pp_out_fifo_6432/ILA_packet_fifo UUID: b136e600-ef26-57f9-8e20-f80fc6236875 
INFO: [Chipscope 16-324] Core: top_vio UUID: 7b2ee998-e565-566c-a490-bae90ac485a9 
INFO: [Chipscope 16-324] Core: ttc_source_sel UUID: c1a2c02a-9f6d-5067-b34f-a57ba8dd1b77 
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:54]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:54]
get_clocks: Time (s): cpu = 00:00:27 ; elapsed = 00:00:18 . Memory (MB): peak = 4229.133 ; gain = 907.656 ; free physical = 38765 ; free virtual = 78771
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'ttc_source_sel'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'ttc_source_sel'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/polarity'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/polarity'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0'
WARNING: [Vivado 12-2489] -period contains time 3.118500 which will be rounded to 3.119 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc:72]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]
WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_0/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_6/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc:22]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc]
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports -scoped_to_current_instance ext_spi_clk]'. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:73]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:74]
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Project 1-1714] 338 XPM XDC files have been applied to the design.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-1687] 6 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5044.805 ; gain = 0.000 ; free physical = 38023 ; free virtual = 78029
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 4609 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 4064 instances
  IOBUF => IOBUF (IBUF, OBUFT): 23 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 42 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
  RAM64M => RAM64M (RAMD64E(x4)): 380 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 96 instances

106 Infos, 128 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:02:34 ; elapsed = 00:02:14 . Memory (MB): peak = 5044.840 ; gain = 3310.719 ; free physical = 38021 ; free virtual = 78028
source /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it...
INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd...
INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found.
INFO: [Hog:Msg-0] All done
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
Parsing TCL File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/FullMode_tx/FullMode_tx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl]
Parsing TCL File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl]
Parsing TCL File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl]
Parsing TCL File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5052.809 ; gain = 7.969 ; free physical = 38025 ; free virtual = 78032

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup

Phase 1.1.1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
Done building netlist checker database: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38047 ; free virtual = 78060
get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38046 ; free virtual = 78059
Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38051 ; free virtual = 78064
Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 1936ef87b

Time (s): cpu = 00:01:56 ; elapsed = 00:01:55 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38051 ; free virtual = 78064
Phase 1.1 Core Generation And Design Setup | Checksum: 1936ef87b

Time (s): cpu = 00:01:56 ; elapsed = 00:01:56 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38051 ; free virtual = 78064

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1936ef87b

Time (s): cpu = 00:01:57 ; elapsed = 00:01:56 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38051 ; free virtual = 78064
Phase 1 Initialization | Checksum: 1936ef87b

Time (s): cpu = 00:01:57 ; elapsed = 00:01:56 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38051 ; free virtual = 78064

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1936ef87b

Time (s): cpu = 00:02:05 ; elapsed = 00:02:04 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38043 ; free virtual = 78056

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1936ef87b

Time (s): cpu = 00:02:05 ; elapsed = 00:02:04 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38027 ; free virtual = 78040
Phase 2 Timer Update And Timing Data Collection | Checksum: 1936ef87b

Time (s): cpu = 00:02:05 ; elapsed = 00:02:04 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38027 ; free virtual = 78040

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 84 inverters resulting in an inversion of 2043 pins
INFO: [Opt 31-138] Pushed 84 inverter(s) to 665 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 18f09a742

Time (s): cpu = 00:02:12 ; elapsed = 00:02:11 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38026 ; free virtual = 78039
Retarget | Checksum: 18f09a742
INFO: [Opt 31-389] Phase Retarget created 859 cells and removed 2332 cells
INFO: [Opt 31-1021] In phase Retarget, 3154 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 1 inverter(s) to 2 load pin(s).
Phase 4 Constant propagation | Checksum: 1156a77e8

Time (s): cpu = 00:02:14 ; elapsed = 00:02:14 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38026 ; free virtual = 78038
Constant propagation | Checksum: 1156a77e8
INFO: [Opt 31-389] Phase Constant propagation created 341 cells and removed 1790 cells
INFO: [Opt 31-1021] In phase Constant propagation, 2457 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 Sweep
INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD6623) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
INFO: [Opt 31-120] Instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
Phase 5 Sweep | Checksum: 12a795d74

Time (s): cpu = 00:02:28 ; elapsed = 00:02:27 . Memory (MB): peak = 5052.809 ; gain = 0.000 ; free physical = 38025 ; free virtual = 78038
Sweep | Checksum: 12a795d74
INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 9004 cells
INFO: [Opt 31-1021] In phase Sweep, 24660 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 12a795d74

Time (s): cpu = 00:02:31 ; elapsed = 00:02:29 . Memory (MB): peak = 5076.820 ; gain = 24.012 ; free physical = 38025 ; free virtual = 78038
BUFG optimization | Checksum: 12a795d74
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
INFO: [Common 17-14] Message 'Opt 31-1131' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 12a795d74

Time (s): cpu = 00:02:32 ; elapsed = 00:02:30 . Memory (MB): peak = 5076.820 ; gain = 24.012 ; free physical = 38025 ; free virtual = 78038
Shift Register Optimization | Checksum: 12a795d74
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7vx550t is unsupported

Phase 8 Post Processing Netlist
INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 3 pins
Phase 8 Post Processing Netlist | Checksum: 12af2a805

Time (s): cpu = 00:02:33 ; elapsed = 00:02:31 . Memory (MB): peak = 5076.820 ; gain = 24.012 ; free physical = 38025 ; free virtual = 78037
Post Processing Netlist | Checksum: 12af2a805
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 2578 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: b7e674da

Time (s): cpu = 00:02:37 ; elapsed = 00:02:34 . Memory (MB): peak = 5076.820 ; gain = 24.012 ; free physical = 38024 ; free virtual = 78037

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.48 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 38024 ; free virtual = 78037
Phase 9.2 Verifying Netlist Connectivity | Checksum: b7e674da

Time (s): cpu = 00:02:37 ; elapsed = 00:02:35 . Memory (MB): peak = 5076.820 ; gain = 24.012 ; free physical = 38024 ; free virtual = 78037
Phase 9 Finalization | Checksum: b7e674da

Time (s): cpu = 00:02:37 ; elapsed = 00:02:35 . Memory (MB): peak = 5076.820 ; gain = 24.012 ; free physical = 38024 ; free virtual = 78037
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |             859  |            2332  |                                           3154  |
|  Constant propagation         |             341  |            1790  |                                           2457  |
|  Sweep                        |              11  |            9004  |                                          24660  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               1  |                                           2578  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: b7e674da

Time (s): cpu = 00:02:37 ; elapsed = 00:02:35 . Memory (MB): peak = 5076.820 ; gain = 24.012 ; free physical = 38024 ; free virtual = 78037
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 38024 ; free virtual = 78037
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] from IP /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/axi4_subsys_jtag_axi_0_0.xci
Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc:69]
all_fanout: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 38029 ; free virtual = 78042
Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 38029 ; free virtual = 78042
Ending Netlist Obfuscation Task | Checksum: b7e674da

Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 38029 ; free virtual = 78042
INFO: [Common 17-83] Releasing license: Implementation
146 Infos, 228 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:03:14 ; elapsed = 00:03:12 . Memory (MB): peak = 5076.820 ; gain = 31.980 ; free physical = 38029 ; free virtual = 78042
INFO: [runtcl-4] Executing : report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx
Command: report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 38025 ; free virtual = 78038
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.29 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37882 ; free virtual = 78035
Wrote PlaceDB: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37880 ; free virtual = 78036
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37880 ; free virtual = 78036
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.36 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37880 ; free virtual = 78035
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37880 ; free virtual = 78035
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37878 ; free virtual = 78035
Write Physdb Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.49 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37878 ; free virtual = 78035
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37948 ; free virtual = 78033
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37929 ; free virtual = 78014
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7da993dd

Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37929 ; free virtual = 78014
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37929 ; free virtual = 78014

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1544d382e

Time (s): cpu = 00:01:15 ; elapsed = 00:01:15 . Memory (MB): peak = 5076.820 ; gain = 0.000 ; free physical = 37919 ; free virtual = 78004

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 237a1928d

Time (s): cpu = 00:02:20 ; elapsed = 00:02:21 . Memory (MB): peak = 5773.445 ; gain = 696.625 ; free physical = 37215 ; free virtual = 77299

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 237a1928d

Time (s): cpu = 00:02:22 ; elapsed = 00:02:22 . Memory (MB): peak = 5773.445 ; gain = 696.625 ; free physical = 37215 ; free virtual = 77299
Phase 1 Placer Initialization | Checksum: 237a1928d

Time (s): cpu = 00:02:22 ; elapsed = 00:02:23 . Memory (MB): peak = 5773.445 ; gain = 696.625 ; free physical = 37215 ; free virtual = 77299

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1e4eb079c

Time (s): cpu = 00:02:44 ; elapsed = 00:02:45 . Memory (MB): peak = 5773.445 ; gain = 696.625 ; free physical = 37214 ; free virtual = 77298

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 17a6a0d3d

Time (s): cpu = 00:03:04 ; elapsed = 00:03:05 . Memory (MB): peak = 5773.445 ; gain = 696.625 ; free physical = 37214 ; free virtual = 77298

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 168e0b3dc

Time (s): cpu = 00:03:05 ; elapsed = 00:03:06 . Memory (MB): peak = 5773.445 ; gain = 696.625 ; free physical = 37214 ; free virtual = 77298

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 11c0bdb12

Time (s): cpu = 00:06:17 ; elapsed = 00:06:19 . Memory (MB): peak = 5833.406 ; gain = 756.586 ; free physical = 37142 ; free virtual = 77227

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 10670 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 4638 nets or LUTs. Breaked 0 LUT, combined 4638 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1402] Pass 1: Identified 1 candidate cell for Shift Register optimization.
INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5882.352 ; gain = 0.000 ; free physical = 37117 ; free virtual = 77201
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5882.352 ; gain = 0.000 ; free physical = 37117 ; free virtual = 77201

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |           4638  |                  4638  |           0  |           1  |  00:00:06  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:02  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            2  |              0  |                     1  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            2  |           4638  |                  4639  |           0  |           9  |  00:00:09  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1bac2a193

Time (s): cpu = 00:06:50 ; elapsed = 00:06:53 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37117 ; free virtual = 77201
Phase 2.4 Global Placement Core | Checksum: 1b683d1c0

Time (s): cpu = 00:07:14 ; elapsed = 00:07:16 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37117 ; free virtual = 77201
Phase 2 Global Placement | Checksum: 1b683d1c0

Time (s): cpu = 00:07:14 ; elapsed = 00:07:17 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37117 ; free virtual = 77201

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1e0df6626

Time (s): cpu = 00:07:36 ; elapsed = 00:07:38 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37117 ; free virtual = 77201

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 150ba5f36

Time (s): cpu = 00:08:17 ; elapsed = 00:08:20 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37116 ; free virtual = 77201

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 12420cbcc

Time (s): cpu = 00:08:20 ; elapsed = 00:08:23 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37116 ; free virtual = 77201

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1fc9e915d

Time (s): cpu = 00:08:25 ; elapsed = 00:08:28 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37116 ; free virtual = 77201

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 126ae99e5

Time (s): cpu = 00:09:14 ; elapsed = 00:09:17 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37116 ; free virtual = 77201

Phase 3.6 Small Shape Detail Placement

Phase 3.6.1 Place Remaining
Phase 3.6.1 Place Remaining | Checksum: 1a65e150e

Time (s): cpu = 00:10:44 ; elapsed = 00:10:48 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37113 ; free virtual = 77198
Phase 3.6 Small Shape Detail Placement | Checksum: 1a65e150e

Time (s): cpu = 00:10:47 ; elapsed = 00:10:50 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37113 ; free virtual = 77198

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 128894986

Time (s): cpu = 00:10:56 ; elapsed = 00:11:00 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37115 ; free virtual = 77199

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1bb17aecb

Time (s): cpu = 00:11:03 ; elapsed = 00:11:07 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37114 ; free virtual = 77199
Phase 3 Detail Placement | Checksum: 1bb17aecb

Time (s): cpu = 00:11:05 ; elapsed = 00:11:08 . Memory (MB): peak = 5882.352 ; gain = 805.531 ; free physical = 37114 ; free virtual = 77199

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1fd4fa4ca

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.649 | TNS=-20.677 |
Phase 1 Physical Synthesis Initialization | Checksum: 23850f3fa

Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 5898.352 ; gain = 0.000 ; free physical = 37111 ; free virtual = 77196
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 23850f3fa

Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 5898.352 ; gain = 0.000 ; free physical = 37111 ; free virtual = 77196
Phase 4.1.1.1 BUFG Insertion | Checksum: 1fd4fa4ca

Time (s): cpu = 00:12:58 ; elapsed = 00:13:03 . Memory (MB): peak = 5898.352 ; gain = 821.531 ; free physical = 37111 ; free virtual = 77196

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.046. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2855bc251

Time (s): cpu = 00:15:49 ; elapsed = 00:15:55 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183

Time (s): cpu = 00:15:49 ; elapsed = 00:15:55 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183
Phase 4.1 Post Commit Optimization | Checksum: 2855bc251

Time (s): cpu = 00:15:51 ; elapsed = 00:15:57 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 2855bc251

Time (s): cpu = 00:15:53 ; elapsed = 00:15:59 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                4x4|
|___________|___________________|___________________|
|      South|                1x1|                4x4|
|___________|___________________|___________________|
|       East|                1x1|                4x4|
|___________|___________________|___________________|
|       West|                1x1|                2x2|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 2855bc251

Time (s): cpu = 00:15:55 ; elapsed = 00:16:01 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183
Phase 4.3 Placer Reporting | Checksum: 2855bc251

Time (s): cpu = 00:15:56 ; elapsed = 00:16:02 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 37099 ; free virtual = 77183

Time (s): cpu = 00:15:56 ; elapsed = 00:16:03 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21c02bf84

Time (s): cpu = 00:15:58 ; elapsed = 00:16:04 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183
Ending Placer Task | Checksum: 124852e1f

Time (s): cpu = 00:15:59 ; elapsed = 00:16:05 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183
186 Infos, 228 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:16:13 ; elapsed = 00:16:20 . Memory (MB): peak = 5910.352 ; gain = 833.531 ; free physical = 37099 ; free virtual = 77183
INFO: [runtcl-4] Executing : report_io -file top_rod_efex_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.47 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 37099 ; free virtual = 77184
INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_placed.rpt -pb top_rod_efex_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_rod_efex_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.89 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 37094 ; free virtual = 77184
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.52 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36938 ; free virtual = 77181
Wrote PlaceDB: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36750 ; free virtual = 77181
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36750 ; free virtual = 77181
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.35 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36749 ; free virtual = 77181
Wrote Netlist Cache: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36737 ; free virtual = 77181
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36736 ; free virtual = 77181
Write Physdb Complete: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36736 ; free virtual = 77181
report_design_analysis: Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36739 ; free virtual = 77185
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:13 ; elapsed = 00:01:16 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 37004 ; free virtual = 77189
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore

Starting Initial Update Timing Task

Time (s): cpu = 00:01:08 ; elapsed = 00:01:08 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 37002 ; free virtual = 77187
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
196 Infos, 228 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:01:09 ; elapsed = 00:01:10 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 37002 ; free virtual = 77187
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.51 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36847 ; free virtual = 77187
Wrote PlaceDB: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36659 ; free virtual = 77187
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36659 ; free virtual = 77187
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.36 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36659 ; free virtual = 77187
Wrote Netlist Cache: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36647 ; free virtual = 77187
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36646 ; free virtual = 77187
Write Physdb Complete: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36646 ; free virtual = 77187
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:51 ; elapsed = 00:00:53 . Memory (MB): peak = 5910.352 ; gain = 0.000 ; free physical = 36905 ; free virtual = 77187
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.

Phase 1 Build RT Design
Checksum: PlaceDB: d52d2afc ConstDB: 0 ShapeSum: 4f580323 RouteDB: 0
Post Restoration Checksum: NetGraph: 92cce7e | NumContArr: fa9a8227 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2891945df

Time (s): cpu = 00:02:21 ; elapsed = 00:02:21 . Memory (MB): peak = 6116.891 ; gain = 109.172 ; free physical = 36714 ; free virtual = 76995

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2891945df

Time (s): cpu = 00:02:23 ; elapsed = 00:02:24 . Memory (MB): peak = 6116.891 ; gain = 109.172 ; free physical = 36714 ; free virtual = 76995

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2891945df

Time (s): cpu = 00:02:24 ; elapsed = 00:02:25 . Memory (MB): peak = 6116.891 ; gain = 109.172 ; free physical = 36714 ; free virtual = 76995
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 212e57738

Time (s): cpu = 00:05:27 ; elapsed = 00:05:29 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75926
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.005  | TNS=0.000  | WHS=-1.150 | THS=-21504.185|


Phase 2.4 Update Timing for Bus Skew

Phase 2.4.1 Update Timing
Phase 2.4.1 Update Timing | Checksum: 26feaa84b

Time (s): cpu = 00:06:24 ; elapsed = 00:06:26 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75926
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.005  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 2.4 Update Timing for Bus Skew | Checksum: 1d6a1c635

Time (s): cpu = 00:06:26 ; elapsed = 00:06:28 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75926

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.202956 %
  Global Horizontal Routing Utilization  = 0.305914 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 231295
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 231295
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 4

Phase 2 Router Initialization | Checksum: 2a4e47704

Time (s): cpu = 00:06:31 ; elapsed = 00:06:33 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75925

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2a4e47704

Time (s): cpu = 00:06:32 ; elapsed = 00:06:34 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75925

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1f601581c

Time (s): cpu = 00:07:38 ; elapsed = 00:07:41 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35638 ; free virtual = 75928
Phase 3 Initial Routing | Checksum: 1f601581c

Time (s): cpu = 00:07:39 ; elapsed = 00:07:41 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35638 ; free virtual = 75928

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 19388
 Number of Nodes with overlaps = 4224
 Number of Nodes with overlaps = 409
 Number of Nodes with overlaps = 138
 Number of Nodes with overlaps = 27
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.156 | TNS=-0.680 | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 26497c727

Time (s): cpu = 00:15:11 ; elapsed = 00:15:15 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35639 ; free virtual = 75928

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 1424
 Number of Nodes with overlaps = 193
 Number of Nodes with overlaps = 81
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 10
 Number of Nodes with overlaps = 11
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.028 | TNS=-0.051 | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 20e1426fc

Time (s): cpu = 00:16:23 ; elapsed = 00:16:28 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35634 ; free virtual = 75923

Phase 4.3 Global Iteration 2
 Number of Nodes with overlaps = 1212
 Number of Nodes with overlaps = 324
 Number of Nodes with overlaps = 105
 Number of Nodes with overlaps = 26
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.012  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.3 Global Iteration 2 | Checksum: f4055404

Time (s): cpu = 00:17:33 ; elapsed = 00:17:38 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922
Phase 4 Rip-up And Reroute | Checksum: f4055404

Time (s): cpu = 00:17:33 ; elapsed = 00:17:39 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: f4055404

Time (s): cpu = 00:17:34 ; elapsed = 00:17:40 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: f4055404

Time (s): cpu = 00:17:35 ; elapsed = 00:17:40 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922
Phase 5 Delay and Skew Optimization | Checksum: f4055404

Time (s): cpu = 00:17:35 ; elapsed = 00:17:41 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1b66094fb

Time (s): cpu = 00:18:01 ; elapsed = 00:18:06 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.041  | TNS=0.000  | WHS=-0.522 | THS=-1014.454|


Phase 6.1.2 Lut RouteThru Assignment for hold
Phase 6.1.2 Lut RouteThru Assignment for hold | Checksum: 23073390a

Time (s): cpu = 00:18:18 ; elapsed = 00:18:24 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922
Phase 6.1 Hold Fix Iter | Checksum: 23073390a

Time (s): cpu = 00:18:19 ; elapsed = 00:18:25 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35633 ; free virtual = 75922

Phase 6.2 Additional Hold Fix
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.041  | TNS=0.000  | WHS=-0.498 | THS=-985.494|

Phase 6.2 Additional Hold Fix | Checksum: 1da99e201

Time (s): cpu = 00:18:45 ; elapsed = 00:18:51 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35632 ; free virtual = 75922

Phase 6.3 Non Free Resource Hold Fix Iter
Phase 6.3 Non Free Resource Hold Fix Iter | Checksum: 2308e32d7

Time (s): cpu = 00:18:54 ; elapsed = 00:19:00 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75925
Phase 6 Post Hold Fix | Checksum: 2308e32d7

Time (s): cpu = 00:18:55 ; elapsed = 00:19:01 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75925

Phase 7 Timing Verification

Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: 180fd5d14

Time (s): cpu = 00:19:27 ; elapsed = 00:19:33 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75925
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.041  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 7 Timing Verification | Checksum: 180fd5d14

Time (s): cpu = 00:19:27 ; elapsed = 00:19:33 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75925

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 12.2249 %
  Global Horizontal Routing Utilization  = 11.8023 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 8 Route finalize | Checksum: 180fd5d14

Time (s): cpu = 00:19:29 ; elapsed = 00:19:35 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35636 ; free virtual = 75925

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 180fd5d14

Time (s): cpu = 00:19:30 ; elapsed = 00:19:36 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35635 ; free virtual = 75925

Phase 10 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin alternate_cttc.fm_interface_3/combined_transceiver/common0_i/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y9/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y30/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y31/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y7/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y28/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y29/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y30/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y31/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y7/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y36/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y37/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y27/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y26/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y35/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y34/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y33/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y32/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y8/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y24/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y25/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y6/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y23/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y22/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y21/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y20/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y15/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y14/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y3/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y4/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y5/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y6/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y7/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y1/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y12/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y13/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y3/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y11/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y10/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y9/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y8/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y2/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y3/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y2/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y0/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y0/GTSOUTHREFCLK1
Phase 10 Depositing Routes | Checksum: 20239d5af

Time (s): cpu = 00:19:50 ; elapsed = 00:19:56 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35624 ; free virtual = 75913

Phase 11 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.042  | TNS=0.000  | WHS=0.050  | THS=0.000  |

Phase 11 Post Router Timing | Checksum: 1ff4dc4bf

Time (s): cpu = 00:21:28 ; elapsed = 00:21:34 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35619 ; free virtual = 75908
INFO: [Route 35-61] The design met the timing requirement.
INFO: [Route 35-16] Router Completed Successfully

Phase 12 Post-Route Event Processing
Phase 12 Post-Route Event Processing | Checksum: 1fdfa40c3

Time (s): cpu = 00:21:35 ; elapsed = 00:21:42 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35619 ; free virtual = 75908
Ending Routing Task | Checksum: 1fdfa40c3

Time (s): cpu = 00:21:41 ; elapsed = 00:21:47 . Memory (MB): peak = 7222.492 ; gain = 1214.773 ; free physical = 35619 ; free virtual = 75908

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
266 Infos, 228 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:22:10 ; elapsed = 00:22:16 . Memory (MB): peak = 7222.492 ; gain = 1312.141 ; free physical = 35619 ; free virtual = 75908
INFO: [runtcl-4] Executing : report_drc -file top_rod_efex_drc_routed.rpt -pb top_rod_efex_drc_routed.pb -rpx top_rod_efex_drc_routed.rpx
Command: report_drc -file top_rod_efex_drc_routed.rpt -pb top_rod_efex_drc_routed.pb -rpx top_rod_efex_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:55 ; elapsed = 00:00:55 . Memory (MB): peak = 7222.492 ; gain = 0.000 ; free physical = 35619 ; free virtual = 75909
INFO: [runtcl-4] Executing : report_methodology -file top_rod_efex_methodology_drc_routed.rpt -pb top_rod_efex_methodology_drc_routed.pb -rpx top_rod_efex_methodology_drc_routed.rpx
Command: report_methodology -file top_rod_efex_methodology_drc_routed.rpt -pb top_rod_efex_methodology_drc_routed.pb -rpx top_rod_efex_methodology_drc_routed.rpx
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:02:28 ; elapsed = 00:02:28 . Memory (MB): peak = 7222.492 ; gain = 0.000 ; free physical = 35614 ; free virtual = 75905
INFO: [runtcl-4] Executing : report_power -file top_rod_efex_power_routed.rpt -pb top_rod_efex_power_summary_routed.pb -rpx top_rod_efex_power_routed.rpx
Command: report_power -file top_rod_efex_power_routed.rpt -pb top_rod_efex_power_summary_routed.pb -rpx top_rod_efex_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUP_INCLUDE.GEN_7Series_STARTUP.STARTUPE2_inst
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
278 Infos, 229 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:01:43 ; elapsed = 00:01:04 . Memory (MB): peak = 7278.520 ; gain = 56.027 ; free physical = 35595 ; free virtual = 75906
INFO: [runtcl-4] Executing : report_route_status -file top_rod_efex_route_status.rpt -pb top_rod_efex_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file top_rod_efex_timing_summary_routed.rpt -pb top_rod_efex_timing_summary_routed.pb -rpx top_rod_efex_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 7278.520 ; gain = 0.000 ; free physical = 35525 ; free virtual = 75894
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_rod_efex_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_rod_efex_clock_utilization_routed.rpt
report_clock_utilization: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 7278.520 ; gain = 0.000 ; free physical = 35524 ; free virtual = 75894
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_rod_efex_bus_skew_routed.rpt -pb top_rod_efex_bus_skew_routed.pb -rpx top_rod_efex_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_timing_summary -file top_rod_efex_timing_summary_routed_1.rpt -pb top_rod_efex_timing_summary_routed_1.pb -rpx top_rod_efex_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 7278.520 ; gain = 0.000 ; free physical = 35519 ; free virtual = 75894
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
source /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean.
INFO: [Hog:Msg-0] Git describe set to: v1.0.5-5811E1B
INFO: [Hog:Msg-0] Evaluating last git SHA in which rod_efex was modified...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean.
INFO: [Hog:Msg-0] The git SHA value 5811e1b will be embedded in the binary file.
INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean.
INFO: [Hog:Msg-0] Git describe set to: v1.0.5-5811E1B
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v1.0.5-5811E1B...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
report_utilization: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 7278.520 ; gain = 0.000 ; free physical = 35512 ; free virtual = 75892