*** Running vivado with args -log top_rod_efex.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_rod_efex.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source top_rod_efex.tcl -notrace create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1562.785 ; gain = 5.961 ; free physical = 41373 ; free virtual = 81270 source /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-synthesis.tcl INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] Found modified *.bd files: BD/axi4_subsys.bd, will restore them... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v1.0.5-5811E1B... INFO: [Hog:Msg-0] Opening project rod_efex... Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2023.2/data/ip'. open_project: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1898.242 ; gain = 335.457 ; free physical = 41091 ; free virtual = 80988 INFO: [Hog:Msg-0] Checking rod_efex list files... INFO: [Hog:Msg-0] Retrieved Vivado project files... WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg in project has been modified from creation time. Please update the script you used to create the file and regenerate the project, or save the file outside the Projects/ directory and add it to a project list file WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl in project has been modified from creation time. Please update the script you used to create the file and regenerate the project, or save the file outside the Projects/ directory and add it to a project list file WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/hdl/post.tcl was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/bulk0_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/tb/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/efex_all_chans_normal/wav/pp_testbench_behav.wcfg was found in project but not in list files or .hog/extra.files WARNING: [Hog:MsgAndLog-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/sim_sets/generic_waves/pp_testbench_behav.wcfg was found in list files but not in project. INFO: [Common 17-14] Message 'Hog:MsgAndLog 0' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Hog:Msg-0] Design List Files matches project. Nothing to do. INFO: [Hog:Msg-0] Constraint List Files matches project. Nothing to do. INFO: [Hog:Msg-0] /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Top//rod_efex/hog.conf matches project. Nothing to do INFO: [Hog:Msg-0] Design List files and hog.conf match project. All ok! WARNING: [Hog:Msg-0] Number of mismatch in simulation list files = 329 WARNING: [Hog:Msg-0] Number of mismatch in simulation conf files = 54 INFO: [Hog:Msg-0] All done. INFO: [Hog:Msg-0] Evaluating non committed changes... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Git describe for 5811e1b is: v1.0.5-5811E1B INFO: [Hog:Msg-0] Found last SHA for rod_efex: 5811e1b INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml and replacing placeholders with xml version 01000001... Python path configuration: PYTHONHOME = '/usr' PYTHONPATH = '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3:/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/bin:/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib:/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib/python3.8/site-packages:/opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default:/opt/Xilinx/Vivado/2023.2/lib/lnx64.o:/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3:/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/bin:/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib:/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib/python3.8/site-packages:/opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default:/opt/Xilinx/Vivado/2023.2/lib/lnx64.o:' program name = 'python' isolated = 0 environment = 1 user site = 1 import site = 1 sys._base_executable = '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/bin/python' sys.base_prefix = '/usr' sys.base_exec_prefix = '/usr' sys.executable = '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/bin/python' sys.prefix = '/usr' sys.exec_prefix = '/usr' sys.path = [ '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3', '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/bin', '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib', '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib/python3.8/site-packages', '/opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default', '/opt/Xilinx/Vivado/2023.2/lib/lnx64.o', '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3', '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/bin', '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib', '/opt/Xilinx/Vivado/2023.2/tps/lnx64/python-3.8.3/lib/python3.8/site-packages', '/opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default', '/opt/Xilinx/Vivado/2023.2/lib/lnx64.o', '', '/usr/lib/python38.zip', '/usr/lib/python3.8', '/usr/lib/python3.8/lib-dynload', ] Fatal Python error: init_fs_encoding: failed to get the Python codec of the filesystem encoding Python runtime state: core initialized ModuleNotFoundError: No module named 'encodings' Current thread 0x00007faf5fc12740 (most recent call first): WARNING: [Hog:CopyXMLsFromListFile-0] Error while trying to run python: child process exited abnormally WARNING: [Hog:CopyXMLsFromListFile-0] IPbus executable gen_ipbus_addr_decode not found or not working, will not verify IPbus address tables. INFO: [Hog:CopyXMLsFromListFile-0] 23 lines read from ./Top//rod_efex/list/xml.lst INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRod.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRod_common_IdVersion.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBackplane.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBackplaneRegisters.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBulkProc.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodChannel.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlash.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlashChip.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlashSectors.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodGpio.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodHwicap.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodI2C.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodInfrastructure.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodPktCaptureRegisters.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodL1idCaptureRegisters.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodInputCaptureRegisters.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodProcessor.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodTobProc.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodTTCRegisters.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodTrace.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodXadc.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodXadcMeasurements.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodXadcMeasureVbram.xml to /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] 23 file/s copied INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:WriteGenerics-0] Passing parameters/generics to project's top module... INFO: [Hog:WriteGenerics-0] Setting parameters/generics... INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/versions.txt... ------------------------- PRE SYNTHESIS ------------------------- 14/12/2024 at 14:53:14 Firmware date and time: 13122024, 00161227 Global SHA: 5811e1b, VER: 1.0.5 Constraints SHA: f7080fad, VER: 1.0.4 IPbus XML SHA: 8f37344, VER: 1.0.1 Top SHA: 1214d6f, VER: 1.0.5 Hog SHA: bab6567, VER: 7.17.7 --- Libraries --- rod_efex SHA: 5811e1b, VER: 1.0.5 others SHA: 10f1382, VER: 1.0.5 ----------------------------------------------------------------- INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with Hog2023.2-7 in .gitlab-ci.yml. INFO: [Hog:Msg-0] All done. Command: synth_design -top top_rod_efex -part xc7vx550tffg1927-2 -directive PerformanceOptimized -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1436025 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.375 ; gain = 404.711 ; free physical = 39865 ; free virtual = 79762 --------------------------------------------------------------------------------- WARNING: [Synth 8-8943] 'jtag_axi_v1_2_18_jtag_axi' is not compiled in library 'jtag_axi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:57] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_dpram.vhd:38] INFO: [Synth 8-638] synthesizing module 'top_rod_efex' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:354] Parameter GLOBAL_DATE bound to: 32'b00010011000100100010000000100100 Parameter GLOBAL_TIME bound to: 32'b00000000000101100001001000100111 Parameter GLOBAL_VER bound to: 32'b00000001000000000000000000000101 Parameter GLOBAL_SHA bound to: 32'b00000101100000010001111000011011 Parameter TOP_VER bound to: 32'b00000001000000000000000000000101 Parameter TOP_SHA bound to: 32'b00000001001000010100110101101111 Parameter CON_VER bound to: 32'b00000001000000000000000000000100 Parameter CON_SHA bound to: 32'b11110111000010000000111110101101 Parameter HOG_VER bound to: 32'b00000111000100010000000000000111 Parameter HOG_SHA bound to: 32'b00001011101010110110010101100111 Parameter XML_SHA bound to: 32'b00001000111100110111001101000100 Parameter XML_VER bound to: 32'b00000001000000000000000000000001 Parameter ROD_EFEX_SHA bound to: 32'b00000101100000010001111000011011 Parameter ROD_EFEX_VER bound to: 32'b00000001000000000000000000000101 WARNING: [Synth 8-3819] Generic 'OTHERS_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'OTHERS_SHA' not present in instantiated entity will be ignored Parameter max_count bound to: 32'b00000000000000001111111111111111 INFO: [Synth 8-3491] module 'system_top_reset' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:9' bound to instance 'reset_top' of component 'system_top_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1837] INFO: [Synth 8-638] synthesizing module 'system_top_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:22] Parameter max_count bound to: 32'b00000000000000001111111111111111 INFO: [Synth 8-256] done synthesizing module 'system_top_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:22] Parameter max_count bound to: 32'b00000010011000100101101000000000 INFO: [Synth 8-3491] module 'system_top_reset' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:9' bound to instance 'phy_reset' of component 'system_top_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1856] INFO: [Synth 8-638] synthesizing module 'system_top_reset__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:22] Parameter max_count bound to: 32'b00000010011000100101101000000000 INFO: [Synth 8-256] done synthesizing module 'system_top_reset__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:22] INFO: [Synth 8-3491] module 'packet_processor_clock' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/packet_processor_clock_stub.vhdl:6' bound to instance 'proc_clock_gen' of component 'packet_processor_clock' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1875] INFO: [Synth 8-638] synthesizing module 'packet_processor_clock' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/packet_processor_clock_stub.vhdl:16] INFO: [Synth 8-3491] module 'vio_top' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/vio_top_stub.vhdl:6' bound to instance 'top_vio' of component 'vio_top' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1887] INFO: [Synth 8-638] synthesizing module 'vio_top' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/vio_top_stub.vhdl:32] WARNING: [Synth 8-5640] Port 'fp_gp_led_b' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:380] Parameter GLOBAL_DATE bound to: 32'b00010011000100100010000000100100 Parameter GLOBAL_TIME bound to: 32'b00000000000101100001001000100111 Parameter GLOBAL_VER bound to: 32'b00000001000000000000000000000101 Parameter GLOBAL_SHA bound to: 32'b00000101100000010001111000011011 Parameter TOP_VER bound to: 32'b00000001000000000000000000000101 Parameter TOP_SHA bound to: 32'b00000001001000010100110101101111 Parameter CON_VER bound to: 32'b00000001000000000000000000000100 Parameter CON_SHA bound to: 32'b11110111000010000000111110101101 Parameter HOG_VER bound to: 32'b00000111000100010000000000000111 Parameter HOG_SHA bound to: 32'b00001011101010110110010101100111 Parameter XML_SHA bound to: 32'b00001000111100110111001101000100 Parameter XML_VER bound to: 32'b00000001000000000000000000000001 Parameter ROD_EFEX_SHA bound to: 32'b00000101100000010001111000011011 Parameter ROD_EFEX_VER bound to: 32'b00000001000000000000000000000101 Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden_rod bound to: 0 - type: integer Parameter Module_ID bound to: 32'b01000000000000000000000011101101 Parameter BuildTimeAndDate bound to: 32'b00010011000100100010000000100100 Parameter FirmwareVersion bound to: 32'b00000101100000010001111000011011 INFO: [Synth 8-3491] module 'ROD_system' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:45' bound to instance 'ipbus_blk' of component 'ROD_system' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1915] INFO: [Synth 8-638] synthesizing module 'ROD_system' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:204] Parameter GLOBAL_DATE bound to: 32'b00010011000100100010000000100100 Parameter GLOBAL_TIME bound to: 32'b00000000000101100001001000100111 Parameter GLOBAL_VER bound to: 32'b00000001000000000000000000000101 Parameter GLOBAL_SHA bound to: 32'b00000101100000010001111000011011 Parameter TOP_VER bound to: 32'b00000001000000000000000000000101 Parameter TOP_SHA bound to: 32'b00000001001000010100110101101111 Parameter CON_VER bound to: 32'b00000001000000000000000000000100 Parameter CON_SHA bound to: 32'b11110111000010000000111110101101 Parameter HOG_VER bound to: 32'b00000111000100010000000000000111 Parameter HOG_SHA bound to: 32'b00001011101010110110010101100111 Parameter XML_SHA bound to: 32'b00001000111100110111001101000100 Parameter XML_VER bound to: 32'b00000001000000000000000000000001 Parameter ROD_EFEX_SHA bound to: 32'b00000101100000010001111000011011 Parameter ROD_EFEX_VER bound to: 32'b00000001000000000000000000000101 Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden_rod bound to: 0 - type: integer Parameter Module_ID bound to: 32'b01000000000000000000000011101101 Parameter BuildTimeAndDate bound to: 32'b00010011000100100010000000100100 Parameter FirmwareVersion bound to: 32'b00000101100000010001111000011011 INFO: [Synth 8-3491] module 'ip_dual_decode' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ip_dual_decode.vhd:34' bound to instance 'shelf_addr_sel' of component 'ip_dual_decode' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:489] INFO: [Synth 8-638] synthesizing module 'ip_dual_decode' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ip_dual_decode.vhd:43] INFO: [Synth 8-256] done synthesizing module 'ip_dual_decode' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ip_dual_decode.vhd:43] INFO: [Synth 8-3491] module 'vio_ip_address' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/vio_ip_address_stub.vhdl:6' bound to instance 'ip_addr_probe' of component 'vio_ip_address' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:497] INFO: [Synth 8-638] synthesizing module 'vio_ip_address' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/vio_ip_address_stub.vhdl:17] Parameter GLOBAL_DATE bound to: 32'b00010011000100100010000000100100 Parameter GLOBAL_TIME bound to: 32'b00000000000101100001001000100111 Parameter GLOBAL_VER bound to: 32'b00000001000000000000000000000101 Parameter GLOBAL_SHA bound to: 32'b00000101100000010001111000011011 Parameter TOP_VER bound to: 32'b00000001000000000000000000000101 Parameter TOP_SHA bound to: 32'b00000001001000010100110101101111 Parameter CON_VER bound to: 32'b00000001000000000000000000000100 Parameter CON_SHA bound to: 32'b11110111000010000000111110101101 Parameter HOG_VER bound to: 32'b00000111000100010000000000000111 Parameter HOG_SHA bound to: 32'b00001011101010110110010101100111 Parameter XML_SHA bound to: 32'b00001000111100110111001101000100 Parameter XML_VER bound to: 32'b00000001000000000000000000000001 Parameter ROD_EFEX_SHA bound to: 32'b00000101100000010001111000011011 Parameter ROD_EFEX_VER bound to: 32'b00000001000000000000000000000101 Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden_rod bound to: 0 - type: integer Parameter phase_2 bound to: 0 - type: integer Parameter Module_ID bound to: 32'b01000000000000000000000011101101 Parameter BuildTimeAndDate bound to: 32'b00010011000100100010000000100100 Parameter FirmwareVersion bound to: 32'b00000101100000010001111000011011 INFO: [Synth 8-3491] module 'common_IdVersion_regs' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:39' bound to instance 'common_regs' of component 'common_IdVersion_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:522] INFO: [Synth 8-638] synthesizing module 'common_IdVersion_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:82] Parameter GLOBAL_DATE bound to: 32'b00010011000100100010000000100100 Parameter GLOBAL_TIME bound to: 32'b00000000000101100001001000100111 Parameter GLOBAL_VER bound to: 32'b00000001000000000000000000000101 Parameter GLOBAL_SHA bound to: 32'b00000101100000010001111000011011 Parameter TOP_VER bound to: 32'b00000001000000000000000000000101 Parameter TOP_SHA bound to: 32'b00000001001000010100110101101111 Parameter CON_VER bound to: 32'b00000001000000000000000000000100 Parameter CON_SHA bound to: 32'b11110111000010000000111110101101 Parameter HOG_VER bound to: 32'b00000111000100010000000000000111 Parameter HOG_SHA bound to: 32'b00001011101010110110010101100111 Parameter XML_SHA bound to: 32'b00001000111100110111001101000100 Parameter XML_VER bound to: 32'b00000001000000000000000000000001 Parameter ROD_EFEX_SHA bound to: 32'b00000101100000010001111000011011 Parameter ROD_EFEX_VER bound to: 32'b00000001000000000000000000000101 Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter phase_2 bound to: 0 - type: integer Parameter Module_ID bound to: 32'b01000000000000000000000011101101 Parameter BuildTimeAndDate bound to: 32'b00010011000100100010000000100100 Parameter FirmwareVersion bound to: 32'b00000101100000010001111000011011 WARNING: [Synth 8-3819] Generic 'golden_rod' not present in instantiated entity will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:522] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 6 - type: integer Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_syncreg_v' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 1 - type: integer WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:66] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:67] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:68] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:82] WARNING: [Synth 8-3919] null assignment ignored WARNING: [Synth 8-3919] null assignment ignored INFO: [Synth 8-638] synthesizing module 'syncreg_r' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:58] INFO: [Synth 8-256] done synthesizing module 'syncreg_r' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:58] WARNING: [Synth 8-11358] null range expression ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:176] INFO: [Synth 8-256] done synthesizing module 'ipbus_syncreg_v' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:141] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:142] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:153] INFO: [Synth 8-638] synthesizing module 'ipbus_syncreg_v__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:66] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:67] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:68] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:82] WARNING: [Synth 8-3919] null assignment ignored WARNING: [Synth 8-3919] null assignment ignored WARNING: [Synth 8-11358] null range expression ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:176] INFO: [Synth 8-256] done synthesizing module 'ipbus_syncreg_v__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:173] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:174] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:189] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:191] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:204] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:206] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:221] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:223] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:237] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:239] INFO: [Synth 8-3491] module 'dna_reader' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:30' bound to instance 'fpga_dna' of component 'dna_reader' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:243] INFO: [Synth 8-638] synthesizing module 'dna_reader' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:38] Parameter SIM_DNA_VALUE bound to: 60'b000100100011010001010110011110001001101010111100110111100010 INFO: [Synth 8-113] binding component instance 'DNA_PORT_inst' to cell 'DNA_PORT' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:67] INFO: [Synth 8-256] done synthesizing module 'dna_reader' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:38] INFO: [Synth 8-3491] module 'dna_decoder' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_decoder.vhd:34' bound to instance 'fpga_dna_decode' of component 'dna_decoder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:250] INFO: [Synth 8-638] synthesizing module 'dna_decoder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_decoder.vhd:46] INFO: [Synth 8-256] done synthesizing module 'dna_decoder' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_decoder.vhd:46] INFO: [Synth 8-256] done synthesizing module 'common_IdVersion_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:82] INFO: [Synth 8-3491] module 'ipbus_rod' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:142' bound to instance 'ipbus' of component 'ipbus_rod' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:570] INFO: [Synth 8-638] synthesizing module 'ipbus_rod' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:217] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_example_design_clocks' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:60' bound to instance 'example_clocks' of component 'ethernet_mac_rgmii_example_design_clocks' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:682] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_example_design_clocks' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:79] INFO: [Synth 8-113] binding component instance 'bufg_clkin1' to cell 'BUFGCE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:154] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'lock_sync' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:157] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:84] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg0' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:113] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg1' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:126] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg2' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:138] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg3' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:150] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg4' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:162] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_sync_block' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:84] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'mmcm_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:178] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:87] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'reset_sync0' to cell 'FDPE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:109] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'reset_sync1' to cell 'FDPE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:121] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'reset_sync2' to cell 'FDPE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:133] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'reset_sync3' to cell 'FDPE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:145] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'reset_sync4' to cell 'FDPE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:157] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_reset_sync' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:87] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_clk_wiz' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:71' bound to instance 'clock_generator' of component 'ethernet_mac_rgmii_clk_wiz' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:190] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_clk_wiz' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:86] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 10 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_DIVIDE bound to: 32 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter REF_JITTER1 bound to: 0.010000 - type: double INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:122] INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:201] INFO: [Synth 8-113] binding component instance 'clkout2_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:207] INFO: [Synth 8-113] binding component instance 'clkout3_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:213] INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:219] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_clk_wiz' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:86] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_example_design_clocks' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:79] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_example_design_resets' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:57' bound to instance 'example_resets' of component 'ethernet_mac_rgmii_example_design_resets' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:714] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_example_design_resets' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:84] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'dcm_sync' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:131] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'glbl_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:145] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'axi_lite_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:159] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'gtx_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:187] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'chk_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:219] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_example_design_resets' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:84] INFO: [Synth 8-3491] module 'eth_7s_rgmii' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:94' bound to instance 'trimac_fifo_block' of component 'eth_7s_rgmii' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:906] INFO: [Synth 8-638] synthesizing module 'eth_7s_rgmii' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:212] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_support' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:68' bound to instance 'trimac_sup_block' of component 'ethernet_mac_rgmii_support' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:528] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_support' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:164] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_support_resets' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:62' bound to instance 'tri_mode_ethernet_mac_support_resets_i' of component 'ethernet_mac_rgmii_support_resets' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:284] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_support_resets' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:72] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'idelayctrl_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:108] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_support_resets' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:72] Parameter SIM_DEVICE bound to: 7SERIES - type: string INFO: [Synth 8-113] binding component instance 'tri_mode_ethernet_mac_idelayctrl_common_i' to cell 'IDELAYCTRL' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:295] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ethernet_mac_rgmii_stub.vhdl:6' bound to instance 'tri_mode_ethernet_mac_i' of component 'ethernet_mac_rgmii' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:309] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ethernet_mac_rgmii_stub.vhdl:68] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_support' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:164] INFO: [Synth 8-3491] module 'rgmii_rx_fifo_2' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/rgmii_rx_fifo_2_stub.vhdl:6' bound to instance 'trimac_read_fifo_2' of component 'rgmii_rx_fifo_2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:642] INFO: [Synth 8-638] synthesizing module 'rgmii_rx_fifo_2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/rgmii_rx_fifo_2_stub.vhdl:27] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'rx_mac_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:684] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'tx_mac_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:692] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_axi_lite_sm' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:69' bound to instance 'axi_lite_controller' of component 'ethernet_mac_rgmii_axi_lite_sm' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:761] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_axi_lite_sm' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:105] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'update_speed_sync_inst' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:278] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_axi_lite_sm' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:105] INFO: [Synth 8-256] done synthesizing module 'eth_7s_rgmii' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:212] INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:50] INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:24] INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:30] INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:24] INFO: [Synth 8-638] synthesizing module 'led_stretcher' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/led_stretcher.vhd:25] Parameter WIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'led_stretcher' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/led_stretcher.vhd:25] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:50] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:89] WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:90] INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'udp_ipam_block' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:60] Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_ipam_block' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:60] INFO: [Synth 8-638] synthesizing module 'udp_build_arp' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_arp' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_build_ping' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] INFO: [Synth 8-256] done synthesizing module 'udp_build_ping' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_ipam' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_ipam' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:62] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:82] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] INFO: [Synth 8-638] synthesizing module 'ipbus_example' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:60] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 4 - type: integer Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_axi4_bridge' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_axi4_bridge.vhd:66] INFO: [Synth 8-256] done synthesizing module 'ipbus_axi4_bridge' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_axi4_bridge.vhd:66] INFO: [Synth 8-256] done synthesizing module 'ipbus_example' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ipbus_rod' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:217] INFO: [Synth 8-3491] module 'axi4_subsys_wrapper' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:14' bound to instance 'axi4_subsys' of component 'axi4_subsys_wrapper' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:641] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_wrapper' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:80] INFO: [Synth 8-3491] module 'axi4_subsys' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4597' bound to instance 'axi4_subsys_i' of component 'axi4_subsys' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:231] INFO: [Synth 8-638] synthesizing module 'axi4_subsys' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4668] INFO: [Synth 8-3491] module 'axi4_subsys_axi_emc_0_0' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:59' bound to instance 'axi_emc_0' of component 'axi4_subsys_axi_emc_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:5342] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_emc_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:119] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_INSTANCE bound to: axi_emc_inst - type: string Parameter C_AXI_CLK_PERIOD_PS bound to: 30769 - type: integer Parameter C_LFLASH_PERIOD_PS bound to: 30769 - type: integer Parameter C_LINEAR_FLASH_SYNC_BURST bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_PORT_DIFF bound to: 0 - type: integer Parameter C_S_AXI_REG_ADDR_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_REG_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_EN_REG bound to: 0 - type: integer Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_ID_WIDTH bound to: 2 - type: integer Parameter C_S_AXI_MEM0_BASEADDR bound to: 32'b01100000000000000000000000000000 Parameter C_S_AXI_MEM0_HIGHADDR bound to: 32'b01111111111111111111111111111111 Parameter C_S_AXI_MEM1_BASEADDR bound to: 32'b10110000000000000000000000000000 Parameter C_S_AXI_MEM1_HIGHADDR bound to: 32'b10111111111111111111111111111111 Parameter C_S_AXI_MEM2_BASEADDR bound to: 32'b11000000000000000000000000000000 Parameter C_S_AXI_MEM2_HIGHADDR bound to: 32'b11001111111111111111111111111111 Parameter C_S_AXI_MEM3_BASEADDR bound to: 32'b11010000000000000000000000000000 Parameter C_S_AXI_MEM3_HIGHADDR bound to: 32'b11011111111111111111111111111111 Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_MEM0_TYPE bound to: 1 - type: integer Parameter C_MEM1_TYPE bound to: 0 - type: integer Parameter C_MEM2_TYPE bound to: 0 - type: integer Parameter C_MEM3_TYPE bound to: 0 - type: integer Parameter C_MEM0_WIDTH bound to: 32 - type: integer Parameter C_MEM1_WIDTH bound to: 16 - type: integer Parameter C_MEM2_WIDTH bound to: 16 - type: integer Parameter C_MEM3_WIDTH bound to: 16 - type: integer Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer Parameter C_PAGE_SIZE bound to: 16 - type: integer Parameter C_MEM_A_MSB bound to: 31 - type: integer Parameter C_MEM_A_LSB bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_0 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_1 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_2 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_3 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TAVDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TPACC_PS_FLASH_0 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_0 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_0 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_0 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_1 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_1 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_1 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_2 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_2 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_2 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_3 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_3 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_3 bound to: 27000 - type: integer INFO: [Synth 8-3491] module 'axi_emc' declared at '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:3419' bound to instance 'U0' of component 'axi_emc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:373] INFO: [Synth 8-638] synthesizing module 'axi_emc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:3729] INFO: [Synth 8-638] synthesizing module 'axi_emc_native_interface' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:1780] INFO: [Synth 8-638] synthesizing module 'axi_emc_addr_gen' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:577] INFO: [Synth 8-256] done synthesizing module 'axi_emc_addr_gen' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:577] INFO: [Synth 8-638] synthesizing module 'axi_emc_address_decode' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:1208] INFO: [Synth 8-256] done synthesizing module 'axi_emc_address_decode' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:1208] INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/02c4/hdl/lib_srl_fifo_v1_0_rfs.vhd:538] INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/02c4/hdl/lib_srl_fifo_v1_0_rfs.vhd:134] INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/02c4/hdl/lib_srl_fifo_v1_0_rfs.vhd:134] INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/02c4/hdl/lib_srl_fifo_v1_0_rfs.vhd:329] INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/02c4/hdl/lib_srl_fifo_v1_0_rfs.vhd:329] INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/02c4/hdl/lib_srl_fifo_v1_0_rfs.vhd:538] INFO: [Synth 8-638] synthesizing module 'axi_emc_v3_0_29_counter_f' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:240] INFO: [Synth 8-256] done synthesizing module 'axi_emc_v3_0_29_counter_f' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:240] INFO: [Synth 8-256] done synthesizing module 'axi_emc_native_interface' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:1780] INFO: [Synth 8-638] synthesizing module 'EMC' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:8174] INFO: [Synth 8-638] synthesizing module 'emc_common_v3_0_6_ipic_if' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:535] INFO: [Synth 8-638] synthesizing module 'ld_arith_reg' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-6157] synthesizing module 'MULT_AND' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116] INFO: [Synth 8-6155] done synthesizing module 'MULT_AND' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-6157] synthesizing module 'MUXCY' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127] INFO: [Synth 8-6155] done synthesizing module 'MUXCY' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-6157] synthesizing module 'XORCY' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093] INFO: [Synth 8-6155] done synthesizing module 'XORCY' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-6157] synthesizing module 'FDRE' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005] INFO: [Synth 8-6155] done synthesizing module 'FDRE' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-256] done synthesizing module 'emc_common_v3_0_6_ipic_if' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:535] INFO: [Synth 8-638] synthesizing module 'mem_state_machine' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:2139] INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3063] INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3063] INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3063] INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3063] INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3063] INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3063] INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3063] INFO: [Synth 8-256] done synthesizing module 'mem_state_machine' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:2139] INFO: [Synth 8-638] synthesizing module 'addr_counter_mux' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4406] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4501] INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4518] INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4518] INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4518] INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4518] INFO: [Synth 8-256] done synthesizing module 'addr_counter_mux' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4406] INFO: [Synth 8-638] synthesizing module 'counters' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:1620] INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41141' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:285] INFO: [Synth 8-6157] synthesizing module 'FDSE' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41141] INFO: [Synth 8-6155] done synthesizing module 'FDSE' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41141] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41141' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:285] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41141' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:285] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41141' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:285] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41141' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:285] INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85127' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:248] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:139093' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:259] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:275] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85116' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:238] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:118] INFO: [Synth 8-256] done synthesizing module 'counters' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:1620] INFO: [Synth 8-638] synthesizing module 'select_param' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3580] INFO: [Synth 8-256] done synthesizing module 'select_param' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3580] INFO: [Synth 8-638] synthesizing module 'mem_steer' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:5288] INFO: [Synth 8-113] binding component instance 'RDACK_PIPE_ASYNC' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:5967] INFO: [Synth 8-113] binding component instance 'RDACK_PIPE_ASYNC' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:5967] INFO: [Synth 8-113] binding component instance 'AALIGN_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6030] INFO: [Synth 8-113] binding component instance 'AALIGN_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6030] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6054] INFO: [Synth 8-113] binding component instance 'RDDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:7063] INFO: [Synth 8-113] binding component instance 'RDDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:7063] INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'mem_steer' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:5288] INFO: [Synth 8-638] synthesizing module 'io_registers' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:1179] INFO: [Synth 8-256] done synthesizing module 'io_registers' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:1179] INFO: [Synth 8-256] done synthesizing module 'EMC' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:8174] INFO: [Synth 8-256] done synthesizing module 'axi_emc' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:3729] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_emc_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:119] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_gpio_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/synth/axi4_subsys_axi_gpio_0_0.vhd:85] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_GPIO_WIDTH bound to: 16 - type: integer Parameter C_GPIO2_WIDTH bound to: 24 - type: integer Parameter C_ALL_INPUTS bound to: 0 - type: integer Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer Parameter C_ALL_OUTPUTS bound to: 1 - type: integer Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000001111111100000000 Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 Parameter C_IS_DUAL bound to: 1 - type: integer Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 INFO: [Synth 8-638] synthesizing module 'axi_gpio' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:1356] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:181] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:838] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:181] INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:1356] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_gpio_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/synth/axi4_subsys_axi_gpio_0_0.vhd:85] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_hwicap_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/synth/axi4_subsys_axi_hwicap_0_0.vhd:93] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_ICAP_EXTERNAL bound to: 1 - type: integer Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer Parameter C_ENABLE_ASYNC bound to: 0 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer Parameter C_ICAP_WIDTH_S bound to: X32 - type: string Parameter C_DEVICE_ID bound to: 32'b00000100001000100100000010010011 Parameter C_MODE bound to: 0 - type: integer Parameter C_NOREAD bound to: 0 - type: integer Parameter C_SIMULATION bound to: 2 - type: integer Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_OPERATION bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_hwicap' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:4074] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized6' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized6' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized7' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized8' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized8' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized9' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized9' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized10' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized10' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized11' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized11' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized12' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized12' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized13' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized13' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized14' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized14' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized15' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized15' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized16' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized16' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized17' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized17' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized18' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized18' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized19' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized19' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized20' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized20' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized21' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized21' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized22' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized22' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized23' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized23' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized24' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized24' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized25' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized25' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized26' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized26' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized27' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized27' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized28' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized28' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'hwicap_shared' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:3438] INFO: [Synth 8-638] synthesizing module 'axi_hwicap_v3_0_33_ipic_if' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:212] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'async_fifo_fg' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/1531/hdl/lib_fifo_v1_0_rfs.vhd:246] Parameter FIFO_MEMORY_TYPE bound to: block - type: string Parameter FIFO_WRITE_DEPTH bound to: 64 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: std - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter CDC_SYNC_STAGES bound to: 4 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2158] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:53] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:54] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:54] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1626] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1626] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1914] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1914] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:53] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2158] INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/1531/hdl/lib_fifo_v1_0_rfs.vhd:246] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'async_fifo_fg__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/1531/hdl/lib_fifo_v1_0_rfs.vhd:246] Parameter FIFO_MEMORY_TYPE bound to: block - type: string Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: std - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter CDC_SYNC_STAGES bound to: 4 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2158] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:53] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:54] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:54] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized1' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1892] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized6' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized6' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1866] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:53] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (0#1) [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2158] INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/1531/hdl/lib_fifo_v1_0_rfs.vhd:246] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter PROG_USR bound to: FALSE - type: string Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double INFO: [Synth 8-256] done synthesizing module 'axi_hwicap_v3_0_33_ipic_if' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:212] INFO: [Synth 8-638] synthesizing module 'icap_statemachine_shared' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2162] INFO: [Synth 8-256] done synthesizing module 'icap_statemachine_shared' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2162] INFO: [Synth 8-256] done synthesizing module 'hwicap_shared' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:3438] INFO: [Synth 8-638] synthesizing module 'interrupt_control' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d8cc/hdl/interrupt_control_v3_1_vh_rfs.vhd:257] INFO: [Synth 8-256] done synthesizing module 'interrupt_control' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d8cc/hdl/interrupt_control_v3_1_vh_rfs.vhd:257] INFO: [Synth 8-256] done synthesizing module 'axi_hwicap' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:4074] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_hwicap_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/synth/axi4_subsys_axi_hwicap_0_0.vhd:93] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_iic_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/synth/axi4_subsys_axi_iic_0_0.vhd:91] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_GPO_WIDTH bound to: 1 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_LEVEL bound to: 1 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer Parameter C_DISABLE_SETUP_VIOLATION_CHECK bound to: 0 - type: integer Parameter C_STATIC_TIMING_REG_WIDTH bound to: 0 - type: integer Parameter C_TIMING_REG_WIDTH bound to: 32 - type: integer Parameter C_DEFAULT_VALUE bound to: 8'b00000000 INFO: [Synth 8-638] synthesizing module 'axi_iic' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:6866] INFO: [Synth 8-638] synthesizing module 'iic' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:6167] INFO: [Synth 8-638] synthesizing module 'axi_ipif_ssp1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:5631] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized29' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized29' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized30' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized30' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized31' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized31' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized32' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized32' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized33' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized33' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized34' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized34' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized35' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized35' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized36' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized36' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized37' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized37' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized38' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized38' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized39' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized39' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized40' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized40' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized41' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized41' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized42' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized42' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized43' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized43' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized44' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized44' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized45' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized45' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized46' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized46' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized47' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized47' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized48' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized48' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'interrupt_control__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d8cc/hdl/interrupt_control_v3_1_vh_rfs.vhd:257] INFO: [Synth 8-256] done synthesizing module 'interrupt_control__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d8cc/hdl/interrupt_control_v3_1_vh_rfs.vhd:257] INFO: [Synth 8-638] synthesizing module 'axi_iic_v2_1_5_soft_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:109] INFO: [Synth 8-256] done synthesizing module 'axi_iic_v2_1_5_soft_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:109] INFO: [Synth 8-256] done synthesizing module 'axi_ipif_ssp1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:5631] INFO: [Synth 8-638] synthesizing module 'reg_interface' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:1627] INFO: [Synth 8-256] done synthesizing module 'reg_interface' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:1627] INFO: [Synth 8-638] synthesizing module 'filter' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:4949] INFO: [Synth 8-638] synthesizing module 'debounce' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:1254] INFO: [Synth 8-256] done synthesizing module 'debounce' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:1254] INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:4949] INFO: [Synth 8-638] synthesizing module 'iic_control' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:2864] INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:670] INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:670] INFO: [Synth 8-638] synthesizing module 'shift8' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:830] INFO: [Synth 8-256] done synthesizing module 'shift8' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:830] INFO: [Synth 8-638] synthesizing module 'upcnt_n__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:670] INFO: [Synth 8-256] done synthesizing module 'upcnt_n__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:670] INFO: [Synth 8-256] done synthesizing module 'iic_control' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:2864] INFO: [Synth 8-638] synthesizing module 'SRL_FIFO' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:376] INFO: [Synth 8-6157] synthesizing module 'FDR' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40992] INFO: [Synth 8-6155] done synthesizing module 'FDR' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40992] INFO: [Synth 8-6157] synthesizing module 'MUXCY_L' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85152] INFO: [Synth 8-6155] done synthesizing module 'MUXCY_L' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85152] INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133737] INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133737] INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:376] INFO: [Synth 8-638] synthesizing module 'dynamic_master' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:5171] INFO: [Synth 8-256] done synthesizing module 'dynamic_master' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:5171] INFO: [Synth 8-638] synthesizing module 'SRL_FIFO__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:376] INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:376] INFO: [Synth 8-256] done synthesizing module 'iic' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:6167] INFO: [Synth 8-256] done synthesizing module 'axi_iic' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:6866] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_iic_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/synth/axi4_subsys_axi_iic_0_0.vhd:91] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_iic_1_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/synth/axi4_subsys_axi_iic_1_0.vhd:91] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_GPO_WIDTH bound to: 1 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_LEVEL bound to: 1 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer Parameter C_DISABLE_SETUP_VIOLATION_CHECK bound to: 0 - type: integer Parameter C_STATIC_TIMING_REG_WIDTH bound to: 0 - type: integer Parameter C_TIMING_REG_WIDTH bound to: 32 - type: integer Parameter C_DEFAULT_VALUE bound to: 8'b00000000 INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_iic_1_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/synth/axi4_subsys_axi_iic_1_0.vhd:91] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_interconnect_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2824] INFO: [Synth 8-638] synthesizing module 'm00_couplers_imp_1AOY6T4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:94] INFO: [Synth 8-256] done synthesizing module 'm00_couplers_imp_1AOY6T4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:94] INFO: [Synth 8-638] synthesizing module 'm01_couplers_imp_FF3AZQ' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:271] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_0/synth/axi4_subsys_auto_pc_0.v:53] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871] WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126] WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_0/synth/axi4_subsys_auto_pc_0.v:53] INFO: [Synth 8-256] done synthesizing module 'm01_couplers_imp_FF3AZQ' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:271] INFO: [Synth 8-638] synthesizing module 'm02_couplers_imp_L8N2BP' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:588] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_1/synth/axi4_subsys_auto_pc_1.v:53] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_1/synth/axi4_subsys_auto_pc_1.v:53] INFO: [Synth 8-256] done synthesizing module 'm02_couplers_imp_L8N2BP' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:588] INFO: [Synth 8-638] synthesizing module 'm03_couplers_imp_1MMZOD7' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:905] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_2/synth/axi4_subsys_auto_pc_2.v:53] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_2/synth/axi4_subsys_auto_pc_2.v:53] INFO: [Synth 8-256] done synthesizing module 'm03_couplers_imp_1MMZOD7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:905] INFO: [Synth 8-638] synthesizing module 'm04_couplers_imp_1FSUCEB' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1222] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_3/synth/axi4_subsys_auto_pc_3.v:53] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_3/synth/axi4_subsys_auto_pc_3.v:53] INFO: [Synth 8-256] done synthesizing module 'm04_couplers_imp_1FSUCEB' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1222] INFO: [Synth 8-638] synthesizing module 'm05_couplers_imp_ADRT99' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1539] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_4/synth/axi4_subsys_auto_pc_4.v:53] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_4/synth/axi4_subsys_auto_pc_4.v:53] INFO: [Synth 8-256] done synthesizing module 'm05_couplers_imp_ADRT99' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1539] INFO: [Synth 8-638] synthesizing module 'm06_couplers_imp_Q7JFB2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1856] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_5/synth/axi4_subsys_auto_pc_5.v:53] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_5/synth/axi4_subsys_auto_pc_5.v:53] INFO: [Synth 8-256] done synthesizing module 'm06_couplers_imp_Q7JFB2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1856] INFO: [Synth 8-638] synthesizing module 's00_couplers_imp_IY3DNS' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2169] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_6' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_6/synth/axi4_subsys_auto_pc_6.v:53] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_6' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_6/synth/axi4_subsys_auto_pc_6.v:53] INFO: [Synth 8-256] done synthesizing module 's00_couplers_imp_IY3DNS' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2169] INFO: [Synth 8-638] synthesizing module 's01_couplers_imp_1OXAPVA' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2488] INFO: [Synth 8-256] done synthesizing module 's01_couplers_imp_1OXAPVA' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2488] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_xbar_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xbar_0/synth/axi4_subsys_xbar_0.v:53] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_axi_crossbar' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4871] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_crossbar' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2232] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_si_transactor' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_addr_decoder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_carry_and' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:60] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_carry_and' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:60] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_addr_decoder' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_28_axic_srl_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:694] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_28_ndeep_srl' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:1129] INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133887] INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133887] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_28_ndeep_srl' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:1129] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_28_axic_srl_fifo' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:694] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85238] INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:85238] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_si_transactor' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_si_transactor__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_si_transactor__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_splitter' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_splitter' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_wdata_router' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4724] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:884] INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:982] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:884] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_wdata_router' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4724] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_si_transactor__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_arbiter_resp' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:1020] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_arbiter_resp' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:1020] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_si_transactor__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_si_transactor__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_si_transactor__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3791] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_addr_decoder__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_addr_decoder__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_28_axic_srl_fifo__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:694] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_28_axic_srl_fifo__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:694] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_wdata_mux' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4550] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:884] INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:982] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:884] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_wdata_mux' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4550] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized8' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:982] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'reg_slice_mi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3116] INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3626] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_interconnect_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2824] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_quad_spi_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/synth/axi4_subsys_axi_quad_spi_0_0.vhd:97] Parameter Async_Clk bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SELECT_XPM bound to: 0 - type: integer Parameter C_SUB_FAMILY bound to: virtex7 - type: string Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer Parameter C_XIP_MODE bound to: 0 - type: integer Parameter C_XIP_PERF_MODE bound to: 1 - type: integer Parameter C_BYTE_LEVEL_INTERRUPT_EN bound to: 0 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 16 - type: integer Parameter C_SCK_RATIO bound to: 16 - type: integer Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 4 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_S_AXI4_BASEADDR bound to: 32'b11111111111111111111111111111111 Parameter C_S_AXI4_HIGHADDR bound to: 32'b00000000000000000000000000000000 Parameter C_LSB_STUP bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_quad_spi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36578] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_top' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34840] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized49' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized49' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized50' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized50' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized51' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized51' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'qspi_core_interface' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:19067] INFO: [Synth 8-638] synthesizing module 'reset_sync_module' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:2378] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'reset_sync_module' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:2378] INFO: [Synth 8-638] synthesizing module 'cross_clk_sync_fifo_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:14826] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cross_clk_sync_fifo_1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:14826] Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 1f1f - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:506] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1214] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1281] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1303] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized6' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized6' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_28_counter_f' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:642] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_28_counter_f' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:642] INFO: [Synth 8-638] synthesizing module 'async_fifo_fg__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/1531/hdl/lib_fifo_v1_0_rfs.vhd:246] Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1214] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1281] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1303] INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/1531/hdl/lib_fifo_v1_0_rfs.vhd:246] INFO: [Synth 8-638] synthesizing module 'qspi_fifo_ifmodule' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:13367] INFO: [Synth 8-256] done synthesizing module 'qspi_fifo_ifmodule' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:13367] INFO: [Synth 8-638] synthesizing module 'qspi_occupancy_reg' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:3575] INFO: [Synth 8-256] done synthesizing module 'qspi_occupancy_reg' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:3575] INFO: [Synth 8-638] synthesizing module 'qspi_mode_0_module' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:8689] Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'qspi_mode_0_module' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:8689] INFO: [Synth 8-638] synthesizing module 'qspi_cntrl_reg' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:13716] INFO: [Synth 8-256] done synthesizing module 'qspi_cntrl_reg' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:13716] INFO: [Synth 8-638] synthesizing module 'qspi_status_slave_sel_reg' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:2604] INFO: [Synth 8-256] done synthesizing module 'qspi_status_slave_sel_reg' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:2604] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_28_soft_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:838] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_28_soft_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:838] INFO: [Synth 8-638] synthesizing module 'interrupt_control__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d8cc/hdl/interrupt_control_v3_1_vh_rfs.vhd:257] INFO: [Synth 8-256] done synthesizing module 'interrupt_control__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d8cc/hdl/interrupt_control_v3_1_vh_rfs.vhd:257] INFO: [Synth 8-256] done synthesizing module 'qspi_core_interface' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:19067] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_top' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34840] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36578] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_quad_spi_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/synth/axi4_subsys_axi_quad_spi_0_0.vhd:97] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_jtag_axi_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:103] Parameter RD_TXN_QUEUE_LENGTH bound to: 1 - type: integer Parameter WR_TXN_QUEUE_LENGTH bound to: 1 - type: integer Parameter M_AXI_ID_WIDTH bound to: 1 - type: integer Parameter M_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter FAMILY bound to: virtex7 - type: string Parameter M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter M_HAS_BURST bound to: 1 - type: integer Parameter PROTOCOL bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_jtag_axi_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:103] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.vhd:100] Parameter C_INSTANCE bound to: axi4_subsys_xadc_wiz_0_0_axi_xadc - type: string Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_INCLUDE_INTR bound to: 1 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_xadc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_axi_xadc.vhd:235] Parameter C_INSTANCE bound to: axi4_subsys_xadc_wiz_0_0_axi_xadc - type: string Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_INCLUDE_INTR bound to: 1 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_lite_ipif' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_axi_lite_ipif.vhd:241] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000001111111111 Parameter C_USE_WSTRB bound to: 1 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:227] Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 Parameter C_IPIF_ABUS_WIDTH bound to: 11 - type: integer Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000001111111111 Parameter C_USE_WSTRB bound to: 1 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_address_decoder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_address_decoder.vhd:176] Parameter C_BUS_AWIDTH bound to: 10 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000001111111111 Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 10 - type: integer Parameter C_BAR bound to: 10'b0000000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 10 - type: integer Parameter C_BAR bound to: 10'b0001000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized25' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 1 - type: integer Parameter C_AW bound to: 10 - type: integer Parameter C_BAR bound to: 10'b1000000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized25' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_address_decoder' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_address_decoder.vhd:176] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:381] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:227] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_lite_ipif' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_axi_lite_ipif.vhd:241] Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter CE_NUMBERS bound to: 9 - type: integer Parameter IP_INTR_NUM bound to: 17 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string Parameter MUX_ADDR_NO bound to: 5 - type: integer INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_xadc_core_drp' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_xadc_core_drp.vhd:186] Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter CE_NUMBERS bound to: 9 - type: integer Parameter IP_INTR_NUM bound to: 17 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string Parameter MUX_ADDR_NO bound to: 5 - type: integer Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0010000110100000 Parameter INIT_42 bound to: 16'b0000010000000000 Parameter INIT_48 bound to: 16'b0111111100000001 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101011111100100 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1100101000110011 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101001011000110 Parameter INIT_56 bound to: 16'b1001010101010101 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter INIT_5C bound to: 16'b0101000100010001 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_xadc_core_drp' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_xadc_core_drp.vhd:186] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_soft_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_soft_reset.vhd:142] Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer Parameter C_RESET_WIDTH bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_soft_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_soft_reset.vhd:142] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_interrupt_control' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_interrupt_control.vhd:240] Parameter C_NUM_CE bound to: 16 - type: integer Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 544'b0000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101 Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool Parameter C_IPIF_DWIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_interrupt_control' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_interrupt_control.vhd:240] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_xadc' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_axi_xadc.vhd:235] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.vhd:100] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4668] Parameter DEVICE_ID bound to: 28'b0011011001010001000010010011 Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_wrapper' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:80] INFO: [Synth 8-256] done synthesizing module 'ROD_system' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:204] INFO: [Synth 8-638] synthesizing module 'aurora_64b_rx_12ch' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:356] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_exdes' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:101] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_support' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support.vhd:156] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_CLOCK_MODULE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_clock_module.vhd:85] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_CLOCK_MODULE' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_clock_module.vhd:85] INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_SUPPORT_RESET_LOGIC' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:81] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_cdc_sync_exdes' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:153] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_cdc_sync_exdes' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:153] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_SUPPORT_RESET_LOGIC' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:81] INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_gt_common_wrapper' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_gt_common_wrapper.vhd:84] Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_gt_common_wrapper' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_gt_common_wrapper.vhd:84] INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/aurora_rx_1q_stub.vhdl:175] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_support' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support.vhd:156] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_exdes' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:101] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_exdes' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:108] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_support' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:155] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_CLOCK_MODULE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_clock_module.vhd:85] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_CLOCK_MODULE' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_clock_module.vhd:85] INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_SUPPORT_RESET_LOGIC' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:81] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_cdc_sync_exdes' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:153] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_cdc_sync_exdes' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:153] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_SUPPORT_RESET_LOGIC' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:81] INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_gt_common_wrapper' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_gt_common_wrapper.vhd:93] Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_gt_common_wrapper' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_gt_common_wrapper.vhd:93] INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/aurora_rx_4l_64b_stub.vhdl:180] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_support' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:155] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_exdes' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:108] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 0 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_exdes__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:108] Parameter USE_COMMON_BLOCK bound to: 0 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_support__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:155] Parameter USE_COMMON_BLOCK bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_support__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:155] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_exdes__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:108] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool WARNING: [Synth 8-5640] Port 'ck_pwr_dnb' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:542] WARNING: [Synth 8-5640] Port 'ref_ck_sel' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:542] WARNING: [Synth 8-5640] Port 'ck_syncb' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:542] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_exdes' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:158] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_support' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_support.vhd:148] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_gt_usrclk_source.vhd:87] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_GT_USRCLK_SOURCE' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_gt_usrclk_source.vhd:87] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/rod_RO_Tx_stub.vhdl:52] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_support' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_support.vhd:148] INFO: [Synth 8-638] synthesizing module 'vio_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/vio_0_stub.vhdl:15] INFO: [Synth 8-638] synthesizing module 'ila_1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_1_stub.vhdl:15] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_exdes' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:158] Parameter COUNTER_WIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] WARNING: [Synth 8-5640] Port 'gt0_rxusrclk_mux' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:580] INFO: [Synth 8-638] synthesizing module 'combined_ttc_rx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:103] WARNING: [Synth 8-5640] Port 'gt0_rxpcommaalignen_in' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:113] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_support' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:174] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_usrclk_source.vhd:87] INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_GT_USRCLK_SOURCE' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_usrclk_source.vhd:87] INFO: [Synth 8-638] synthesizing module 'MGT_combined_ttc_rx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/MGT_combined_ttc_rx_stub.vhdl:63] INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_support' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:174] Parameter RX_DATA_WIDTH bound to: 32 - type: integer Parameter RXCTRL_WIDTH bound to: 4 - type: integer Parameter WORDS_IN_BRAM bound to: 512 - type: integer Parameter COMMA_DOUBLE bound to: 16'b0000010010111100 Parameter START_OF_PACKET_CHAR bound to: 32'b10100101000011110000010110111100 INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_GT_FRAME_CHECK' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:124] Parameter RX_DATA_WIDTH bound to: 32 - type: integer Parameter RXCTRL_WIDTH bound to: 4 - type: integer Parameter WORDS_IN_BRAM bound to: 512 - type: integer Parameter CHANBOND_SEQ_LEN bound to: 1 - type: integer Parameter COMMA_DOUBLE bound to: 16'b0000010010111100 Parameter START_OF_PACKET_CHAR bound to: 32'b10100101000011110000010110111100 INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:712] INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_GT_FRAME_CHECK' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:124] INFO: [Synth 8-638] synthesizing module 'vio_ttc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/vio_ttc_stub.vhdl:15] INFO: [Synth 8-638] synthesizing module 'ila_2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_2_stub.vhdl:29] INFO: [Synth 8-638] synthesizing module 'rx_registers' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/rx_registers.vhd:49] INFO: [Synth 8-256] done synthesizing module 'rx_registers' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/rx_registers.vhd:49] INFO: [Synth 8-256] done synthesizing module 'combined_ttc_rx' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:103] INFO: [Synth 8-638] synthesizing module 'aurora_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'aurora_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'pwr_on_timer' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/pwr_on_timer.vhd:45] INFO: [Synth 8-256] done synthesizing module 'pwr_on_timer' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/pwr_on_timer.vhd:45] INFO: [Synth 8-256] done synthesizing module 'aurora_64b_rx_12ch' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:356] INFO: [Synth 8-638] synthesizing module 'fex_rx_checker' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_rx_checker.vhd:48] Parameter fex_check bound to: 1 - type: integer Parameter crc20_G_Poly bound to: 20'b10000011010110011111 INFO: [Synth 8-638] synthesizing module 'backplane_crc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_crc.vhd:53] Parameter fex_check bound to: 1 - type: integer Parameter crc20_G_Poly bound to: 20'b10000011010110011111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'CRC' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'CRC' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-638] synthesizing module 'CRC__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-256] done synthesizing module 'CRC__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/osum_crc9d32.vhd:39] INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/osum_crc9d32.vhd:39] INFO: [Synth 8-256] done synthesizing module 'backplane_crc' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_crc.vhd:53] INFO: [Synth 8-638] synthesizing module 'chan_crc_ila' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/chan_crc_ila_stub.vhdl:24] INFO: [Synth 8-256] done synthesizing module 'fex_rx_checker' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_rx_checker.vhd:48] WARNING: [Synth 8-5640] Port 'aurora_user_clock_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_22' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_user_clock_23' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_22' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_23' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_22' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'aurora_chan_control_23' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_22' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 'bp_data_23' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_22' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tvalid_23' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_22' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tlast_23' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_22' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axis_tready_23' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_12' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_13' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_14' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_15' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_16' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_17' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_18' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_19' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_20' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] WARNING: [Synth 8-5640] Port 's_axi_ufc_rx_tdata_21' is missing in component declaration [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:856] INFO: [Common 17-14] Message 'Synth 8-5640' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter CRC20_G_Poly bound to: 20'b10000011010110011111 Parameter jfex bound to: 0 - type: integer Parameter sim bound to: 0 - type: integer Parameter tob_0_flx_bp_link bound to: 0 - type: integer Parameter bulk_0_flx_bp_link bound to: 1 - type: integer Parameter bulk_1_flx_bp_link bound to: 2 - type: integer Parameter bulk_2_flx_bp_link bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_processor' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:500] Parameter SIM bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter crc20_G_Poly bound to: 20'b10000011010110011111 Parameter tob_0_flx_bp_link bound to: 0 - type: integer Parameter bulk_0_flx_bp_link bound to: 1 - type: integer Parameter bulk_1_flx_bp_link bound to: 2 - type: integer Parameter bulk_2_flx_bp_link bound to: 3 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter sim bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'input_fifos' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1080] Parameter sim bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 26 - type: integer Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'backplane_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:78] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 13 - type: integer Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:209] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:210] INFO: [Synth 8-638] synthesizing module 'ipbus_reg_v' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55] INFO: [Synth 8-256] done synthesizing module 'ipbus_reg_v' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55] INFO: [Synth 8-638] synthesizing module 'ipbus_reg_v__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55] INFO: [Synth 8-256] done synthesizing module 'ipbus_reg_v__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:333] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:334] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:368] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:369] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:388] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:389] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:437] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:438] INFO: [Synth 8-638] synthesizing module 'priority_encoder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/priority_encoder.vhd:43] INFO: [Synth 8-256] done synthesizing module 'priority_encoder' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/priority_encoder.vhd:43] Parameter reset_count bound to: 16'b0000001111111111 Parameter count_40_term bound to: 8'b01000101 Parameter count_160_term bound to: 8'b01000101 INFO: [Synth 8-638] synthesizing module 'clock_test_ipbus' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/clock_test_ipbus.vhd:81] Parameter COUNTER_WIDTH_40 bound to: 8 - type: integer Parameter reset_count bound to: 16'b0000001111111111 Parameter count_40_term bound to: 8'b01000101 Parameter count_160_term bound to: 8'b01000101 INFO: [Synth 8-256] done synthesizing module 'clock_test_ipbus' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/clock_test_ipbus.vhd:81] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:581] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:582] INFO: [Synth 8-256] done synthesizing module 'backplane_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:78] INFO: [Synth 8-638] synthesizing module 'ttc_chan_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:84] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 24 - type: integer Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:230] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:231] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:253] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:254] INFO: [Synth 8-638] synthesizing module 'watermark' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watermark.vhd:49] Parameter watermark_width bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'watermark' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watermark.vhd:49] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:291] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:292] INFO: [Synth 8-638] synthesizing module 'threshold_counter' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43] INFO: [Synth 8-256] done synthesizing module 'threshold_counter' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:318] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:319] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:347] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:348] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:364] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:365] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:392] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:393] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:441] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:442] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:458] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:459] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:476] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:477] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:497] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:498] INFO: [Synth 8-638] synthesizing module 'error_counter' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] Parameter cwidth bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'error_counter' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:608] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:609] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:625] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:626] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:642] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:643] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:659] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:660] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:685] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:686] INFO: [Synth 8-256] done synthesizing module 'ttc_chan_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:84] Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] INFO: [Synth 8-256] done synthesizing module 'aurora_pipe' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] INFO: [Synth 8-638] synthesizing module 'dual_input_fifo_4k' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dual_input_fifo_4k.vhd:60] INFO: [Synth 8-638] synthesizing module 'aurora_in_fifo_512' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/aurora_in_fifo_512_stub.vhdl:29] INFO: [Synth 8-638] synthesizing module 'processor_in_fifo_4k' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/processor_in_fifo_4k_stub.vhdl:27] INFO: [Synth 8-256] done synthesizing module 'dual_input_fifo_4k' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dual_input_fifo_4k.vhd:60] INFO: [Synth 8-638] synthesizing module 'ufc_rx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ufc_rx.vhd:69] INFO: [Synth 8-256] done synthesizing module 'ufc_rx' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ufc_rx.vhd:69] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'fex_chan_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:133] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 27 - type: integer Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:395] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:396] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:424] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:425] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:461] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:462] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:488] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:489] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:549] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:550] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:573] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:574] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:612] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:613] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:640] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:641] Parameter COUNTER_WIDTH bound to: 5 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:722] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:723] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:752] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:753] INFO: [Synth 8-638] synthesizing module 'error_counter__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] INFO: [Synth 8-256] done synthesizing module 'error_counter__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_init' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_init.vhd:56] Parameter jfex bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 5 - type: integer Parameter GAP_WIDTH bound to: 20 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'self_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/self_reset.vhd:66] Parameter GAP_WIDTH bound to: 20 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'self_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/self_reset.vhd:66] INFO: [Synth 8-256] done synthesizing module 'channel_init' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_init.vhd:56] INFO: [Synth 8-638] synthesizing module 'ila_self_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_self_reset_stub.vhdl:26] Parameter cwidth bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'edge_error_counter' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] Parameter cwidth bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'edge_error_counter' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:983] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:984] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1005] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1006] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1040] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1041] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1210] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1211] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1244] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1245] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1261] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1262] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1279] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1280] INFO: [Synth 8-638] synthesizing module 'tob_rx_timer' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_rx_timer.vhd:49] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_rx_timer.vhd:59] INFO: [Synth 8-256] done synthesizing module 'tob_rx_timer' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_rx_timer.vhd:49] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1306] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1307] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1323] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1324] INFO: [Synth 8-256] done synthesizing module 'fex_chan_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:133] INFO: [Synth 8-256] done synthesizing module 'channel_fifo' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized3' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized3' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized7' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized7' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized9' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized9' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized9' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized9' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized11' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized11' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized11' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized11' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized13' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized13' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized13' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized13' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized15' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized15' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized15' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized15' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized17' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized17' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized17' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized17' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized19' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized19' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized19' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized19' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized21' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter fifo_instr bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized21' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized21' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized21' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:202] INFO: [Synth 8-256] done synthesizing module 'input_fifos' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1080] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4382] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4387] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4392] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4397] Parameter CRC20_G_Poly bound to: 20'b10000011010110011111 Parameter sim bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'tob_processor' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:368] Parameter sim bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter CRC20_G_Poly bound to: 20'b10000011010110011111 INFO: [Synth 8-638] synthesizing module 'channel_mux' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_mux.vhd:330] INFO: [Synth 8-638] synthesizing module 'onehot_dec' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] Parameter n bound to: 5 - type: integer Parameter m bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'onehot_dec' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] INFO: [Synth 8-256] done synthesizing module 'channel_mux' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_mux.vhd:330] Parameter CRC20_G_Poly bound to: 20'b10000011010110011111 Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ev_builder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:208] Parameter CRC20_G_Poly bound to: 20'b10000011010110011111 Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter event_width bound to: 64 - type: integer Parameter header_width bound to: 64 - type: integer Parameter n bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'vDFF' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ff.vhd:64] Parameter n bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'vDFF' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ff.vhd:64] INFO: [Synth 8-638] synthesizing module 'event_builder_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/event_builder_fifo_stub.vhdl:26] WARNING: [Synth 8-614] signal 'stop_proc' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] WARNING: [Synth 8-614] signal 'L1ID_reg_lt' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] WARNING: [Synth 8-614] signal 'L1ID_reg_gt' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] WARNING: [Synth 8-614] signal 'L1id_ttc_32_reg' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] WARNING: [Synth 8-614] signal 's_tdata' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] WARNING: [Synth 8-614] signal 'l1id_resync_enable' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] WARNING: [Synth 8-614] signal 'hdr_crc_flag' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] WARNING: [Synth 8-614] signal 'l1id_resync_flag' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:815] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1942] INFO: [Synth 8-638] synthesizing module 'tob_timeout' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_timeout.vhd:66] INFO: [Synth 8-256] done synthesizing module 'tob_timeout' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_timeout.vhd:66] INFO: [Synth 8-638] synthesizing module 'hdr_in_crc9' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/hdr_in_crc9.vhd:50] INFO: [Synth 8-256] done synthesizing module 'hdr_in_crc9' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/hdr_in_crc9.vhd:50] INFO: [Synth 8-638] synthesizing module 'event_hdr_crc9' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_hdr_crc9.vhd:61] INFO: [Synth 8-256] done synthesizing module 'event_hdr_crc9' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_hdr_crc9.vhd:61] Parameter crc20_G_Poly bound to: 20'b10000011010110011111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'event_trailer_CRC20' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_trailer_CRC20.vhd:59] Parameter crc20_G_Poly bound to: 20'b10000011010110011111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b11000001101011001111 Parameter G_InitVal bound to: 20'b11111111111111111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'flx_CRC' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/flx_CRC20.vhd:34] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'flx_CRC' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/flx_CRC20.vhd:34] INFO: [Synth 8-256] done synthesizing module 'event_trailer_CRC20' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_trailer_CRC20.vhd:59] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2373] Parameter crc20_G_Poly bound to: 20'b10000011010110011111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_InitVal bound to: 20'b11111111111111111111 Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'trailer_map' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:61] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'onehot_dec__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] Parameter n bound to: 4 - type: integer Parameter m bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'onehot_dec__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] INFO: [Synth 8-256] done synthesizing module 'trailer_map' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:61] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2660] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2814] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2818] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2823] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2828] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2833] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2885] INFO: [Synth 8-638] synthesizing module 'ila_ev_builder' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_ev_builder_stub.vhdl:43] Parameter overflow_clock_count bound to: 8'b00001111 INFO: [Synth 8-638] synthesizing module 'watchdog' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watchdog.vhd:48] Parameter overflow_clock_count bound to: 8'b00001111 INFO: [Synth 8-256] done synthesizing module 'watchdog' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watchdog.vhd:48] INFO: [Synth 8-256] done synthesizing module 'ev_builder' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:208] Parameter COUNTER_WIDTH bound to: 4 - type: integer Parameter sim bound to: 0 - type: integer Parameter timeout_1_default bound to: 16'b0000011000000000 Parameter timeout_n_default bound to: 16'b0000000000110000 INFO: [Synth 8-638] synthesizing module 'tob_proc_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:124] Parameter sim bound to: 0 - type: integer Parameter timeout_1_default bound to: 16'b0000011000000000 Parameter timeout_n_default bound to: 16'b0000000000110000 Parameter wdog_thresh_default bound to: 16'b0010000000000000 INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized5' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 39 - type: integer Parameter SEL_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized5' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:464] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:465] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:500] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:501] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:535] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:536] INFO: [Common 17-14] Message 'Synth 8-6778' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'pkt_capture_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized6' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 8 - type: integer Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized6' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-256] done synthesizing module 'pkt_capture_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] INFO: [Synth 8-638] synthesizing module 'input_capture_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_capture_regs.vhd:42] Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized7' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 9 - type: integer Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter ADDR_WIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_dpram' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_dpram.vhd:35] Parameter ADDR_WIDTH bound to: 4 - type: integer WARNING: [Synth 8-3819] Generic 'data_width' not present in instantiated entity will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_capture_regs.vhd:306] INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_dpram.vhd:35] Parameter ADDR_WIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer Parameter packet_version bound to: 3'b001 Parameter addr_width bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'input_capture' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_capture.vhd:74] Parameter packet_version bound to: 3'b001 Parameter addr_width bound to: 4 - type: integer Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter fex_check bound to: 1 - type: integer Parameter crc20_G_Poly bound to: 20'b10000011010110011111 INFO: [Synth 8-638] synthesizing module 'packet_crc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_crc.vhd:53] Parameter fex_check bound to: 1 - type: integer Parameter crc20_G_Poly bound to: 20'b10000011010110011111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-256] done synthesizing module 'packet_crc' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_crc.vhd:53] INFO: [Synth 8-256] done synthesizing module 'input_capture' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_capture.vhd:74] INFO: [Synth 8-256] done synthesizing module 'input_capture_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_capture_regs.vhd:42] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'd' ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter cwidth bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'edge_error_counter__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] Parameter cwidth bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'edge_error_counter__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] INFO: [Synth 8-638] synthesizing module 'chan_err_map' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/chan_err_map.vhd:65] Parameter jfex bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'chan_err_map' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/chan_err_map.vhd:65] Parameter start_state bound to: 8'b00010010 Parameter stop_state bound to: 8'b00010001 INFO: [Synth 8-638] synthesizing module 'event_timer' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_timer.vhd:53] Parameter start_state bound to: 8'b00010010 Parameter stop_state bound to: 8'b00010001 INFO: [Synth 8-256] done synthesizing module 'event_timer' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_timer.vhd:53] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'Processor_trace_module' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/Processor_trace_module.vhd:54] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized2' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_dpram.vhd:35] Parameter ADDR_WIDTH bound to: 8 - type: integer WARNING: [Synth 8-3819] Generic 'data_width' not present in instantiated entity will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/Processor_trace_module.vhd:261] INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized2' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_dpram.vhd:35] Parameter addr_width bound to: 8 - type: integer Parameter data_width bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'proc_trace' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/proc_trace.vhd:87] Parameter addr_width bound to: 8 - type: integer WARNING: [Synth 8-3819] Generic 'data_width' not present in instantiated entity will be ignored [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/Processor_trace_module.vhd:284] INFO: [Synth 8-256] done synthesizing module 'proc_trace' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/proc_trace.vhd:87] INFO: [Synth 8-256] done synthesizing module 'Processor_trace_module' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/Processor_trace_module.vhd:54] Parameter sim bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'l1id_capture' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/l1id_capture.vhd:60] Parameter sim bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'l1id_capture' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/l1id_capture.vhd:60] INFO: [Synth 8-638] synthesizing module 'threshold_counter__parameterized0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43] INFO: [Synth 8-256] done synthesizing module 'threshold_counter__parameterized0' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43] INFO: [Synth 8-256] done synthesizing module 'tob_proc_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:124] INFO: [Synth 8-638] synthesizing module 'dummy_chan_in' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dummy_chan_in.vhd:47] INFO: [Synth 8-256] done synthesizing module 'dummy_chan_in' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dummy_chan_in.vhd:47] INFO: [Synth 8-256] done synthesizing module 'tob_processor' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:368] INFO: [Synth 8-638] synthesizing module 'ttc_info' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:109] INFO: [Synth 8-638] synthesizing module 'ttc_header_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ttc_header_fifo_stub.vhdl:25] INFO: [Synth 8-638] synthesizing module 'ila_bulk_ttc' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_bulk_ttc_stub.vhdl:27] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:575] INFO: [Synth 8-638] synthesizing module 'ila_ttc_in' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_ttc_in_stub.vhdl:30] INFO: [Synth 8-638] synthesizing module 'ila_ttc_out' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_ttc_out_stub.vhdl:21] INFO: [Synth 8-638] synthesizing module 'l1id_cont_check' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/l1id_cont_check.vhd:60] INFO: [Synth 8-638] synthesizing module 'ila_l1id_cont' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_l1id_cont_stub.vhdl:28] INFO: [Synth 8-256] done synthesizing module 'l1id_cont_check' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/l1id_cont_check.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ttc_info' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:109] Parameter sim bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_processor' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:172] Parameter sim bound to: 0 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:681] INFO: [Synth 8-638] synthesizing module 'bulk_data_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/bulk_data_fifo_stub.vhdl:26] Parameter COUNTER_WIDTH bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_controller' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_controller.vhd:80] WARNING: [Synth 8-614] signal 'stop_proc' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_controller.vhd:168] Parameter n bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'vDFF__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ff.vhd:64] Parameter n bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'vDFF__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ff.vhd:64] INFO: [Synth 8-256] done synthesizing module 'bulk_controller' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_controller.vhd:80] INFO: [Synth 8-638] synthesizing module 'bulk_channel_mux' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_channel_mux.vhd:312] Parameter bp_width bound to: 64 - type: integer Parameter n bound to: 3 - type: integer Parameter m bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_onehot' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_onehot.vhd:46] Parameter n bound to: 3 - type: integer Parameter m bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'bulk_onehot' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_onehot.vhd:46] INFO: [Synth 8-256] done synthesizing module 'bulk_channel_mux' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_channel_mux.vhd:312] Parameter SIM bound to: 0 - type: integer Parameter packet_version bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'bulk_proc_regs' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_proc_regs.vhd:85] Parameter SIM bound to: 0 - type: integer Parameter packet_version bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized8' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 17 - type: integer Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized8' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter packet_version bound to: 3'b001 Parameter sim bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'pkt_capture_regs__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] Parameter packet_version bound to: 3'b001 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'pkt_capture_regs__parameterized1' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] INFO: [Synth 8-256] done synthesizing module 'bulk_proc_regs' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_proc_regs.vhd:85] INFO: [Synth 8-256] done synthesizing module 'bulk_processor' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:172] Parameter sim bound to: 0 - type: integer Parameter sim bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ro_controller' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:51] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-638] synthesizing module 'rod_ROctrl_mux_ila' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/rod_ROctrl_mux_ila_stub.vhdl:20] INFO: [Synth 8-256] done synthesizing module 'ro_controller' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:51] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'combined_ttc_no_mgt' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_no_mgt.vhd:91] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer Parameter RX_DATA_WIDTH bound to: 32 - type: integer Parameter RXCTRL_WIDTH bound to: 4 - type: integer Parameter WORDS_IN_BRAM bound to: 512 - type: integer Parameter COMMA_DOUBLE bound to: 16'b0000010010111100 Parameter START_OF_PACKET_CHAR bound to: 32'b10100101000011110000010110111100 INFO: [Synth 8-638] synthesizing module 'ila_2__parameterized1' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_2_stub.vhdl:29] INFO: [Synth 8-256] done synthesizing module 'combined_ttc_no_mgt' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_no_mgt.vhd:91] INFO: [Synth 8-638] synthesizing module 'cttc_crc_test' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/cttc_crc_test.vhd:50] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/cttc_crc_test.vhd:104] INFO: [Synth 8-638] synthesizing module 'ila_CRC' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_CRC_stub.vhdl:17] INFO: [Synth 8-256] done synthesizing module 'cttc_crc_test' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/cttc_crc_test.vhd:50] INFO: [Synth 8-256] done synthesizing module 'packet_processor' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:500] Parameter DEBUG bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'Full_Mode_Tx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:146] Parameter DEBUG bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'clk_wiz_240' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/clk_wiz_240_stub.vhdl:17] Parameter debug bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'FM_channel' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:126] Parameter debug bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FMchannelTXctrl' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FMchannelTXctrl.vhd:35] INFO: [Synth 8-638] synthesizing module 'pulse_pdxx_pwxx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/pulse_pdxx_pwxx.vhd:25] Parameter pd bound to: 0 - type: integer Parameter pw bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_pdxx_pwxx' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/pulse_pdxx_pwxx.vhd:25] INFO: [Synth 8-638] synthesizing module 'CRC__parameterized4' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter Nbits bound to: 32 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'CRC__parameterized4' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] INFO: [Synth 8-256] done synthesizing module 'FMchannelTXctrl' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FMchannelTXctrl.vhd:35] INFO: [Synth 8-638] synthesizing module 'FIFO34to34b' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FIFO34to34b.vhd:29] INFO: [Synth 8-638] synthesizing module 'fifo1KB_34bit' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/fifo1KB_34bit_stub.vhdl:25] INFO: [Synth 8-256] done synthesizing module 'FIFO34to34b' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FIFO34to34b.vhd:29] INFO: [Synth 8-638] synthesizing module 'vio_fullmode_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/vio_fullmode_reset_stub.vhdl:24] INFO: [Synth 8-638] synthesizing module 'rst_tmr' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/rst_tmr.vhd:47] INFO: [Synth 8-256] done synthesizing module 'rst_tmr' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/rst_tmr.vhd:47] INFO: [Synth 8-638] synthesizing module 'tx_data_mux' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:53] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:56] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:61] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:66] INFO: [Synth 8-256] done synthesizing module 'tx_data_mux' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:53] INFO: [Synth 8-638] synthesizing module 'fm_axi' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/fm_axi.vhd:51] INFO: [Synth 8-256] done synthesizing module 'fm_axi' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/fm_axi.vhd:51] INFO: [Synth 8-638] synthesizing module 'FM_example_emuram' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_emuram.vhd:22] INFO: [Synth 8-638] synthesizing module 'DPram_32b' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/DPram_32b_stub.vhdl:22] INFO: [Synth 8-256] done synthesizing module 'FM_example_emuram' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_emuram.vhd:22] INFO: [Synth 8-638] synthesizing module 'FM_example_FIFOctrl' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_FIFOctrl.vhd:26] INFO: [Synth 8-256] done synthesizing module 'FM_example_FIFOctrl' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_FIFOctrl.vhd:26] INFO: [Synth 8-638] synthesizing module 'fm_status_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/fm_status_fifo_stub.vhdl:22] INFO: [Synth 8-638] synthesizing module 'ila_fullmode' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_fullmode_stub.vhdl:19] INFO: [Synth 8-256] done synthesizing module 'FM_channel' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:126] Parameter debug bound to: 0 - type: integer Parameter NUM_LINKS bound to: 2 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter USE_GREFCLK bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:49] Parameter NUM_LINKS bound to: 2 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter USE_GREFCLK bound to: 0 - type: bool Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:463] Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 Parameter ACJTAG_MODE bound to: 1'b0 Parameter ACJTAG_RESET bound to: 1'b0 Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter A_RXOSCALRESET bound to: 1'b0 Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000 Parameter CFOK_CFG2 bound to: 8'b00100000 Parameter CFOK_CFG3 bound to: 8'b00100000 Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 9 - type: integer Parameter CLK_COR_MIN_LAT bound to: 7 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100 Parameter CPLL_FBDIV bound to: 2 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CLK_PHASE_SEL bound to: 1'b0 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b000 Parameter LOOPBACK_CFG bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000 Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010 Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 16'b0000000000001000 Parameter PMA_RSV5 bound to: 4'b0000 Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: TRUE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011000 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 12'b000000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: FALSE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOOB_CLK_CFG bound to: PMA - type: string Parameter RXOSCALRESET_TIME bound to: 5'b00011 Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b110000000000000000000010 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPI_CFG0 bound to: 2'b00 Parameter RXPI_CFG1 bound to: 2'b00 Parameter RXPI_CFG2 bound to: 2'b00 Parameter RXPI_CFG3 bound to: 2'b11 Parameter RXPI_CFG4 bound to: 1'b1 Parameter RXPI_CFG5 bound to: 1'b1 Parameter RXPI_CFG6 bound to: 3'b001 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: OFF - type: string Parameter RXSYNC_MULTILANE bound to: 1'b0 Parameter RXSYNC_OVRD bound to: 1'b0 Parameter RXSYNC_SKIP_DA bound to: 1'b0 Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 10 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b01 Parameter RX_CM_TRIM bound to: 4'b0000 Parameter RX_DATA_WIDTH bound to: 20 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFELPM_CFG0 bound to: 4'b0110 Parameter RX_DFELPM_CFG1 bound to: 1'b0 Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 Parameter RX_DFE_AGC_CFG1 bound to: 3'b010 Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_H6_CFG bound to: 12'b000000100000 Parameter RX_DFE_H7_CFG bound to: 12'b000000100000 Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111 Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXREC - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b111 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 Parameter TERM_RCAL_OVRD bound to: 3'b000 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 Parameter TXBUF_EN bound to: TRUE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 12'b000000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: FALSE - type: string Parameter TXOOB_CFG bound to: 1'b0 Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPI_CFG0 bound to: 2'b00 Parameter TXPI_CFG1 bound to: 2'b00 Parameter TXPI_CFG2 bound to: 2'b00 Parameter TXPI_CFG3 bound to: 1'b0 Parameter TXPI_CFG4 bound to: 1'b0 Parameter TXPI_CFG5 bound to: 3'b100 Parameter TXPI_GREY_SEL bound to: 1'b0 Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string Parameter TXPI_PPM_CFG bound to: 8'b00000000 Parameter TXPI_SYNFREQ_PPM bound to: 3'b001 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TXSYNC_MULTILANE bound to: 1'b0 Parameter TXSYNC_OVRD bound to: 1'b0 Parameter TXSYNC_SKIP_DA bound to: 1'b0 Parameter TX_CLK25_DIV bound to: 10 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 40 - type: integer Parameter TX_DEEMPH0 bound to: 6'b000000 Parameter TX_DEEMPH1 bound to: 6'b000000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXOUT - type: string Parameter UCODEER_CLR bound to: 1'b0 Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_RX_STARTUP_FSM' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:623] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_sync_block' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:1386] Parameter INITIALISE bound to: 6'b000000 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_sync_block' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:1386] INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_RX_STARTUP_FSM' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:623] Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 Parameter ACJTAG_MODE bound to: 1'b0 Parameter ACJTAG_RESET bound to: 1'b0 Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter A_RXOSCALRESET bound to: 1'b0 Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000 Parameter CFOK_CFG2 bound to: 8'b00100000 Parameter CFOK_CFG3 bound to: 8'b00100000 Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 9 - type: integer Parameter CLK_COR_MIN_LAT bound to: 7 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100 Parameter CPLL_FBDIV bound to: 2 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CLK_PHASE_SEL bound to: 1'b0 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b000 Parameter LOOPBACK_CFG bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000 Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010 Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 16'b0000000000001000 Parameter PMA_RSV5 bound to: 4'b0000 Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: TRUE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011000 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 12'b000000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: FALSE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOOB_CLK_CFG bound to: PMA - type: string Parameter RXOSCALRESET_TIME bound to: 5'b00011 Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b110000000000000000000010 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPI_CFG0 bound to: 2'b00 Parameter RXPI_CFG1 bound to: 2'b00 Parameter RXPI_CFG2 bound to: 2'b00 Parameter RXPI_CFG3 bound to: 2'b11 Parameter RXPI_CFG4 bound to: 1'b1 Parameter RXPI_CFG5 bound to: 1'b1 Parameter RXPI_CFG6 bound to: 3'b001 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: OFF - type: string Parameter RXSYNC_MULTILANE bound to: 1'b0 Parameter RXSYNC_OVRD bound to: 1'b0 Parameter RXSYNC_SKIP_DA bound to: 1'b0 Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 10 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b01 Parameter RX_CM_TRIM bound to: 4'b0000 Parameter RX_DATA_WIDTH bound to: 20 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFELPM_CFG0 bound to: 4'b0110 Parameter RX_DFELPM_CFG1 bound to: 1'b0 Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 Parameter RX_DFE_AGC_CFG1 bound to: 3'b010 Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_H6_CFG bound to: 12'b000000100000 Parameter RX_DFE_H7_CFG bound to: 12'b000000100000 Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111 Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXREC - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b111 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 Parameter TERM_RCAL_OVRD bound to: 3'b000 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 Parameter TXBUF_EN bound to: TRUE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 12'b000000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: FALSE - type: string Parameter TXOOB_CFG bound to: 1'b0 Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPI_CFG0 bound to: 2'b00 Parameter TXPI_CFG1 bound to: 2'b00 Parameter TXPI_CFG2 bound to: 2'b00 Parameter TXPI_CFG3 bound to: 1'b0 Parameter TXPI_CFG4 bound to: 1'b0 Parameter TXPI_CFG5 bound to: 3'b100 Parameter TXPI_GREY_SEL bound to: 1'b0 Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string Parameter TXPI_PPM_CFG bound to: 8'b00000000 Parameter TXPI_SYNFREQ_PPM bound to: 3'b001 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TXSYNC_MULTILANE bound to: 1'b0 Parameter TXSYNC_OVRD bound to: 1'b0 Parameter TXSYNC_SKIP_DA bound to: 1'b0 Parameter TX_CLK25_DIV bound to: 10 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 40 - type: integer Parameter TX_DEEMPH0 bound to: 6'b000000 Parameter TX_DEEMPH1 bound to: 6'b000000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXOUT - type: string Parameter UCODEER_CLR bound to: 1'b0 Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_TX_STARTUP_FSM' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:51] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_TX_STARTUP_FSM' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:51] INFO: [Synth 8-638] synthesizing module 'ila_mgtfsm' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_mgtfsm_stub.vhdl:21] INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:49] Parameter COUNTER_WIDTH bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized7' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized7' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] INFO: [Synth 8-256] done synthesizing module 'Full_Mode_Tx' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:146] Parameter DEBUG bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'Full_Mode_CTTC' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/Full_Mode_CTTC.vhd:186] Parameter DEBUG bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer Parameter debug bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 3 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'FullMode_tx_CTTC_rx_support' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_support.vhd:211] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'FullMode_tx_CTTC_rx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_gt_usrclk_source.vhd:94] INFO: [Synth 8-256] done synthesizing module 'FullMode_tx_CTTC_rx_GT_USRCLK_SOURCE' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_gt_usrclk_source.vhd:94] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-638] synthesizing module 'FullMode_tx_CTTC_rx_common' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_common.vhd:92] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000001011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'FullMode_tx_CTTC_rx_common' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_common.vhd:92] Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'FullMode_tx_CTTC_rx_common_reset' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_common_reset.vhd:91] Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_common_reset.vhd:133] INFO: [Synth 8-256] done synthesizing module 'FullMode_tx_CTTC_rx_common_reset' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_common_reset.vhd:91] INFO: [Synth 8-638] synthesizing module 'FullMode_tx_CTTC_rx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/FullMode_tx_CTTC_rx_stub.vhdl:72] INFO: [Synth 8-638] synthesizing module 'FullMode_tx' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/FullMode_tx_stub.vhdl:49] INFO: [Synth 8-256] done synthesizing module 'FullMode_tx_CTTC_rx_support' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/support/fullmode_tx_cttc_rx_support.vhd:211] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'Full_Mode_CTTC' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/Full_Mode_CTTC.vhd:186] INFO: [Synth 8-638] synthesizing module 'packet_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/packet_fifo.vhd:65] INFO: [Synth 8-638] synthesizing module 'axis_dwidth_64_32' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/axis_dwidth_64_32_stub.vhdl:22] INFO: [Synth 8-638] synthesizing module 'axis_data_fifo_0' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/axis_data_fifo_0_stub.vhdl:26] INFO: [Synth 8-638] synthesizing module 'ila_fifo' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435184-efex-heavyduty-vm1.cern.ch/realtime/ila_fifo_stub.vhdl:26] INFO: [Synth 8-256] done synthesizing module 'packet_fifo' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/packet_fifo.vhd:65] INFO: [Synth 8-638] synthesizing module 'reset_count' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/reset_count.vhd:48] Parameter COUNTER_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'reset_count' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/reset_count.vhd:48] INFO: [Synth 8-637] synthesizing blackbox instance 'backplane_control_ila_5' of component 'bkpln_control_ila' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:3266] INFO: [Synth 8-637] synthesizing blackbox instance 'backplane_control_ila_6' of component 'bkpln_control_ila' [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:3274] INFO: [Synth 8-256] done synthesizing module 'top_rod_efex' (0#1) [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:354] WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA WARNING: [Synth 8-3848] Net rx_fifo_overflow in module/entity eth_7s_rgmii does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:206] WARNING: [Synth 8-6014] Unused sequential element rctr_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:133] WARNING: [Synth 8-3848] Net nuke in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:33] WARNING: [Synth 8-3848] Net soft_rst in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:34] WARNING: [Synth 8-3848] Net userled in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:35] WARNING: [Synth 8-3848] Net tx_axis_fifo_tvalid in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:540] WARNING: [Synth 8-3848] Net tx_axis_fifo_tdata in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:538] WARNING: [Synth 8-3848] Net tx_axis_fifo_tlast in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:541] WARNING: [Synth 8-3848] Net pause_val in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:568] WARNING: [Synth 8-6014] Unused sequential element last_rd_data_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:2387] WARNING: [Synth 8-6014] Unused sequential element single_transfer_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:2405] WARNING: [Synth 8-6014] Unused sequential element bus2ip_mem_cs_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:623] WARNING: [Synth 8-6014] Unused sequential element pr_state_wait_temp_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:624] WARNING: [Synth 8-6014] Unused sequential element mem_cen_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3128] WARNING: [Synth 8-6014] Unused sequential element mem_oen_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3129] WARNING: [Synth 8-6014] Unused sequential element mem_wen_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3130] WARNING: [Synth 8-6014] Unused sequential element addr_cnt_ce_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3157] WARNING: [Synth 8-6014] Unused sequential element addr_cnt_rst_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3158] WARNING: [Synth 8-6014] Unused sequential element Bus2IP_RdReq_d2_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3207] WARNING: [Synth 8-6014] Unused sequential element last_addr1_d1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3253] WARNING: [Synth 8-6014] Unused sequential element last_addr1_d2_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3254] WARNING: [Synth 8-6014] Unused sequential element last_addr1_d3_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:3255] WARNING: [Synth 8-3848] Net addressData_strobe_cmb in module/entity mem_state_machine does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:2187] WARNING: [Synth 8-3848] Net Addr_align in module/entity addr_counter_mux does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4381] WARNING: [Synth 8-3848] Net par_error_addr in module/entity addr_counter_mux does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:4389] WARNING: [Synth 8-6014] Unused sequential element mem_dqt_parity_t_d_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:6904] WARNING: [Synth 8-3848] Net write_data_parity_cmb in module/entity mem_steer does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:5311] WARNING: [Synth 8-3848] Net MemSteer_Mem_DQ_prty_T in module/entity mem_steer does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/2e3c/hdl/emc_common_v3_0_vh_rfs.vhd:5248] WARNING: [Synth 8-6014] Unused sequential element mem_wait_io_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:4253] WARNING: [Synth 8-6014] Unused sequential element or_reduced_rdce_d1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:6320] WARNING: [Synth 8-6014] Unused sequential element bus2ip_wrreq_reg_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:6321] WARNING: [Synth 8-3848] Net cfgclk in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:3659] WARNING: [Synth 8-3848] Net cfgmclk in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:3660] WARNING: [Synth 8-3848] Net eos in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/8852/hdl/axi_emc_v3_0_vh_rfs.vhd:3661] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[8].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[9].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[10].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[11].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[12].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[13].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[14].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[15].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:693] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[8].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[9].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[10].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[11].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[12].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[13].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[14].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[15].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[16].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[17].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[18].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[19].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[20].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[21].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[22].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[23].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:722] WARNING: [Synth 8-6014] Unused sequential element Dual.gpio_Data_In_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6fbe/hdl/axi_gpio_v2_0_vh_rfs.vhd:885] WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] WARNING: [Synth 8-6014] Unused sequential element IP2Bus_Rderrack_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:996] WARNING: [Synth 8-6014] Unused sequential element busip_2_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:1051] WARNING: [Synth 8-6014] Unused sequential element busip_ack_fifo_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:1053] WARNING: [Synth 8-3848] Net Status_read in module/entity axi_hwicap_v3_0_33_ipic_if does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:182] WARNING: [Synth 8-3848] Net CFGCLK in module/entity axi_hwicap_v3_0_33_ipic_if does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:193] WARNING: [Synth 8-3848] Net CFGMCLK in module/entity axi_hwicap_v3_0_33_ipic_if does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:194] WARNING: [Synth 8-3848] Net PREQ in module/entity axi_hwicap_v3_0_33_ipic_if does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:195] WARNING: [Synth 8-6014] Unused sequential element icap_rel_d3_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2212] WARNING: [Synth 8-6014] Unused sequential element icap_ce_cs1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2539] WARNING: [Synth 8-6014] Unused sequential element icap_we_cs1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2540] WARNING: [Synth 8-6014] Unused sequential element int2_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c7aa/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2548] WARNING: [Synth 8-6014] Unused sequential element ro_a_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:2223] WARNING: [Synth 8-6014] Unused sequential element sda_cout_reg_d1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:3614] WARNING: [Synth 8-6014] Unused sequential element gen_stop_and_scl_hi_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:3835] WARNING: [Synth 8-6014] Unused sequential element dynamic_MSMS_d_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/0f29/hdl/axi_iic_v2_1_vh_rfs.vhd:5232] WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596] WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597] WARNING: [Synth 8-6014] Unused sequential element areset_d1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:747] WARNING: [Synth 8-6014] Unused sequential element S_READY_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:786] WARNING: [Synth 8-6014] Unused sequential element gen_single_thread.gen_debug_r_single_thread.debug_r_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4184] WARNING: [Synth 8-6014] Unused sequential element gen_single_thread.active_id_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4142] WARNING: [Synth 8-6014] Unused sequential element gen_single_thread.gen_debug_r_single_thread.debug_r_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4184] WARNING: [Synth 8-6014] Unused sequential element gen_single_thread.active_id_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4142] WARNING: [Synth 8-6014] Unused sequential element gen_multi_thread.gen_thread_loop[0].gen_debug_r_multi_thread.debug_r_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4338] WARNING: [Synth 8-6014] Unused sequential element gen_multi_thread.gen_thread_loop[1].gen_debug_r_multi_thread.debug_r_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4338] WARNING: [Synth 8-6014] Unused sequential element gen_multi_thread.gen_thread_loop[0].gen_debug_r_multi_thread.debug_r_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4338] WARNING: [Synth 8-6014] Unused sequential element gen_multi_thread.gen_thread_loop[1].gen_debug_r_multi_thread.debug_r_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4338] WARNING: [Synth 8-6014] Unused sequential element areset_d1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:747] WARNING: [Synth 8-6014] Unused sequential element S_READY_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:786] WARNING: [Synth 8-6014] Unused sequential element s_ready_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:1034] WARNING: [Synth 8-6014] Unused sequential element areset_d1_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:747] WARNING: [Synth 8-6014] Unused sequential element S_READY_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:786] WARNING: [Synth 8-6014] Unused sequential element s_ready_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v:1034] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[0].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[1].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[2].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[3].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[4].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[5].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[6].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_master_slots[7].gen_mi_write.gen_debug_w.debug_w_beat_cnt_i_reg was removed. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2991] WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:3069] INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net cfgclk in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:19044] WARNING: [Synth 8-3848] Net cfgmclk in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:19045] WARNING: [Synth 8-3848] Net eos in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:19046] WARNING: [Synth 8-3848] Net preq in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:19047] WARNING: [Synth 8-3848] Net di in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:19048] WARNING: [Synth 8-3848] Net s_axi4_awready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34731] WARNING: [Synth 8-3848] Net s_axi4_wready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34739] WARNING: [Synth 8-3848] Net s_axi4_bid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34743] WARNING: [Synth 8-3848] Net s_axi4_bresp in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34744] WARNING: [Synth 8-3848] Net s_axi4_bvalid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34745] WARNING: [Synth 8-3848] Net s_axi4_arready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34759] WARNING: [Synth 8-3848] Net s_axi4_rid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34763] WARNING: [Synth 8-3848] Net s_axi4_rdata in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34764] WARNING: [Synth 8-3848] Net s_axi4_rresp in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34765] WARNING: [Synth 8-3848] Net s_axi4_rlast in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34766] WARNING: [Synth 8-3848] Net s_axi4_rvalid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:34767] WARNING: [Synth 8-3848] Net io0_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36521] WARNING: [Synth 8-3848] Net io0_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36522] WARNING: [Synth 8-3848] Net io1_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36525] WARNING: [Synth 8-3848] Net io1_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36526] WARNING: [Synth 8-3848] Net io2_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36531] WARNING: [Synth 8-3848] Net io2_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36532] WARNING: [Synth 8-3848] Net io3_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36535] WARNING: [Synth 8-3848] Net io3_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36536] WARNING: [Synth 8-3848] Net ss_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36551] WARNING: [Synth 8-3848] Net ss_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/98d8/hdl/axi_quad_spi_v3_2_rfs.vhd:36552] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'common_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:522] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'shelf_addr_sel'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:489] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ipbus_blk'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1915] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ipbus'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:570] WARNING: [Synth 8-3848] Net ipb_clk_i in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:464] WARNING: [Synth 8-3848] Net FP_GP_LED_B in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:146] WARNING: [Synth 8-3848] Net prmry_ack in module/entity aurora_rx_1q_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:135] WARNING: [Synth 8-3848] Net scndry_vect_out in module/entity aurora_rx_1q_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:143] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:737] WARNING: [Synth 8-3848] Net prmry_ack in module/entity aurora_rx_4l_64b_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:135] WARNING: [Synth 8-3848] Net scndry_vect_out in module/entity aurora_rx_4l_64b_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:143] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:747] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:747] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'rod_RO_Tx_support_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:614] WARNING: [Synth 8-3848] Net gt0_cpllrefclklost_i in module/entity rod_RO_Tx_exdes does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:404] WARNING: [Synth 8-3848] Net gt0_cpllreset_i in module/entity rod_RO_Tx_exdes does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:405] WARNING: [Synth 8-3848] Net GT0_DRPDO_COMMON_OUT in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:161] WARNING: [Synth 8-3848] Net GT0_DRPRDY_COMMON_OUT in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:163] WARNING: [Synth 8-3848] Net gt0_qplloutclk_i in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:403] WARNING: [Synth 8-3848] Net gt0_qplloutrefclk_i in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:404] WARNING: [Synth 8-3848] Net slip_assert_r in module/entity sume_RO_Rx_GT_FRAME_CHECK does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:171] WARNING: [Synth 8-3848] Net input_to_chanbond_reg_i in module/entity sume_RO_Rx_GT_FRAME_CHECK does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:189] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gt0_frame_check'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:808] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'inst_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:961] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'sume_RO_Rx_support_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:649] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'combined_ttc'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:1568] WARNING: [Synth 8-3848] Net gt0_RXUSRCLK_MUX in module/entity combined_ttc_rx does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:68] WARNING: [Synth 8-3848] Net gt0_cpllrefclklost_i in module/entity combined_ttc_rx does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:402] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ILA_axi_chan_0'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2383] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ILA_axi_chan_6'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2398] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'crc_checker'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_rx_checker.vhd:97] WARNING: [Synth 8-3848] Net ufc_parity_disable in module/entity ufc_rx does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ufc_rx.vhd:63] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_reset_pulse'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:673] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_reset'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:856] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:1146] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_len_err_counter'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:897] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'header_crc_err_counter'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:836] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'odd_word_counter'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:808] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Frame_error_counter'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:795] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'protocol_error_counter'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:785] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'soft_error_counter'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:776] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'hard_error_counter'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:767] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Aurora_self_reset_count_reg'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1232] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Aurora_channel_up_timer_reg'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1249] WARNING: [Synth 8-3848] Net aurora_chan_control_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:595] WARNING: [Synth 8-3848] Net tob_s_tready_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:598] WARNING: [Synth 8-3848] Net tob_m_tvalid_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:603] WARNING: [Synth 8-3848] Net tob_m_tlast_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:604] WARNING: [Synth 8-3848] Net tob_m_tdata_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:606] WARNING: [Synth 8-3848] Net tob_header_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:607] WARNING: [Synth 8-3848] Net tob_tail_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:608] WARNING: [Synth 8-3848] Net hdr_crc_tag_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:609] WARNING: [Synth 8-3848] Net comb_error_tag_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:610] WARNING: [Synth 8-3848] Net calo_m_tvalid_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:613] WARNING: [Synth 8-3848] Net calo_m_fifo_tlast_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:614] WARNING: [Synth 8-3848] Net calo_s_axis_tready_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:616] WARNING: [Synth 8-3848] Net calo_m_axis_tdata_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:617] WARNING: [Synth 8-3848] Net calo_header_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:618] WARNING: [Synth 8-3848] Net calo_tail_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:619] WARNING: [Synth 8-3848] Net aurora_chan_control_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:635] WARNING: [Synth 8-3848] Net tob_s_tready_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:638] WARNING: [Synth 8-3848] Net tob_m_tvalid_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:643] WARNING: [Synth 8-3848] Net tob_m_tlast_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:644] WARNING: [Synth 8-3848] Net tob_m_tdata_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:646] WARNING: [Synth 8-3848] Net tob_header_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:647] WARNING: [Synth 8-3848] Net tob_tail_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:648] WARNING: [Synth 8-3848] Net hdr_crc_tag_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:649] WARNING: [Synth 8-3848] Net comb_error_tag_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:650] WARNING: [Synth 8-3848] Net calo_m_tvalid_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:653] WARNING: [Synth 8-3848] Net calo_m_fifo_tlast_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:654] WARNING: [Synth 8-3848] Net calo_s_axis_tready_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:656] WARNING: [Synth 8-3848] Net calo_m_axis_tdata_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:657] WARNING: [Synth 8-3848] Net calo_header_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:658] WARNING: [Synth 8-3848] Net calo_tail_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:659] WARNING: [Synth 8-3848] Net aurora_chan_control_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:676] WARNING: [Synth 8-3848] Net tob_s_tready_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:679] WARNING: [Synth 8-3848] Net tob_m_tvalid_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:684] WARNING: [Synth 8-3848] Net tob_m_tlast_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:685] WARNING: [Synth 8-3848] Net tob_m_tdata_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:687] WARNING: [Synth 8-3848] Net tob_header_marker_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:688] WARNING: [Synth 8-3848] Net tob_tail_marker_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:689] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'current_chan_del_reg' and it is trimmed from '5' to '4' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:110] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'state_reg'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:707] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_builder_0'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:1298] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'dbg_trailer_err_map'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2772] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'evnt_trailer_err_map'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2457] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_trailer_crc'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2379] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_header_crc'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2319] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'timeout'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2073] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'wdog_timer'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:3017] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'channel_header_crc'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2294] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'l1id_continuity_checker'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:664] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ttc_input'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4771] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'cttc_crc'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:563] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'readout_controller'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:5270] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ro_crc'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:180] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'CTTC_receiver'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:5730] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'CTTC_receiver'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/Full_Mode_CTTC.vhd:866] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'alt_cttc_crc'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:5795] WARNING: [Synth 8-3936] Found unconnected internal register 'mux_CTTC_MGT_bus_reg' and it is trimmed from '32' to '20' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:5782] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_0'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:340] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_1'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:379] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_0'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/Full_Mode_CTTC.vhd:613] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_1'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/Full_Mode_CTTC.vhd:652] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'reset_timer'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:715] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ctl0'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:872] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ram0'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:816] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u7'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:578] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u5'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:565] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u0'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:418] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'txresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1903] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'g_gt_channel[1].rxresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1820] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'g_gt_channel[0].rxresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1820] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'combined_transceiver'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/fullmode_cttc/Full_Mode_CTTC.vhd:738] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Bulk_0_64_32'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2990] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Bulk_1_64_32'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:3030] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Bulk_2_64_32'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:3069] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'pp_out_fifo_6432'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:3111] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'backplane'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2071] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'alternate_cttc.fm_interface_3'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2902] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'fm_interface_1'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2801] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_builder'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2475] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'reset_top'. This will prevent further optimization [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1837] WARNING: [Synth 8-7129] Port RX_SLIDE in module sume_RO_Rx_GT_FRAME_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port RX_CHANBOND_SEQ_IN in module sume_RO_Rx_GT_FRAME_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port INC_IN in module sume_RO_Rx_GT_FRAME_CHECK is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[31] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[30] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[29] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[28] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[27] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[26] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[25] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[24] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[23] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[22] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[21] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[20] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[19] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[18] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[17] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[16] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[15] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[14] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[13] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[12] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[11] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[10] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[9] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[8] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_status[7] in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port ttc_reset in module combined_ttc_no_mgt is either unconnected or has no load WARNING: [Synth 8-7129] Port gttxn_out[1] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gttxn_out[0] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gttxp_out[1] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gttxp_out[0] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_CTTC_rxoutclk in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port GT1_TXUSRCLK_OUT in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port GT1_TXUSRCLK2_OUT in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[31] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[30] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[29] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[28] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[27] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[26] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[25] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[24] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[23] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[22] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[21] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[20] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[18] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[17] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[16] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[15] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[14] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port FM_CTTC_MGT_bus[12] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port GTGREFCLK_IN in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gtrxp_in[1] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gtrxp_in[0] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gtrxn_in[1] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port gtrxn_in[0] in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port GT1_DATA_VALID_IN in module FullMode_tx_CTTC_rx_support is either unconnected or has no load WARNING: [Synth 8-7129] Port app_clk_in in module FM_channel is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[15] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[14] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[13] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[12] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[11] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[10] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[9] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[8] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[7] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[6] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[5] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[4] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_0[2] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[15] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[14] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[13] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[12] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[11] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[10] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[9] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[8] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[7] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[6] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[5] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[4] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_stat_1[2] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_rxusrclk in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port flx_bp_240_0 in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port flx_bp_240_1 in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[31] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[30] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[29] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[28] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[27] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[26] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[25] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[24] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[23] in module Full_Mode_CTTC is either unconnected or has no load WARNING: [Synth 8-7129] Port full_mode_ctrl_0[22] in module Full_Mode_CTTC is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 3450.469 ; gain = 1015.805 ; free physical = 39223 ; free virtual = 79131 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 3450.469 ; gain = 1015.805 ; free physical = 39223 ; free virtual = 79131 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 3450.469 ; gain = 1015.805 ; free physical = 39223 ; free virtual = 79131 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3450.469 ; gain = 0.000 ; free physical = 39221 ; free virtual = 79129 WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1346 Unisim elements for replacement WARNING: [Netlist 29-432] The IBUFG primitive 'ipbus_blk/clkin1_buf' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx/FullMode_tx_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx/FullMode_tx_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_CRC/ila_CRC_in_context.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_CRC/ila_CRC_in_context.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/rod_efex.gen/sources_1/ip/ila_self_reset/ila_self_reset/ila_self_reset_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_0_64_32/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_0_64_32/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_1_64_32/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_1_64_32/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_2_64_32/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_2_64_32/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'pp_out_fifo_6432/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'pp_out_fifo_6432/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock/packet_processor_clock_in_context.xdc] for cell 'proc_clock_gen' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock/packet_processor_clock_in_context.xdc] for cell 'proc_clock_gen' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_0_64_32/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_0_64_32/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_1_64_32/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_1_64_32/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_2_64_32/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_2_64_32/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'pp_out_fifo_6432/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'pp_out_fifo_6432/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top/vio_top_in_context.xdc] for cell 'top_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top/vio_top_in_context.xdc] for cell 'top_vio' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/polarity' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/polarity' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'ttc_source_sel' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/vio_ttc_in_context.xdc] for cell 'ttc_source_sel' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx/MGT_combined_ttc_rx_in_context.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx/MGT_combined_ttc_rx_in_context.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_l1id_cont/ila_l1id_cont_in_context.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_l1id_cont/ila_l1id_cont_in_context.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_0/data_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_0/data_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_1/data_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_1/data_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_2/data_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_2/data_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/rod_RO_Tx_in_context.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/rod_RO_Tx_in_context.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila_in_context.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila_in_context.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_ev_builder/ila_ev_builder_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_ev_builder/ila_ev_builder_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0/vio_ttc_in_context.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0/vio_ttc_in_context.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo_4k/processor_in_fifo_4k/processor_in_fifo_4k_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo_512/aurora_in_fifo_512/aurora_in_fifo_512_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address/vio_ip_address_in_context.xdc] for cell 'ipbus_blk/ip_addr_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address/vio_ip_address_in_context.xdc] for cell 'ipbus_blk/ip_addr_probe' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1/ila_1_in_context.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1/ila_1_in_context.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc/ila_bulk_ttc_in_context.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc/ila_bulk_ttc_in_context.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/ttc_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/ttc_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila/chan_crc_ila_in_context.xdc] for cell 'ILA_axi_chan_0/ila_crc_check' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila/chan_crc_ila_in_context.xdc] for cell 'ILA_axi_chan_0/ila_crc_check' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila/chan_crc_ila_in_context.xdc] for cell 'ILA_axi_chan_6/ila_crc_check' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila/chan_crc_ila_in_context.xdc] for cell 'ILA_axi_chan_6/ila_crc_check' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_1/clk_blk' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_1/clk_blk' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_0/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_0/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_1/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_1/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_0/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_0/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out/ila_ttc_out_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out/ila_ttc_out_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in/ila_ttc_in_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in/ila_ttc_in_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/ethernet_mac_rgmii/ethernet_mac_rgmii_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/ethernet_mac_rgmii/ethernet_mac_rgmii_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2/rgmii_rx_fifo_2_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2/rgmii_rx_fifo_2_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_1/u0/ila_resetfsm' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_1/u0/ila_resetfsm' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_0/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_6/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_3/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_4/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_5/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_6/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_7/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_8/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_9/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/GEN_BUS2ICAP_RESET/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/FIFO_RST_CDC_PROCESS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc:22] Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] WARNING: [Vivado 12-508] No pins matched 'fm_interface_1/clk_blk/inst/plle2_adv_inst/CLKOUT0'. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:74] WARNING: [Vivado 12-508] No pins matched 'alternate_cttc.fm_interface_3/clk_blk/inst/plle2_adv_inst/CLKOUT0'. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:93] Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_rod_efex_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-1714] 36 XPM XDC files have been applied to the design. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3600.188 ; gain = 0.000 ; free physical = 39107 ; free virtual = 79016 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1103 instances were transformed. BUFGCE => BUFGCTRL: 4 instances BUFGMUX => BUFGCTRL (inverted pins: CE0): 1 instance FD => FDRE: 176 instances FDP => FDPE: 4 instances FDR => FDRE: 762 instances FDRSE => FDRSE (FDRE, LUT4, VCC): 44 instances IBUFG => IBUF: 1 instance IOBUF => IOBUF (IBUF, OBUFT): 23 instances MULT_AND => LUT2: 62 instances MUXCY_L => MUXCY: 24 instances SRL16 => SRL16E: 2 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3600.223 ; gain = 0.000 ; free physical = 39114 ; free virtual = 79024 WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ttc_source_sel' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ILA_axi_chan_0/ila_crc_check' at clock pin 'clk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ILA_axi_chan_6/ila_crc_check' at clock pin 'clk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/clk_blk' at clock pin 'clk_in1' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/polarity' at clock pin 'clk' is different from the actual clock period '9.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_0/ila_fm' at clock pin 'clk' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_0/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b' at clock pin 'rd_clk' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_1/ila_fm' at clock pin 'clk' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_1/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b' at clock pin 'rd_clk' is different from the actual clock period '4.158', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '24.950' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i' at clock pin 'SYSCLK_IN' is different from the actual clock period '9.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '24.950' specified during out-of-context synthesis of instance 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i' at clock pin 'SYSCLK_IN' is different from the actual clock period '9.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/combined_ttc/ila_rx2_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/readout_ctrl/ila_tx0_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/CTTC_receiver/ila_rx2_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/CTTC_receiver/vio_gt_inst' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/alt_cttc_crc/crc_check_ila' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_0/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_1/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_2/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/gen_reg.status_regs/probe_self_reset' at clock pin 'clk' is different from the actual clock period '8.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo' at clock pin 's_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/readout_controller/readout_ctrl_ila2' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/debug_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/event_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/bulk_ttc_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. INFO: [Common 17-14] Message 'Timing 38-316' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:01:24 ; elapsed = 00:01:27 . Memory (MB): peak = 3600.223 ; gain = 1165.559 ; free physical = 39104 ; free virtual = 79013 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'idelay_reset_cnt_reg' in module 'ethernet_mac_rgmii_support_resets' INFO: [Synth 8-802] inferred FSM for state register 'axi_state_reg' in module 'ethernet_mac_rgmii_axi_lite_sm' INFO: [Synth 8-802] inferred FSM for state register 'mdio_access_sm_reg' in module 'ethernet_mac_rgmii_axi_lite_sm' WARNING: [Synth 8-3936] Found unconnected internal register 'pkt_rdy_ipb_clk.pkt_rdy_buf_reg' and it is trimmed from '3' to '2' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:154] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-802] inferred FSM for state register 'emc_addr_ps_reg' in module 'axi_emc_native_interface' INFO: [Synth 8-802] inferred FSM for state register 'crnt_state_reg' in module 'mem_state_machine' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'icap_nstate_cs_reg' in module 'icap_statemachine_shared' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'scl_state_reg' in module 'iic_control' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'iic_control' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'gen_axi.write_cs_reg' in module 'axi_crossbar_v2_1_30_decerr_slave' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized2' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized2' INFO: [Synth 8-802] inferred FSM for state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' in module 'qspi_mode_0_module' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'jtag_axi_v1_2_18_cmd_decode' INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' INFO: [Synth 8-802] inferred FSM for state register 'wr_done_state_reg' in module 'jtag_axi_v1_2_18_jtag_axi_engine' INFO: [Synth 8-802] inferred FSM for state register 'rd_done_state_reg' in module 'jtag_axi_v1_2_18_jtag_axi_engine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * READ_TX_FIFO | 0001 | 0001 AXI_WR_ADDR | 0010 | 0010 AXI_WR_DATA | 0100 | 0100 AXI_WR_RESPONSE | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_18_write_axi' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'jtag_axi_v1_2_18_read_axi' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' INFO: [Synth 8-802] inferred FSM for state register 'rx_state_reg' in module 'FullModeTransceiver_RX_STARTUP_FSM' INFO: [Synth 8-802] inferred FSM for state register 'tx_state_reg' in module 'FullModeTransceiver_TX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE7 | 000000000000001 | 0000 iSTATE6 | 000000000000010 | 0001 iSTATE2 | 000000000000100 | 0010 iSTATE | 000000000001000 | 0011 iSTATE0 | 000000000010000 | 0100 iSTATE13 | 000000000100000 | 0101 iSTATE11 | 000000001000000 | 0110 iSTATE9 | 000000010000000 | 0111 iSTATE10 | 000000100000000 | 1000 iSTATE8 | 000001000000000 | 1001 iSTATE5 | 000010000000000 | 1010 iSTATE3 | 000100000000000 | 1011 iSTATE4 | 001000000000000 | 1100 iSTATE1 | 010000000000000 | 1101 iSTATE12 | 100000000000000 | 1110 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'idelay_reset_cnt_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_support_resets' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0010 | 00 set_data | 1000 | 01 init | 0100 | 10 poll | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'mdio_access_sm_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_axi_lite_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- startup | 000000000000000000000001 | 00000 change_speed | 000000000000000000000010 | 00001 mdio_rd | 000000000000000000000100 | 00010 mdio_poll_check | 000000000000000000001000 | 00011 mdio_1g | 000000000000000000010000 | 00100 mdio_10_100 | 000000000000000000100000 | 00101 mdio_rgmii_rd | 000000000000000001000000 | 00110 mdio_rgmii_rd_poll | 000000000000000010000000 | 00111 mdio_rgmii | 000000000000000100000000 | 01000 mdio_delay_rd | 000000000000001000000000 | 01001 mdio_delay_rd_poll | 000000000000010000000000 | 01010 mdio_delay | 000000000000100000000000 | 01011 mdio_restart | 000000000001000000000000 | 01100 mdio_loopback | 000000000010000000000000 | 01101 mdio_stats | 000000000100000000000000 | 01110 mdio_stats_poll_check | 000000001000000000000000 | 01111 reset_mac_rx | 000000010000000000000000 | 10000 reset_mac_tx | 000000100000000000000000 | 10001 cnfg_mdio | 000001000000000000000000 | 10010 cnfg_flow | 000010000000000000000000 | 10011 cnfg_lo_addr | 000100000000000000000000 | 10101 cnfg_hi_addr | 001000000000000000000000 | 10110 cnfg_filter | 010000000000000000000000 | 10100 check_speed | 100000000000000000000000 | 10111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'axi_state_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_axi_lite_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000001 | 000 rd_last | 0000010 | 010 rd | 0000100 | 001 wr | 0001000 | 011 wr_wait | 0010000 | 100 wr_last | 0100000 | 110 resp | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'emc_addr_ps_reg' using encoding 'one-hot' in module 'axi_emc_native_interface' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000000000000001 | 00000 address_set | 00000000000000010 | 00010 deassert_cen | 00000000000000100 | 00011 write | 00000000000001000 | 00001 dassert_wen | 00000000000010000 | 00110 write_wait | 00000000000100000 | 01000 wait_temp | 00000000001000000 | 01001 assert_cen | 00000000010000000 | 01011 wait_write_ack | 00000000100000000 | 00111 wr_rec_period | 00000001000000000 | 01010 address_rset | 00000010000000000 | 00100 deassert_rcen | 00000100000000000 | 00101 linear_flash_sync_rd | 00001000000000000 | 01101 read | 00010000000000000 | 01100 page_read | 00100000000000000 | 01110 deassert_oen | 01000000000000000 | 01111 wait_rddata_ack | 10000000000000000 | 10000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'crnt_state_reg' using encoding 'one-hot' in module 'mem_state_machine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized0' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- icap_idle | 00000000000001 | 0000 icap_abort0 | 00000000000010 | 0111 icap_write1 | 00000000000100 | 0001 icap_write3 | 00000000001000 | 0011 icap_write4 | 00000000010000 | 0100 icap_write5 | 00000000100000 | 0101 icap_write2 | 00000001000000 | 0010 icap_read1 | 00000010000000 | 0110 icap_abort1 | 00000100000000 | 1001 icap_abort2 | 00001000000000 | 1010 icap_abort3 | 00010000000000 | 1011 icap_abort4 | 00100000000000 | 1100 icap_abort_hang | 01000000000000 | 1000 done | 10000000000000 | 1101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'icap_nstate_cs_reg' using encoding 'one-hot' in module 'icap_statemachine_shared' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000001 | 000 header | 0100000 | 001 ack_header | 1000000 | 010 rcv_data | 0010000 | 011 ack_data | 0001000 | 100 xmit_data | 0000100 | 101 wait_ack | 0000010 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'iic_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- scl_idle | 0000000001 | 0000 start_wait | 0000000010 | 0001 start | 0000000100 | 0010 start_edge | 0000001000 | 0011 scl_low_edge | 0000010000 | 0100 scl_low | 0000100000 | 0101 scl_high_edge | 0001000000 | 0110 scl_high | 0010000000 | 0111 stop_edge | 0100000000 | 1000 stop_wait | 1000000000 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'scl_state_reg' using encoding 'one-hot' in module 'iic_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- SM_IDLE | 0010 | 00 SM_CMD_EN | 1000 | 01 SM_CMD_ACCEPTED | 0100 | 10 SM_DONE_WAIT | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- SM_IDLE | 0010 | 00 SM_CMD_EN | 1000 | 01 SM_CMD_ACCEPTED | 0100 | 10 SM_DONE | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_28_axic_reg_srl_fifo__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- P_WRITE_IDLE | 001 | 00 P_WRITE_DATA | 010 | 01 P_WRITE_RESP | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_axi.write_cs_reg' using encoding 'one-hot' in module 'axi_crossbar_v2_1_30_decerr_slave' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized2' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 0001 | 00 stage1_valid | 0010 | 10 both_stages_valid | 0100 | 11 stage2_valid | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'one-hot' in module 'xpm_fifo_base__parameterized1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 0001 | 00 stage1_valid | 0010 | 10 both_stages_valid | 0100 | 11 stage2_valid | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'one-hot' in module 'xpm_fifo_base__parameterized2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 transfer_okay | 010 | 01 temp_transfer_okay | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' using encoding 'one-hot' in module 'qspi_mode_0_module' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * READ_CMD_FIFO | 01 | 01 AXI_TRANSACTION | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_18_cmd_decode' INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 10 | 10 both_stages_valid | 11 | 11 stage2_valid | 01 | 01 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RDQ_IDLE | 001 | 001 RDQ_CMD_CNT | 010 | 010 RDQ_DONE_CNT | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'rd_done_state_reg' in module 'jtag_axi_v1_2_18_jtag_axi_engine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRQ_IDLE | 001 | 001 WRQ_CMD_CNT | 010 | 010 WRQ_DONE_CNT | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'wr_done_state_reg' in module 'jtag_axi_v1_2_18_jtag_axi_engine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * READ_AXI | 0001 | 0001 AXI_RD_ADDR | 0010 | 0010 AXI_RD_DATA | 0100 | 0100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_18_read_axi' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- sm_idle | 0010 | 00 sm_read | 1000 | 01 sm_write | 0100 | 10 sm_resp | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' INFO: [Synth 8-3971] The signal "ipbus_dpram:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized2:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 00000000001 | 0000 assert_all_resets | 00000000010 | 0001 wait_for_pll_lock | 00000000100 | 0010 release_pll_reset | 00000001000 | 0011 verify_recclk_stable | 00000010000 | 0100 release_mmcm_reset | 00000100000 | 0101 wait_for_rxusrclk | 00001000000 | 0110 wait_reset_done | 00010000000 | 0111 do_phase_alignment | 00100000000 | 1000 monitor_data_valid | 01000000000 | 1001 fsm_done | 10000000000 | 1010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_reg' using encoding 'one-hot' in module 'FullModeTransceiver_RX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000000001 | 0000 assert_all_resets | 0000000010 | 0001 wait_for_pll_lock | 0000000100 | 0010 release_pll_reset | 0000001000 | 0011 wait_for_txoutclk | 0000010000 | 0100 release_mmcm_reset | 0000100000 | 0101 wait_for_txusrclk | 0001000000 | 0110 wait_reset_done | 0010000000 | 0111 do_phase_alignment | 0100000000 | 1000 reset_fsm_done | 1000000000 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_state_reg' using encoding 'one-hot' in module 'FullModeTransceiver_TX_STARTUP_FSM' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:48 ; elapsed = 00:01:52 . Memory (MB): peak = 3604.105 ; gain = 1169.441 ; free physical = 37671 ; free virtual = 77596 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 36 Bit Adders := 1 2 Input 34 Bit Adders := 24 2 Input 32 Bit Adders := 153 2 Input 28 Bit Adders := 2 2 Input 24 Bit Adders := 2 2 Input 20 Bit Adders := 12 2 Input 19 Bit Adders := 2 4 Input 18 Bit Adders := 1 3 Input 17 Bit Adders := 65 2 Input 17 Bit Adders := 7 2 Input 16 Bit Adders := 136 2 Input 15 Bit Adders := 1 2 Input 13 Bit Adders := 5 2 Input 12 Bit Adders := 54 2 Input 10 Bit Adders := 10 3 Input 9 Bit Adders := 1 2 Input 9 Bit Adders := 23 2 Input 8 Bit Adders := 62 4 Input 8 Bit Adders := 2 3 Input 8 Bit Adders := 2 4 Input 7 Bit Adders := 8 2 Input 7 Bit Adders := 13 3 Input 7 Bit Adders := 2 2 Input 6 Bit Adders := 6 4 Input 6 Bit Adders := 6 2 Input 5 Bit Adders := 83 4 Input 5 Bit Adders := 6 3 Input 5 Bit Adders := 4 2 Input 4 Bit Adders := 142 4 Input 4 Bit Adders := 12 3 Input 3 Bit Adders := 1 2 Input 3 Bit Adders := 6 2 Input 2 Bit Adders := 91 4 Input 2 Bit Adders := 2 2 Input 1 Bit Adders := 3 +---XORs : 2 Input 20 Bit XORs := 1224 2 Input 16 Bit XORs := 1 4 Input 16 Bit XORs := 1 2 Input 9 Bit XORs := 2329 2 Input 8 Bit XORs := 7 2 Input 7 Bit XORs := 4 2 Input 6 Bit XORs := 2 2 Input 5 Bit XORs := 4 2 Input 4 Bit XORs := 8 2 Input 1 Bit XORs := 517 4 Input 1 Bit XORs := 78 3 Input 1 Bit XORs := 30 9 Input 1 Bit XORs := 20 21 Input 1 Bit XORs := 10 15 Input 1 Bit XORs := 10 10 Input 1 Bit XORs := 20 19 Input 1 Bit XORs := 10 14 Input 1 Bit XORs := 10 12 Input 1 Bit XORs := 10 7 Input 1 Bit XORs := 10 +---Registers : 128 Bit Registers := 8 120 Bit Registers := 1 112 Bit Registers := 1 96 Bit Registers := 1 80 Bit Registers := 1 65 Bit Registers := 2 64 Bit Registers := 83 63 Bit Registers := 24 57 Bit Registers := 1 56 Bit Registers := 1 48 Bit Registers := 7 45 Bit Registers := 2 42 Bit Registers := 3 38 Bit Registers := 1 37 Bit Registers := 29 36 Bit Registers := 2 34 Bit Registers := 25 32 Bit Registers := 825 28 Bit Registers := 2 24 Bit Registers := 14 22 Bit Registers := 1 21 Bit Registers := 1 20 Bit Registers := 47 19 Bit Registers := 2 18 Bit Registers := 5 17 Bit Registers := 10 16 Bit Registers := 257 15 Bit Registers := 1 14 Bit Registers := 1 13 Bit Registers := 35 12 Bit Registers := 51 11 Bit Registers := 1 10 Bit Registers := 51 9 Bit Registers := 117 8 Bit Registers := 171 7 Bit Registers := 56 6 Bit Registers := 31 5 Bit Registers := 113 4 Bit Registers := 345 3 Bit Registers := 20 2 Bit Registers := 216 1 Bit Registers := 7222 +---RAMs : 256K Bit (8192 X 32 bit) RAMs := 1 64K Bit (8192 X 8 bit) RAMs := 4 32K Bit (4096 X 8 bit) RAMs := 1 8K Bit (256 X 32 bit) RAMs := 1 4K Bit (128 X 32 bit) RAMs := 1 2K Bit (64 X 32 bit) RAMs := 1 512 Bit (16 X 32 bit) RAMs := 4 +---Muxes : 2 Input 128 Bit Muxes := 8 4 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 112 Bit Muxes := 1 2 Input 80 Bit Muxes := 11 2 Input 64 Bit Muxes := 28 5 Input 64 Bit Muxes := 1 4 Input 64 Bit Muxes := 4 2 Input 63 Bit Muxes := 24 2 Input 56 Bit Muxes := 2 3 Input 56 Bit Muxes := 1 13 Input 49 Bit Muxes := 1 2 Input 49 Bit Muxes := 1 16 Input 48 Bit Muxes := 1 19 Input 48 Bit Muxes := 1 2 Input 48 Bit Muxes := 9 4 Input 48 Bit Muxes := 1 5 Input 48 Bit Muxes := 1 2 Input 42 Bit Muxes := 2 3 Input 42 Bit Muxes := 1 2 Input 38 Bit Muxes := 6 3 Input 38 Bit Muxes := 1 2 Input 37 Bit Muxes := 29 3 Input 36 Bit Muxes := 1 45 Input 35 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 2 Input 32 Bit Muxes := 173 5 Input 32 Bit Muxes := 1 16 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 15 24 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 4 6 Input 32 Bit Muxes := 4 13 Input 28 Bit Muxes := 1 2 Input 28 Bit Muxes := 1 24 Input 28 Bit Muxes := 1 2 Input 24 Bit Muxes := 13 24 Input 24 Bit Muxes := 2 5 Input 24 Bit Muxes := 1 3 Input 22 Bit Muxes := 1 2 Input 20 Bit Muxes := 1085 4 Input 18 Bit Muxes := 1 17 Input 17 Bit Muxes := 1 2 Input 17 Bit Muxes := 40 24 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 110 5 Input 16 Bit Muxes := 5 3 Input 16 Bit Muxes := 1 14 Input 16 Bit Muxes := 2 4 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 18 Input 16 Bit Muxes := 1 8 Input 16 Bit Muxes := 3 7 Input 16 Bit Muxes := 4 15 Input 15 Bit Muxes := 1 14 Input 14 Bit Muxes := 1 2 Input 14 Bit Muxes := 18 2 Input 13 Bit Muxes := 51 4 Input 13 Bit Muxes := 2 8 Input 13 Bit Muxes := 3 17 Input 13 Bit Muxes := 2 14 Input 12 Bit Muxes := 1 2 Input 12 Bit Muxes := 54 4 Input 12 Bit Muxes := 2 11 Input 11 Bit Muxes := 2 2 Input 11 Bit Muxes := 12 4 Input 10 Bit Muxes := 7 2 Input 10 Bit Muxes := 36 10 Input 10 Bit Muxes := 3 3 Input 9 Bit Muxes := 3 2 Input 9 Bit Muxes := 2345 5 Input 9 Bit Muxes := 2 2 Input 8 Bit Muxes := 90 24 Input 8 Bit Muxes := 2 6 Input 8 Bit Muxes := 2 5 Input 8 Bit Muxes := 5 4 Input 8 Bit Muxes := 2 7 Input 8 Bit Muxes := 1 17 Input 8 Bit Muxes := 2 3 Input 8 Bit Muxes := 1 7 Input 7 Bit Muxes := 4 2 Input 7 Bit Muxes := 62 3 Input 7 Bit Muxes := 4 2 Input 6 Bit Muxes := 34 3 Input 6 Bit Muxes := 3 6 Input 6 Bit Muxes := 3 5 Input 6 Bit Muxes := 2 8 Input 6 Bit Muxes := 2 7 Input 6 Bit Muxes := 2 10 Input 6 Bit Muxes := 1 40 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 125 17 Input 5 Bit Muxes := 3 6 Input 5 Bit Muxes := 4 4 Input 5 Bit Muxes := 2 3 Input 5 Bit Muxes := 7 5 Input 5 Bit Muxes := 1 28 Input 5 Bit Muxes := 12 25 Input 5 Bit Muxes := 1 27 Input 5 Bit Muxes := 1 18 Input 5 Bit Muxes := 3 2 Input 4 Bit Muxes := 345 3 Input 4 Bit Muxes := 17 7 Input 4 Bit Muxes := 4 5 Input 4 Bit Muxes := 9 4 Input 4 Bit Muxes := 25 6 Input 4 Bit Muxes := 1 14 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 4 10 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 47 4 Input 3 Bit Muxes := 5 3 Input 3 Bit Muxes := 3 7 Input 3 Bit Muxes := 4 14 Input 3 Bit Muxes := 1 24 Input 3 Bit Muxes := 1 8 Input 3 Bit Muxes := 5 13 Input 3 Bit Muxes := 1 5 Input 3 Bit Muxes := 8 9 Input 3 Bit Muxes := 1 6 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 296 3 Input 2 Bit Muxes := 15 4 Input 2 Bit Muxes := 52 5 Input 2 Bit Muxes := 5 24 Input 2 Bit Muxes := 1 6 Input 2 Bit Muxes := 2 11 Input 2 Bit Muxes := 2 13 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2275 7 Input 1 Bit Muxes := 19 5 Input 1 Bit Muxes := 41 17 Input 1 Bit Muxes := 34 4 Input 1 Bit Muxes := 115 6 Input 1 Bit Muxes := 16 14 Input 1 Bit Muxes := 19 3 Input 1 Bit Muxes := 37 10 Input 1 Bit Muxes := 30 15 Input 1 Bit Muxes := 1 24 Input 1 Bit Muxes := 12 9 Input 1 Bit Muxes := 3 11 Input 1 Bit Muxes := 29 13 Input 1 Bit Muxes := 3 8 Input 1 Bit Muxes := 9 16 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3332] Sequential element (register_chan_seq[0].case_i_equal_to_0.rx_chanbond_reg_0) is unused and will be removed from module sume_RO_Rx_GT_FRAME_CHECK__2. WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ck_pwr_dnb_buf) is unused and will be removed from module aurora_64b_rx_12ch. WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ref_ck_sel_buf) is unused and will be removed from module aurora_64b_rx_12ch. WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ck_syncb_buf) is unused and will be removed from module aurora_64b_rx_12ch. INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_hwicap_0/U0/ip2bus_error_i_reg) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_hwicap_0/U0/\XI4_LITE_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_hwicap_0/U0/\XI4_LITE_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/addr_cnt_numonyx_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_write.si_transactor_aw /\gen_single_thread.active_region_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_write.si_transactor_aw /\gen_single_thread.active_region_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_write.si_transactor_aw /\gen_single_thread.active_region_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_write.si_transactor_aw /\gen_single_thread.active_region_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[0].active_region_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[0].active_region_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[0].active_region_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[0].active_region_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[1].active_region_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[1].active_region_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[1].active_region_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_write.si_transactor_aw /\gen_multi_thread.gen_thread_loop[1].active_region_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_read.si_transactor_ar /\gen_single_thread.active_region_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_read.si_transactor_ar /\gen_single_thread.active_region_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_read.si_transactor_ar /\gen_single_thread.active_region_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[0].gen_si_read.si_transactor_ar /\gen_single_thread.active_region_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[0].active_region_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[0].active_region_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[0].active_region_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[0].active_region_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[1].active_region_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[1].active_region_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[1].active_region_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_slave_slots[1].gen_si_read.si_transactor_ar /\gen_multi_thread.gen_thread_loop[1].active_region_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/AXI_EMC_NATIVE_INTERFACE_I/s_axi_mem_bresp_reg_reg[0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_master_slots[7].reg_slice_mi /\b.b_pipe/m_payload_i_reg[0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_master_slots[7].reg_slice_mi /\b.b_pipe/m_payload_i_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_hwicap_0/U0/\XI4_LITE_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_hwicap_0/U0/\XI4_LITE_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[7].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[6].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[5].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[4].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[3].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[2].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[1].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[0].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[7].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[6].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[5].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[4].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[3].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[2].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[1].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[0].RDDATA_REG ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m05_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/s_bresp_acc_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m01_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/s_bresp_acc_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m01_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/s_bresp_acc_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/xbar/\inst/gen_samd.crossbar_samd /\gen_master_slots[0].reg_slice_mi /\b.b_pipe/m_payload_i_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m05_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/s_bresp_acc_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_emc_0/\U0/EMC_CTRL_I/IPIC_IF_I/IP2Bus_Data_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m05_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[0][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m01_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[0][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m01_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[0][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m05_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[1][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m01_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[1][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m05_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[0][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m01_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[1][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m05_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[2][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m01_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[2][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_interconnect_0/\m05_couplers/auto_pc /\inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[1][1] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[7].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[6].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[5].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[4].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[0].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[3].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[4].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[5].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[6].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[14]) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[12]) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[9]) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/ADDR_COUNTER_MUX_I/BEN_STORE_GEN[0].BEN_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/ADDR_COUNTER_MUX_I/BEN_STORE_GEN[1].BEN_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/ADDR_COUNTER_MUX_I/BEN_STORE_GEN[2].BEN_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/ADDR_COUNTER_MUX_I/BEN_STORE_GEN[3].BEN_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[4].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[3].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[2].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[1].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[15].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[14].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[13].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[12].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[11].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[10].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[9].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[8].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[7].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[6].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[5].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[4].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[3].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[2].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[1].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[0].AALIGN_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[1].AALIGN_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[0].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[1].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[2].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[3].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[4].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[5].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[6].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[2].RDDATA_BYTE_GEN[7].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[0].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[1].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[2].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[3].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[4].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[5].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[6].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/RDDATA_GEN[3].RDDATA_BYTE_GEN[7].RDDATA_REG) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3) is unused and will be removed from module axi_gpio. INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3) is unused and will be removed from module axi_gpio. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5587] ROM size for "ip_addr_geo" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "mac_addr_geo" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "ip_addr_geo" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "mac_addr_geo" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "fpga_dna_decode/revision" won't be mapped to RAM because address size (55) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "fpga_dna_decode/serial_num" won't be mapped to RAM because address size (55) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "fpga_dna_decode/revision" won't be mapped to RAM because address size (55) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "fpga_dna_decode/serial_num" won't be mapped to RAM because address size (55) is larger than maximum supported(25) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power INFO: [Synth 8-5546] ROM "fabric/ipb_from_slaves[23][ipb_err]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "gen_reg.registers/fabric/ipb_from_slaves[12][ipb_err]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) WARNING: [Synth 8-3917] design input_fifos__GB7 has port backplane_control[30] driven by constant 1 INFO: [Synth 8-5546] ROM "ctrl_code" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "bit_sel" won't be mapped to RAM because it is too sparse INFO: [Synth 8-3971] The signal "\gen_reg.status_regs /\no_sim_regs.input_capture/capture_lsw/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM capture_lsw/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\gen_reg.status_regs /\no_sim_regs.input_capture/capture_msw/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM capture_msw/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\gen_reg.status_regs /\no_sim_regs.trace_module/trace_mem/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-5544] ROM "controller/ctrl_code" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "controller/ctrl_code" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "controller/ctrl_code" won't be mapped to Block RAM because address size (3) smaller than threshold (5) --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:06:02 ; elapsed = 00:06:29 . Memory (MB): peak = 3612.113 ; gain = 1177.449 ; free physical = 37107 ; free virtual = 77178 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 64 x 32(NO_CHANGE) | W | | 64 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |ipbus/\ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |\gen_reg.status_regs /\no_sim_regs.input_capture | capture_lsw/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\gen_reg.status_regs /\no_sim_regs.input_capture | capture_msw/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\gen_reg.status_regs /\no_sim_regs.trace_module | trace_mem/ram_reg | 256 x 32(READ_FIRST) | W | R | 256 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. Distributed RAM: Preliminary Mapping Report (see note below) +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ |jtag_axi_0/U0 | jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 256 x 32 | RAM64M x 44 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:06:18 ; elapsed = 00:06:45 . Memory (MB): peak = 3612.113 ; gain = 1177.449 ; free physical = 37005 ; free virtual = 77178 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:06:49 ; elapsed = 00:07:17 . Memory (MB): peak = 3612.113 ; gain = 1177.449 ; free physical = 36991 ; free virtual = 77165 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 64 x 32(NO_CHANGE) | W | | 64 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |ipbus/\ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |\gen_reg.status_regs /\no_sim_regs.input_capture | capture_lsw/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\gen_reg.status_regs /\no_sim_regs.input_capture | capture_msw/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\gen_reg.status_regs /\no_sim_regs.trace_module | trace_mem/ram_reg | 256 x 32(READ_FIRST) | W | R | 256 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Distributed RAM: Final Mapping Report +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ |jtag_axi_0/U0 | jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 256 x 32 | RAM64M x 44 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-620] skipping 0-propagation across instance 'ipbus_blk/\axi4_subsys/axi4_subsys_i /i_0/axi_gpio_0/U0/\gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to ' with timing assertions on output pin 'Q' INFO: [Synth 8-7052] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/i_0/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/i_0/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/i_2/tob_processor_0/gen_reg.status_regs/no_sim_regs.input_capture/capture_lsw/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/i_2/tob_processor_0/gen_reg.status_regs/no_sim_regs.input_capture/capture_msw/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/i_2/tob_processor_0/gen_reg.status_regs/no_sim_regs.trace_module/trace_mem/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/i_2/tob_processor_0/gen_reg.status_regs/no_sim_regs.trace_module/trace_mem/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:07:27 ; elapsed = 00:08:07 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36964 ; free virtual = 77150 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.input_capture/capture_lsw/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.input_capture/capture_msw/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.trace_module/trace_mem/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.trace_module/trace_mem/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-4649] Removing BlackBox instance backplane_control_ila_5 of module bkpln_control_ila_bbox_47 having unconnected or no output ports INFO: [Synth 8-4649] Removing BlackBox instance backplane_control_ila_6 of module bkpln_control_ila_bbox_48 having unconnected or no output ports INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[15] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[14] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[13] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[12] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[11] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[10] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[9] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[8] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[7] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[6] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[5] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[4] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[3] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[2] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[1] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[0] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg_reg to handle IOB=TRUE attribute --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/wr_cmd_fifowren_axi_ff_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/rd_cmd_fifowren_axi_ff_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/wr_cmd_fifowren_axi_ff3_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/rd_cmd_fifowren_axi_ff3_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[0] to constant 0 WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt_txfsmresetdone_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt_txfsmresetdone_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[0] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/gt_reset_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/sysreset_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/sysreset_vio_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/gtreset_vio_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[63] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[62] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[61] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[60] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[59] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[58] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[57] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[56] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[55] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[54] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[53] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[52] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[51] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[50] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[49] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[48] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[47] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[46] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[45] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[44] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[43] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[42] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[41] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[40] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[39] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[38] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[37] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[19] to constant 0 INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5410] Found another clock driver clkin1_buf:O [/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:886] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:07:41 ; elapsed = 00:08:22 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36899 ; free virtual = 77153 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:07:42 ; elapsed = 00:08:22 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36899 ; free virtual = 77153 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:07:46 ; elapsed = 00:08:26 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36901 ; free virtual = 77156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:07:46 ; elapsed = 00:08:27 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36901 ; free virtual = 77156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:07:47 ; elapsed = 00:08:27 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36901 ; free virtual = 77156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:07:48 ; elapsed = 00:08:28 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36901 ; free virtual = 77156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +--------------------+-------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +--------------------+-------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |ipbus_rod | trimac_fifo_block/axi_lite_controller/count_shift_reg[20] | 21 | 1 | NO | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/primary_mode.IPAM_block/rarp_request.rarp_block.pkt_mask_reg[36] | 8 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/primary_mode.IPAM_block/rarp_request.rarp_block.pkt_mask_reg[21] | 7 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/IPADDR/rarp_reply.MAC_IP_addr_rx_rarp.pkt_mask_reg[41] | 32 | 1 | YES | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/resend/resend_pkt_id_block.pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[37] | 23 | 1 | YES | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[13] | 12 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[27] | 6 | 2 | YES | NO | YES | 2 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[11] | 8 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.ping.pkt_mask_reg[35] | 23 | 1 | YES | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.ping.pkt_mask_reg[11] | 10 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.arp.pkt_mask_reg[41] | 12 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.arp.pkt_mask_reg[19] | 16 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/rarp_reply.rarp.pkt_mask_reg[15] | 6 | 2 | YES | NO | YES | 2 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.arp.pkt_mask_reg[29] | 10 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/rarp_reply.rarp.pkt_mask_reg[9] | 10 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.arp.pkt_data_reg[111] | 10 | 4 | YES | NO | YES | 4 | 0 | |FullModeTransceiver | cpllpd_wait_reg[95] | 96 | 1 | NO | NO | YES | 0 | 3 | +--------------------+-------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Dynamic Shift Register Report: +------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+ |Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | +------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+ |dsrl | INFERRED_GEN.data_reg[255] | 33 | 33 | 0 | 264 | 132 | 66 | 0 | |dsrl__1 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 | |dsrl__2 | memory_reg[31] | 3 | 3 | 0 | 3 | 0 | 0 | 0 | +------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+-----------------------+----------+ | |BlackBox name |Instances | +------+-----------------------+----------+ |1 |rgmii_rx_fifo_2 | 1| |2 |ethernet_mac_rgmii | 1| |3 |vio_ip_address | 1| |4 |MGT_combined_ttc_rx | 1| |5 |vio_ttc | 5| |6 |ila_2 | 3| |7 |aurora_rx_4l_64b | 6| |8 |aurora_rx_1q | 6| |9 |rod_RO_Tx | 1| |10 |vio_0 | 1| |11 |ila_1 | 1| |12 |ila_l1id_cont | 1| |13 |ttc_header_fifo | 2| |14 |ila_bulk_ttc | 1| |15 |ila_ttc_in | 1| |16 |ila_ttc_out | 1| |17 |rod_ROctrl_mux_ila | 1| |18 |ila_CRC | 1| |19 |bulk_data_fifo | 3| |20 |ila_self_reset | 12| |21 |aurora_in_fifo_512 | 24| |22 |processor_in_fifo_4k | 24| |23 |event_builder_fifo | 2| |24 |ila_ev_builder | 1| |25 |chan_crc_ila | 2| |26 |fifo1KB_34bit | 4| |27 |DPram_32b | 4| |28 |vio_fullmode_reset | 4| |29 |fm_status_fifo | 4| |30 |ila_fullmode | 4| |31 |ila_mgtfsm | 1| |32 |clk_wiz_240 | 2| |33 |FullMode_tx_CTTC_rx | 1| |34 |FullMode_tx | 1| |35 |axis_dwidth_64_32 | 4| |36 |axis_data_fifo_0 | 4| |37 |ila_fifo | 4| |38 |packet_processor_clock | 1| |39 |vio_top | 1| +------+-----------------------+----------+ Report Cell Usage: +------+-----------------------------+------+ | |Cell |Count | +------+-----------------------------+------+ |1 |DPram_32b_bbox | 1| |2 |DPram_32b_bbox_36 | 3| |5 |FullMode_tx_CTTC_rx_bbox | 1| |6 |FullMode_tx_bbox | 1| |7 |MGT_combined_ttc_rx_bbox | 1| |8 |aurora_in_fifo_512_bbox | 1| |9 |aurora_in_fifo_512_bbox_15 | 23| |32 |aurora_rx_1q_bbox | 1| |33 |aurora_rx_1q_bbox_5 | 5| |38 |aurora_rx_4l_64b_bbox | 1| |39 |aurora_rx_4l_64b_bbox_6 | 4| |43 |aurora_rx_4l_64b_bbox | 1| |44 |axis_data_fifo_0_bbox | 1| |45 |axis_data_fifo_0_bbox_45 | 3| |48 |axis_dwidth_64_32_bbox | 1| |49 |axis_dwidth_64_32_bbox_44 | 3| |52 |bulk_data_fifo_bbox | 1| |53 |bulk_data_fifo_bbox_27 | 2| |55 |chan_crc_ila_bbox | 1| |56 |chan_crc_ila_bbox_14 | 1| |57 |clk_wiz_240_bbox | 2| |59 |ethernet_mac_rgmii_bbox | 1| |60 |event_builder_fifo_bbox | 2| |62 |fifo1KB_34bit_bbox | 1| |63 |fifo1KB_34bit_bbox_34 | 3| |66 |fm_status_fifo_bbox | 1| |67 |fm_status_fifo_bbox_37 | 3| |70 |ila_1_bbox | 1| |71 |ila_2_bbox | 2| |73 |ila_2_bbox_30 | 1| |74 |ila_CRC_bbox | 1| |75 |ila_bulk_ttc_bbox | 1| |76 |ila_ev_builder_bbox | 1| |77 |ila_fifo_bbox | 1| |78 |ila_fifo_bbox_46 | 3| |81 |ila_fullmode_bbox | 1| |82 |ila_fullmode_bbox_38 | 3| |85 |ila_l1id_cont_bbox | 1| |86 |ila_mgtfsm_bbox | 1| |87 |ila_self_reset_bbox | 1| |88 |ila_self_reset_bbox_17 | 11| |99 |ila_ttc_in_bbox | 1| |100 |ila_ttc_out_bbox | 1| |101 |packet_processor_clock_bbox | 1| |102 |processor_in_fifo_4k_bbox | 1| |103 |processor_in_fifo_4k_bbox_16 | 23| |126 |rgmii_rx_fifo_2_bbox | 1| |127 |rod_RO_Tx_bbox | 1| |128 |rod_ROctrl_mux_ila_bbox | 1| |129 |ttc_header_fifo_bbox | 2| |131 |vio_0_bbox | 1| |132 |vio_fullmode_reset_bbox | 1| |133 |vio_fullmode_reset_bbox_35 | 3| |136 |vio_ip_address_bbox | 1| |137 |vio_top_bbox | 1| |138 |vio_ttc_bbox | 2| |140 |vio_ttc_bbox_29 | 1| |141 |vio_ttc_bbox | 2| |143 |BUFG | 14| |144 |BUFGCE | 4| |145 |BUFGMUX | 1| |146 |BUFH | 7| |147 |CARRY4 | 2860| |148 |DNA_PORT | 1| |149 |GTHE2_CHANNEL | 2| |150 |GTHE2_COMMON | 18| |151 |IBUFDS_GTE2 | 8| |152 |ICAPE2 | 1| |153 |IDELAYCTRL | 1| |154 |LUT1 | 3578| |155 |LUT2 | 4422| |156 |LUT3 | 4451| |157 |LUT4 | 6141| |158 |LUT5 | 6298| |159 |LUT6 | 13404| |160 |MMCME2_ADV | 1| |161 |MULT_AND | 27| |162 |MUXCY | 27| |163 |MUXCY_L | 18| |164 |MUXF7 | 1700| |165 |MUXF8 | 325| |166 |RAM32M | 10| |167 |RAM32X1D | 4| |168 |RAM64M | 44| |169 |RAMB18E1 | 3| |171 |RAMB36E1 | 22| |176 |SRL16 | 2| |177 |SRL16E | 53| |178 |SRLC32E | 381| |179 |STARTUPE2 | 1| |180 |XADC | 1| |181 |XORCY | 57| |182 |FD | 125| |183 |FDCE | 4915| |184 |FDPE | 100| |185 |FDR | 431| |186 |FDRE | 44327| |187 |FDSE | 1634| |188 |IBUF | 140| |189 |IBUFDS | 1| |190 |IBUFG | 1| |191 |IOBUF | 22| |192 |OBUF | 55| |193 |OBUFT | 2| +------+-----------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:07:48 ; elapsed = 00:08:28 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 36901 ; free virtual = 77156 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 4062 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:07:16 ; elapsed = 00:07:57 . Memory (MB): peak = 3620.117 ; gain = 1035.699 ; free physical = 39076 ; free virtual = 79331 Synthesis Optimization Complete : Time (s): cpu = 00:07:51 ; elapsed = 00:08:33 . Memory (MB): peak = 3620.117 ; gain = 1185.453 ; free physical = 39093 ; free virtual = 79325 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3620.117 ; gain = 0.000 ; free physical = 39089 ; free virtual = 79321 WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 5687 Unisim elements for replacement WARNING: [Netlist 29-432] The IBUFG primitive 'ipbus_blk/clkin1_buf' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. ipbus_blk/clkin1_buf Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. backplane/reset_buf Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design. INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 4 OBUFs to IO ports without IO buffers. INFO: [Chipscope 16-324] Core: ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0 UUID: 72643ffe-b86c-5856-9378-79d72128bd92 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3620.117 ; gain = 0.000 ; free physical = 39051 ; free virtual = 79296 INFO: [Project 1-111] Unisim Transformation Summary: A total of 688 instances were transformed. (MUXCY,XORCY) => CARRY4: 18 instances BUFGCE => BUFGCTRL: 4 instances BUFGMUX => BUFGCTRL (inverted pins: CE0): 1 instance FD => FDRE: 125 instances FDR => FDRE: 431 instances IOBUF => IOBUF (IBUF, OBUFT): 22 instances MULT_AND => LUT2: 27 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 10 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances RAM64M => RAM64M (RAMD64E(x4)): 44 instances SRL16 => SRL16E: 2 instances Synth Design complete | Checksum: cdd8aba5 INFO: [Common 17-83] Releasing license: Synthesis 1921 Infos, 1102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:08:19 ; elapsed = 00:09:01 . Memory (MB): peak = 3620.117 ; gain = 1185.613 ; free physical = 39051 ; free virtual = 79296 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 4852.013; main = 2666.290; forked = 2321.835 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 8602.434; main = 3616.203; forked = 4986.234 Write ShapeDB Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3620.117 ; gain = 0.000 ; free physical = 39031 ; free virtual = 79296 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/top_rod_efex.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 3620.117 ; gain = 0.000 ; free physical = 38973 ; free virtual = 79290 INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_synth.rpt -pb top_rod_efex_utilization_synth.pb source /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-synthesis.tcl INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:Msg-0] Git describe set to: v1.0.5-5811E1B INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/8ZssKaxRN/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v1.0.5-5811E1B... INFO: [Hog:Msg-0] Copying synthesised IP DPram_32b to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FullMode_tx to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FullMode_tx_CTTC_rx to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP MGT_combined_ttc_rx to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP aurora_in_fifo_512 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP aurora_rx_1q to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP aurora_rx_4l_64b to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_axi_emc_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_axi_gpio_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_axi_hwicap_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_axi_iic_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_axi_iic_1_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_axi_interconnect_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_axi_quad_spi_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_jtag_axi_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axi4_subsys_xadc_wiz_0_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axis_data_fifo_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axis_dwidth_64_32 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP axis_input_fifo to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP bulk_data_fifo to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP chan_crc_ila to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP clk_wiz_240 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ethernet_mac_rgmii to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP event_builder_fifo to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP fifo1KB_34bit to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP fm_status_fifo to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_1 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_2 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_CRC to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_bulk_ttc to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_ev_builder to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_fifo to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_fullmode to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_l1id_cont to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_mgtfsm to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_self_reset to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_ttc_in to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ila_ttc_out to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP packet_processor_clock to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP processor_in_fifo_4k to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP rgmii_rx_fifo_2 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP rod_RO_Tx to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP rod_ROctrl_mux_ila to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ttc_header_fifo to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP vio_0 to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP vio_fullmode_reset to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP vio_ip_address to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP vio_top to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP vio_ttc to /eos/user/e/efex/www/firmware/ROD/ip... eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2023.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/ROD/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] All done. INFO: [Common 17-206] Exiting Vivado at Sat Dec 14 15:03:05 2024...