*** Running vivado with args -log clk_wiz_240.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_240.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source clk_wiz_240.tcl -notrace create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1562.781 ; gain = 5.961 ; free physical = 28812 ; free virtual = 76113 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_240 Command: synth_design -top clk_wiz_240 -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 485384 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2507.906 ; gain = 411.684 ; free physical = 25601 ; free virtual = 72904 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'clk_wiz_240' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.v:66] INFO: [Synth 8-6157] synthesizing module 'clk_wiz_240_clk_wiz' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_clk_wiz.v:66] INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT bound to: 30 - type: integer Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 25.000000 - type: double Parameter CLKOUT0_DIVIDE bound to: 12 - type: integer Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 5 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351] INFO: [Synth 8-6157] synthesizing module 'BUFH' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:2198] INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:2198] INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_240_clk_wiz' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_clk_wiz.v:66] INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_240' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.v:66] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2586.875 ; gain = 490.652 ; free physical = 24971 ; free virtual = 72275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2601.719 ; gain = 505.496 ; free physical = 24944 ; free virtual = 72247 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2601.719 ; gain = 505.496 ; free physical = 24944 ; free virtual = 72247 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2607.656 ; gain = 0.000 ; free physical = 24921 ; free virtual = 72224 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_ooc.xdc] for cell 'inst' Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'inst' Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'inst' Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/clk_wiz_240_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/clk_wiz_240_synth_1/dont_touch.xdc] Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'inst' Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2680.594 ; gain = 0.000 ; free physical = 23659 ; free virtual = 70962 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Timing 38-2] Deriving generated clocks Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2680.629 ; gain = 0.000 ; free physical = 23647 ; free virtual = 70950 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23310 ; free virtual = 70614 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23310 ; free virtual = 70614 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/clk_wiz_240_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23310 ; free virtual = 70614 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23298 ; free virtual = 70603 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23253 ; free virtual = 70558 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23118 ; free virtual = 70423 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23118 ; free virtual = 70423 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23118 ; free virtual = 70423 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFH | 3| |2 |PLLE2_ADV | 1| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2680.629 ; gain = 505.496 ; free physical = 23400 ; free virtual = 70709 Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.629 ; gain = 584.406 ; free physical = 23400 ; free virtual = 70709 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2680.629 ; gain = 0.000 ; free physical = 23400 ; free virtual = 70709 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2680.629 ; gain = 0.000 ; free physical = 23672 ; free virtual = 70981 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: a2c88c28 INFO: [Common 17-83] Releasing license: Synthesis 27 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2680.629 ; gain = 1102.004 ; free physical = 23646 ; free virtual = 70954 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1898.283; main = 1586.303; forked = 320.337 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4261.953; main = 2648.582; forked = 1613.371 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/clk_wiz_240_synth_1/clk_wiz_240.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_240, cache-ID = 2797762f23586f8f INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/clk_wiz_240_synth_1/clk_wiz_240.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_240_utilization_synth.rpt -pb clk_wiz_240_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Sat Dec 14 14:50:42 2024...