*** Running vivado with args -log rod_RO_Tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rod_RO_Tx.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source rod_RO_Tx.tcl -notrace create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1562.785 ; gain = 5.961 ; free physical = 27620 ; free virtual = 75031 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: rod_RO_Tx Command: synth_design -top rod_RO_Tx -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 487163 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2509.066 ; gain = 411.715 ; free physical = 24503 ; free virtual = 71914 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx.vhd:141] WARNING: [Synth 8-3819] Generic 'GLOBAL_DATE' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_TIME' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'ROD_JFEX_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'ROD_JFEX_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'OTHERS_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'OTHERS_SHA' not present in instantiated entity will be ignored Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter USE_BUFG bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer INFO: [Synth 8-3491] module 'rod_RO_Tx_init' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:75' bound to instance 'U0' of component 'rod_RO_Tx_init' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx.vhd:235] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_init' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:156] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter USE_BUFG bound to: 0 - type: integer Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string INFO: [Synth 8-3491] module 'rod_RO_Tx_multi_gt' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_multi_gt.vhd:73' bound to instance 'rod_RO_Tx_i' of component 'rod_RO_Tx_multi_gt' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:420] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_multi_gt' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_multi_gt.vhd:150] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b0 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'rod_RO_Tx_GT' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_gt.vhd:72' bound to instance 'gt0_rod_RO_Tx_i' of component 'rod_RO_Tx_GT' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_multi_gt.vhd:293] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_GT' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_gt.vhd:147] Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 Parameter ACJTAG_MODE bound to: 1'b0 Parameter ACJTAG_RESET bound to: 1'b0 Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter A_RXOSCALRESET bound to: 1'b0 Parameter CBCC_DATA_SOURCE_SEL bound to: ENCODED - type: string Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000 Parameter CFOK_CFG2 bound to: 8'b00100000 Parameter CFOK_CFG3 bound to: 8'b00100000 Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 9 - type: integer Parameter CLK_COR_MIN_LAT bound to: 7 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100 Parameter CPLL_FBDIV bound to: 4 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CLK_PHASE_SEL bound to: 1'b0 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b000 Parameter LOOPBACK_CFG bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000 Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010 Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 16'b0000000000001000 Parameter PMA_RSV5 bound to: 4'b0000 Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: TRUE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011000 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 12'b000000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: FALSE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOOB_CLK_CFG bound to: PMA - type: string Parameter RXOSCALRESET_TIME bound to: 5'b00011 Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b110000000000000000000010 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPI_CFG0 bound to: 2'b00 Parameter RXPI_CFG1 bound to: 2'b00 Parameter RXPI_CFG2 bound to: 2'b00 Parameter RXPI_CFG3 bound to: 2'b11 Parameter RXPI_CFG4 bound to: 1'b1 Parameter RXPI_CFG5 bound to: 1'b1 Parameter RXPI_CFG6 bound to: 3'b001 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: OFF - type: string Parameter RXSYNC_MULTILANE bound to: 1'b0 Parameter RXSYNC_OVRD bound to: 1'b0 Parameter RXSYNC_SKIP_DA bound to: 1'b0 Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 7 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b01 Parameter RX_CM_TRIM bound to: 4'b0000 Parameter RX_DATA_WIDTH bound to: 20 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFELPM_CFG0 bound to: 4'b0110 Parameter RX_DFELPM_CFG1 bound to: 1'b0 Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 Parameter RX_DFE_AGC_CFG1 bound to: 3'b100 Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_H6_CFG bound to: 12'b000000100000 Parameter RX_DFE_H7_CFG bound to: 12'b000000100000 Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b10 Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111 Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 Parameter RX_DISPERR_SEQ_MATCH bound to: FALSE - type: string Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXREC - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 Parameter TERM_RCAL_OVRD bound to: 3'b000 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 Parameter TXBUF_EN bound to: TRUE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 12'b000000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: FALSE - type: string Parameter TXOOB_CFG bound to: 1'b0 Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPI_CFG0 bound to: 2'b00 Parameter TXPI_CFG1 bound to: 2'b00 Parameter TXPI_CFG2 bound to: 2'b00 Parameter TXPI_CFG3 bound to: 1'b0 Parameter TXPI_CFG4 bound to: 1'b0 Parameter TXPI_CFG5 bound to: 3'b100 Parameter TXPI_GREY_SEL bound to: 1'b0 Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string Parameter TXPI_PPM_CFG bound to: 8'b00000000 Parameter TXPI_SYNFREQ_PPM bound to: 3'b001 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TXSYNC_MULTILANE bound to: 1'b0 Parameter TXSYNC_OVRD bound to: 1'b0 Parameter TXSYNC_SKIP_DA bound to: 1'b0 Parameter TX_CLK25_DIV bound to: 7 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 40 - type: integer Parameter TX_DEEMPH0 bound to: 6'b000000 Parameter TX_DEEMPH1 bound to: 6'b000000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXOUT - type: string Parameter UCODEER_CLR bound to: 1'b0 Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'gthe2_i' to cell 'GTHE2_CHANNEL' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_gt.vhd:196] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_GT' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_gt.vhd:147] Parameter USE_BUFG bound to: 0 - type: integer INFO: [Synth 8-3491] module 'rod_RO_Tx_cpll_railing' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_cpll_railing.vhd:75' bound to instance 'cpll_railing0_i' of component 'rod_RO_Tx_cpll_railing' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_multi_gt.vhd:366] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_cpll_railing' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_cpll_railing.vhd:88] INFO: [Synth 8-113] binding component instance 'refclk_buf' to cell 'BUFH' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_cpll_railing.vhd:122] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_cpll_railing' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_cpll_railing.vhd:88] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_multi_gt' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_multi_gt.vhd:150] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 0 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'rod_RO_Tx_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:74' bound to instance 'gt0_txresetfsm_i' of component 'rod_RO_Tx_TX_STARTUP_FSM' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:516] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_TX_STARTUP_FSM' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:120] INFO: [Synth 8-3491] module 'rod_RO_Tx_sync_block' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:81' bound to instance 'sync_run_phase_alignment_int' of component 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:276] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:97] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg1' to cell 'FD' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:130] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg2' to cell 'FD' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:140] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg3' to cell 'FD' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:150] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg4' to cell 'FD' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:160] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg5' to cell 'FD' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:170] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg6' to cell 'FD' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:180] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_sync_block' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:97] INFO: [Synth 8-3491] module 'rod_RO_Tx_sync_block' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:81' bound to instance 'sync_tx_fsm_reset_done_int' of component 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:284] INFO: [Synth 8-3491] module 'rod_RO_Tx_sync_block' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:81' bound to instance 'sync_TXRESETDONE' of component 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:301] INFO: [Synth 8-3491] module 'rod_RO_Tx_sync_block' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:81' bound to instance 'sync_time_out_wait_bypass' of component 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:309] INFO: [Synth 8-3491] module 'rod_RO_Tx_sync_block' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:81' bound to instance 'sync_mmcm_lock_reclocked' of component 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:317] INFO: [Synth 8-3491] module 'rod_RO_Tx_sync_block' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:81' bound to instance 'sync_CPLLLOCK' of component 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:337] INFO: [Synth 8-3491] module 'rod_RO_Tx_sync_block' declared at '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd:81' bound to instance 'sync_QPLLLOCK' of component 'rod_RO_Tx_sync_block' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:345] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_TX_STARTUP_FSM' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:120] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_init' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:156] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx' (0#1) [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx.vhd:141] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA WARNING: [Synth 8-6014] Unused sequential element cplllock_prev_reg was removed. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:332] WARNING: [Synth 8-6014] Unused sequential element qplllock_prev_reg was removed. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:333] WARNING: [Synth 8-6014] Unused sequential element cplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:358] WARNING: [Synth 8-6014] Unused sequential element qplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd:373] WARNING: [Synth 8-3848] Net GT0_RX_FSM_RESET_DONE_OUT in module/entity rod_RO_Tx_init does not have driver. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:94] WARNING: [Synth 8-3848] Net gt0_rxdfeagchold_i in module/entity rod_RO_Tx_init does not have driver. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:371] WARNING: [Synth 8-3848] Net gt0_rxdfelfhold_i in module/entity rod_RO_Tx_init does not have driver. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_ro_tx_init.vhd:372] WARNING: [Synth 8-7129] Port QPLLREFCLKLOST in module rod_RO_Tx_TX_STARTUP_FSM is either unconnected or has no load WARNING: [Synth 8-7129] Port GT0_RX_FSM_RESET_DONE_OUT in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port DONT_RESET_ON_DATA_ERROR_IN in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port GT0_DATA_VALID_IN in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_cpllreset_in in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_gtrxreset_in in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_gttxreset_in in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_txuserrdy_in in module rod_RO_Tx_init is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2593.035 ; gain = 495.684 ; free physical = 24121 ; free virtual = 71533 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.879 ; gain = 510.527 ; free physical = 24109 ; free virtual = 71520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.879 ; gain = 510.527 ; free physical = 24109 ; free virtual = 71520 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2613.816 ; gain = 0.000 ; free physical = 24093 ; free virtual = 71505 INFO: [Netlist 29-17] Analyzing 42 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx_ooc.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/rod_RO_Tx_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/rod_RO_Tx_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2757.566 ; gain = 0.000 ; free physical = 23117 ; free virtual = 70529 INFO: [Project 1-111] Unisim Transformation Summary: A total of 42 instances were transformed. FD => FDRE: 42 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2757.602 ; gain = 0.000 ; free physical = 23105 ; free virtual = 70518 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22827 ; free virtual = 70241 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22826 ; free virtual = 70240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/rod_RO_Tx_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22823 ; free virtual = 70236 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'tx_state_reg' in module 'rod_RO_Tx_TX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 assert_all_resets | 0001 | 0001 wait_for_pll_lock | 0010 | 0010 release_pll_reset | 0011 | 0011 wait_for_txoutclk | 0100 | 0100 release_mmcm_reset | 0101 | 0101 wait_for_txusrclk | 0110 | 0110 wait_reset_done | 0111 | 0111 do_phase_alignment | 1000 | 1000 reset_fsm_done | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_state_reg' using encoding 'sequential' in module 'rod_RO_Tx_TX_STARTUP_FSM' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22792 ; free virtual = 70207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 96 Bit Registers := 1 8 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 1 Bit Registers := 20 +---Muxes : 2 Input 8 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 1 Bit Muxes := 10 10 Input 1 Bit Muxes := 17 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port GT0_RX_FSM_RESET_DONE_OUT in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port DONT_RESET_ON_DATA_ERROR_IN in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port GT0_DATA_VALID_IN in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_cpllreset_in in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_gtrxreset_in in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_gttxreset_in in module rod_RO_Tx_init is either unconnected or has no load WARNING: [Synth 8-7129] Port gt0_txuserrdy_in in module rod_RO_Tx_init is either unconnected or has no load INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_QPLLLOCK/data_sync_reg1) is unused and will be removed from module rod_RO_Tx_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_QPLLLOCK/data_sync_reg2) is unused and will be removed from module rod_RO_Tx_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_QPLLLOCK/data_sync_reg3) is unused and will be removed from module rod_RO_Tx_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_QPLLLOCK/data_sync_reg4) is unused and will be removed from module rod_RO_Tx_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_QPLLLOCK/data_sync_reg5) is unused and will be removed from module rod_RO_Tx_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_QPLLLOCK/data_sync_reg6) is unused and will be removed from module rod_RO_Tx_init. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22725 ; free virtual = 70140 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22490 ; free virtual = 69905 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22488 ; free virtual = 69903 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22483 ; free virtual = 69898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22347 ; free virtual = 69765 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22347 ; free virtual = 69765 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22346 ; free virtual = 69763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22346 ; free virtual = 69763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22346 ; free virtual = 69763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22346 ; free virtual = 69763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +---------------+-----------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +---------------+-----------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |rod_RO_Tx_init | rod_RO_Tx_i/cpll_railing0_i/cpllreset_wait_reg[127] | 128 | 1 | NO | NO | YES | 0 | 4 | |rod_RO_Tx_init | rod_RO_Tx_i/cpll_railing0_i/cpllpd_wait_reg[95] | 96 | 1 | NO | NO | YES | 0 | 3 | +---------------+-----------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------------+------+ | |Cell |Count | +------+--------------+------+ |1 |BUFH | 1| |2 |CARRY4 | 9| |3 |GTHE2_CHANNEL | 1| |4 |LUT1 | 7| |5 |LUT2 | 12| |6 |LUT3 | 8| |7 |LUT4 | 16| |8 |LUT5 | 10| |9 |LUT6 | 23| |10 |SRLC32E | 7| |11 |FD | 36| |12 |FDCE | 6| |13 |FDRE | 67| |14 |FDSE | 3| +------+--------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22346 ; free virtual = 69763 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2757.602 ; gain = 510.527 ; free physical = 22330 ; free virtual = 69747 Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2757.602 ; gain = 660.250 ; free physical = 22330 ; free virtual = 69747 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2757.602 ; gain = 0.000 ; free physical = 22320 ; free virtual = 69737 INFO: [Netlist 29-17] Analyzing 45 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2757.602 ; gain = 0.000 ; free physical = 22603 ; free virtual = 70020 INFO: [Project 1-111] Unisim Transformation Summary: A total of 36 instances were transformed. FD => FDRE: 36 instances Synth Design complete | Checksum: 88f635a2 INFO: [Common 17-83] Releasing license: Synthesis 60 Infos, 55 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 2757.602 ; gain = 1179.973 ; free physical = 22602 ; free virtual = 70019 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1960.068; main = 1642.639; forked = 322.321 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4338.961; main = 2757.570; forked = 1613.406 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2781.578 ; gain = 0.000 ; free physical = 22602 ; free virtual = 70019 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/rod_RO_Tx_synth_1/rod_RO_Tx.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rod_RO_Tx, cache-ID = 8e7c713a0955e6f3 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2781.578 ; gain = 0.000 ; free physical = 22601 ; free virtual = 70019 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/rod_RO_Tx_synth_1/rod_RO_Tx.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file rod_RO_Tx_utilization_synth.rpt -pb rod_RO_Tx_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Sat Dec 14 14:55:26 2024...