Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date             : Sat Dec 14 16:27:30 2024
| Host             : efex-heavyduty-vm0.cern.ch running 64-bit unknown
| Command          : report_power -file top_rod_jfex_power_routed.rpt -pb top_rod_jfex_power_summary_routed.pb -rpx top_rod_jfex_power_routed.rpx
| Design           : top_rod_jfex
| Device           : xc7vx550tffg1927-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 10.036       |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 9.499        |
| Device Static (W)        | 0.537        |
| Effective TJA (C/W)      | 0.8          |
| Max Ambient (C)          | 76.5         |
| Junction Temperature (C) | 33.5         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     1.300 |       69 |       --- |             --- |
| Slice Logic              |     0.186 |   440851 |       --- |             --- |
|   LUT as Logic           |     0.138 |   126350 |    346400 |           36.48 |
|   CARRY4                 |     0.017 |     9839 |    108300 |            9.08 |
|   Register               |     0.016 |   229466 |    692800 |           33.12 |
|   Others                 |     0.006 |    25979 |       --- |             --- |
|   LUT as Shift Register  |     0.005 |    12066 |    174200 |            6.93 |
|   LUT as Distributed RAM |     0.003 |     1825 |    174200 |            1.05 |
|   F7/F8 Muxes            |     0.001 |     4370 |    433200 |            1.01 |
|   BUFR                   |     0.000 |        1 |       320 |            0.31 |
| Signals                  |     0.279 |   333895 |       --- |             --- |
| Block RAM                |     0.341 |    684.5 |      1180 |           58.01 |
| MMCM                     |     0.203 |        2 |        20 |           10.00 |
| PLL                      |     0.236 |        2 |        20 |           10.00 |
| I/O                      |     0.068 |      111 |       600 |           18.50 |
| GTH                      |     6.887 |       30 |       --- |             --- |
| XADC                     |    <0.001 |        1 |       --- |             --- |
| Static Power             |     0.537 |          |           |                 |
| Total                    |    10.036 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     3.145 |       2.857 |      0.288 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.305 |       0.250 |      0.056 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.021 |       0.020 |      0.001 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.059 |       0.025 |      0.034 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     3.863 |       3.804 |      0.058 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     1.925 |       1.910 |      0.015 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.020 |       0.020 |      0.000 |       NA    | Unspecified | NA         |
| MGTZVccl  |       1.075 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTZAVcc  |       1.075 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTZVcch  |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 0.8                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 1.2                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| Clock                                                                                                                                                   | Domain                                                                                                                                            | Constraint (ns) |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| CLK_125_pin                                                                                                                                             | CLK_125_pin                                                                                                                                       |             8.0 |
| CLK_40_pin                                                                                                                                              | CLK_40_BUFG                                                                                                                                       |            25.0 |
| CLK_40_pin                                                                                                                                              | CLK_40_pin_P                                                                                                                                      |            25.0 |
| FM_TXOUTCLK                                                                                                                                             | fm_interface_1/u0/I                                                                                                                               |             4.2 |
| GT_REFCLK112                                                                                                                                            | GTCLK_q112_c0p                                                                                                                                    |             6.2 |
| GT_REFCLK115                                                                                                                                            | GTCLK_q115_c0p                                                                                                                                    |             6.2 |
| GT_REFCLK118                                                                                                                                            | GTCLK_q118_c0p                                                                                                                                    |             6.2 |
| GT_REFCLK211                                                                                                                                            | GTCLK_q211_c0p                                                                                                                                    |             6.2 |
| GT_REFCLK214                                                                                                                                            | GTCLK_q214_c0p                                                                                                                                    |             6.2 |
| GT_REFCLK217                                                                                                                                            | GTCLK_q217_c0p                                                                                                                                    |             6.2 |
| GT_REFCLK219                                                                                                                                            | GTCLK_q219_c0p                                                                                                                                    |             6.2 |
| GT_REFCLK_C1_218                                                                                                                                        | GTCLK_q218_c1p                                                                                                                                    |             4.2 |
| alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0/FullMode_tx_CTTC_rx_i/gt0_FullMode_tx_CTTC_rx_i/gthe2_i/RXOUTCLK       | alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0/FullMode_tx_CTTC_rx_i/gt0_FullMode_tx_CTTC_rx_i/gt0_rxoutclk_out |             6.2 |
| alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0/FullMode_tx_CTTC_rx_i/gt0_FullMode_tx_CTTC_rx_i/gthe2_i/TXOUTCLK       | alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0/FullMode_tx_CTTC_rx_i/gt0_FullMode_tx_CTTC_rx_i/gt0_txoutclk_out |             4.2 |
| backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK    | backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK    |             6.2 |
| backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK | backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK    | backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK    |             6.2 |
| backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK | backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK    | backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK    |             6.2 |
| backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK | backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK | backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK | backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK     | backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK  | backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK  |             6.2 |
| backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK     | backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK     | backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK     | backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK  | backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK  |             6.2 |
| backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK            | backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/TXOUTCLK  | backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/TX_OUT_CLK  |             6.2 |
| backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/MGT_combined_ttc_rx_i/gt0_MGT_combined_ttc_rx_i/gthe2_i/RXOUTCLK                          | backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/MGT_combined_ttc_rx_i/gt0_MGT_combined_ttc_rx_i/gt0_rxoutclk_out                    |             6.2 |
| backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/TXOUTCLK                                             | backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gt0_txoutclk_out                                       |             6.2 |
| clk240_clk_wiz_240_1                                                                                                                                    | fm_interface_1/clk_blk/inst/clk240_clk_wiz_240                                                                                                    |             4.2 |
| clk40                                                                                                                                                   | fm_interface_1/clk_blk/inst/clk40_clk_wiz_240                                                                                                     |            10.0 |
| clk40_3                                                                                                                                                 | alternate_cttc.fm_interface_3/clk_blk/inst/clk40_clk_wiz_240                                                                                      |            10.0 |
| clkfbout                                                                                                                                                | ipbus_blk/ipbus/example_clocks/clock_generator/clkfbout                                                                                           |             8.0 |
| clkfbout_clk_wiz_240                                                                                                                                    | alternate_cttc.fm_interface_3/clk_blk/inst/clkfbout_clk_wiz_240                                                                                   |            25.0 |
| clkfbout_clk_wiz_240_1                                                                                                                                  | fm_interface_1/clk_blk/inst/clkfbout_clk_wiz_240                                                                                                  |            25.0 |
| clkfbout_packet_processor_clock                                                                                                                         | proc_clock_gen/inst/clkfbout_packet_processor_clock                                                                                               |            25.0 |
| clkout0                                                                                                                                                 | ipbus_blk/ipbus/example_clocks/clock_generator/clkout0                                                                                            |             8.0 |
| clkout1                                                                                                                                                 | ipbus_blk/ipbus/example_clocks/clock_generator/clkout1                                                                                            |            10.0 |
| clkout2                                                                                                                                                 | ipbus_blk/ipbus/example_clocks/clock_generator/clkout2                                                                                            |             5.0 |
| clkout3                                                                                                                                                 | ipbus_blk/ipbus/example_clocks/clock_generator/clkout3                                                                                            |            32.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK                                                              | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK                                                                                 |            33.0 |
| ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_mdc                                                                       | ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0/ethernet_mac_rgmii_core/man_block.managen/miim_clk_int              |           400.0 |
| pp_clock_packet_processor_clock                                                                                                                         | proc_clock_gen/inst/pp_clock_packet_processor_clock                                                                                               |             5.0 |
| rgmii_rxc                                                                                                                                               | rgmii_rxc                                                                                                                                         |             8.0 |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+------------------------------------+-----------+
| Name                               | Power (W) |
+------------------------------------+-----------+
| top_rod_jfex                       |     9.499 |
|   Bulk_0_64_32                     |     0.043 |
|     ILA_packet_fifo                |     0.027 |
|       U0                           |     0.027 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.014 |
|       inst                         |     0.014 |
|   Bulk_1_64_32                     |     0.042 |
|     ILA_packet_fifo                |     0.027 |
|       U0                           |     0.027 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.014 |
|       inst                         |     0.014 |
|   Bulk_2_64_32                     |     0.043 |
|     ILA_packet_fifo                |     0.027 |
|       U0                           |     0.027 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.014 |
|       inst                         |     0.014 |
|   ILA_axi_chan_0                   |     0.013 |
|     crc_checker                    |     0.002 |
|     ila_crc_check                  |     0.012 |
|       U0                           |     0.012 |
|   ILA_axi_chan_12                  |     0.013 |
|     crc_checker                    |     0.001 |
|     ila_crc_check                  |     0.011 |
|       U0                           |     0.011 |
|   ILA_axi_chan_13                  |     0.013 |
|     crc_checker                    |     0.002 |
|     ila_crc_check                  |     0.012 |
|       U0                           |     0.012 |
|   ILA_axi_chan_14                  |     0.012 |
|     crc_checker                    |     0.001 |
|     ila_crc_check                  |     0.011 |
|       U0                           |     0.011 |
|   ILA_axi_chan_15                  |     0.013 |
|     crc_checker                    |     0.001 |
|     ila_crc_check                  |     0.012 |
|       U0                           |     0.012 |
|   ILA_axi_chan_4                   |     0.010 |
|     U0                             |     0.010 |
|       ila_core_inst                |     0.010 |
|   ILA_axi_chan_5                   |     0.010 |
|     U0                             |     0.010 |
|       ila_core_inst                |     0.010 |
|   ILA_axi_chan_6                   |     0.010 |
|     U0                             |     0.010 |
|       ila_core_inst                |     0.010 |
|   ILA_axi_chan_7                   |     0.010 |
|     U0                             |     0.010 |
|       ila_core_inst                |     0.010 |
|   alternate_cttc.fm_interface_3    |     0.758 |
|     CTTC_receiver                  |     0.036 |
|       gt0_frame_check              |     0.002 |
|       ila_rx2_inst                 |     0.031 |
|       inst_regs                    |     0.001 |
|     chan_0                         |     0.044 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.015 |
|       ram0                         |     0.009 |
|       u5                           |     0.010 |
|       u7                           |     0.005 |
|       vio_fm_reset                 |     0.001 |
|     chan_1                         |     0.044 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.015 |
|       ram0                         |     0.009 |
|       u5                           |     0.010 |
|       u7                           |     0.005 |
|       vio_fm_reset                 |     0.001 |
|     clk_blk                        |     0.118 |
|       inst                         |     0.118 |
|     combined_transceiver           |     0.514 |
|       FullMode_tx_CTTC_rx_init_i   |     0.352 |
|       FullMode_tx_i                |     0.161 |
|       gt_usrclk_source             |     0.001 |
|     polarity                       |     0.001 |
|       inst                         |     0.001 |
|   backplane                        |     6.372 |
|     aurora_s12_l1                  |     0.244 |
|       aurora_module_i              |     0.244 |
|     aurora_s12_l2                  |     0.244 |
|       aurora_module_i              |     0.244 |
|     aurora_s12_l3                  |     0.245 |
|       aurora_module_i              |     0.244 |
|     aurora_s12_l4                  |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s13_l1                  |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s13_l2                  |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s13_l3                  |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s13_l4                  |     0.244 |
|       aurora_module_i              |     0.244 |
|     aurora_s4_l1                   |     0.245 |
|       aurora_module_i              |     0.244 |
|     aurora_s4_l2                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s4_l3                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s4_l4                   |     0.244 |
|       aurora_module_i              |     0.244 |
|     aurora_s5_l1                   |     0.244 |
|       aurora_module_i              |     0.244 |
|     aurora_s5_l2                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s5_l3                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s5_l4                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s8_l1                   |     0.246 |
|       aurora_module_i              |     0.246 |
|     aurora_s8_l2                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s8_l3                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s8_l4                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s9_l1                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s9_l2                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     aurora_s9_l3                   |     0.244 |
|       aurora_module_i              |     0.244 |
|     aurora_s9_l4                   |     0.245 |
|       aurora_module_i              |     0.245 |
|     combined_ttc                   |     0.275 |
|       gt0_frame_check              |     0.003 |
|       ila_rx2_inst                 |     0.029 |
|       inst_regs                    |     0.005 |
|       sume_RO_Rx_support_i         |     0.237 |
|       vio_gt_inst                  |     0.001 |
|     readout_ctrl                   |     0.204 |
|       ila_tx0_inst                 |     0.007 |
|       rod_RO_Tx_support_i          |     0.196 |
|       vio_gt_inst                  |     0.001 |
|   dbg_hub                          |     0.006 |
|     inst                           |     0.006 |
|       BSCANID.u_xsdbm_id           |     0.006 |
|   event_builder                    |     1.090 |
|     CTTC_receiver                  |     0.035 |
|       gt0_frame_check              |     0.002 |
|       ila_rx2_inst                 |     0.030 |
|       inst_regs                    |     0.001 |
|       vio_gt_inst                  |     0.001 |
|     alt_cttc_crc                   |     0.010 |
|       crc_check_ila                |     0.009 |
|     bulk_0                         |     0.018 |
|       data_fifo                    |     0.008 |
|       event_header_crc             |     0.002 |
|       status_regs                  |     0.007 |
|     bulk_1                         |     0.018 |
|       data_fifo                    |     0.008 |
|       event_header_crc             |     0.002 |
|       status_regs                  |     0.007 |
|     bulk_2                         |     0.017 |
|       data_fifo                    |     0.008 |
|       event_header_crc             |     0.001 |
|       status_regs                  |     0.006 |
|     fifo_layer                     |     0.762 |
|       ch0                          |     0.032 |
|       ch1                          |     0.033 |
|       ch10                         |     0.031 |
|       ch11                         |     0.031 |
|       ch2                          |     0.031 |
|       ch3                          |     0.032 |
|       ch4                          |     0.031 |
|       ch5                          |     0.032 |
|       ch6                          |     0.032 |
|       ch7                          |     0.031 |
|       ch8                          |     0.030 |
|       ch9                          |     0.031 |
|       gen_jfex_chan.ch12           |     0.031 |
|       gen_jfex_chan.ch13           |     0.032 |
|       gen_jfex_chan.ch14           |     0.030 |
|       gen_jfex_chan.ch15           |     0.031 |
|       gen_jfex_chan.ch16           |     0.033 |
|       gen_jfex_chan.ch17           |     0.031 |
|       gen_jfex_chan.ch18           |     0.032 |
|       gen_jfex_chan.ch19           |     0.032 |
|       gen_jfex_chan.ch20           |     0.031 |
|       gen_jfex_chan.ch21           |     0.031 |
|       gen_jfex_chan.ch22           |     0.032 |
|       gen_jfex_chan.ch23           |     0.032 |
|       gen_reg.registers            |     0.003 |
|       gen_reg.ttc_regs             |     0.005 |
|     readout_controller             |     0.045 |
|       readout_ctrl_ila2            |     0.026 |
|       ro_crc                       |     0.008 |
|     tob_processor_0                |     0.091 |
|       event_builder_0              |     0.058 |
|       gen_reg.status_regs          |     0.031 |
|       input_mux                    |     0.002 |
|     ttc_input                      |     0.092 |
|       bulk_ttc_fifo                |     0.011 |
|       cttc_crc                     |     0.001 |
|       ila_bulk_ttc_fifo            |     0.010 |
|       ila_ttc_fifo_in              |     0.025 |
|       ila_ttc_fifo_out             |     0.012 |
|       l1id_continuity_checker      |     0.021 |
|       ttc_fifo                     |     0.010 |
|   fm_interface_1                   |     0.551 |
|     chan_0                         |     0.045 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.015 |
|       ram0                         |     0.009 |
|       u5                           |     0.010 |
|       u7                           |     0.005 |
|       vio_fm_reset                 |     0.001 |
|     chan_1                         |     0.046 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.015 |
|       ram0                         |     0.009 |
|       u5                           |     0.011 |
|       u7                           |     0.005 |
|       vio_fm_reset                 |     0.001 |
|     clk_blk                        |     0.118 |
|       inst                         |     0.118 |
|     u0                             |     0.342 |
|       g_gt_channel[0].rxresetfsm_i |     0.001 |
|       g_gt_channel[1].rxresetfsm_i |     0.001 |
|       ila_resetfsm                 |     0.006 |
|       txresetfsm_i                 |     0.002 |
|   ipbus_blk                        |     0.330 |
|     axi4_subsys                    |     0.025 |
|       axi4_subsys_i                |     0.025 |
|     ip_addr_probe                  |     0.002 |
|       inst                         |     0.002 |
|     ipbus                          |     0.301 |
|       clocks                       |     0.002 |
|       example_clocks               |     0.110 |
|       ipbus                        |     0.097 |
|       trimac_fifo_block            |     0.090 |
|   pp_out_fifo_6432                 |     0.043 |
|     ILA_packet_fifo                |     0.027 |
|       U0                           |     0.027 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.014 |
|       inst                         |     0.014 |
|   proc_clock_gen                   |     0.096 |
|     inst                           |     0.096 |
|   top_vio                          |     0.001 |
|     inst                           |     0.001 |
|   ttc_source_sel                   |     0.001 |
|     inst                           |     0.001 |
+------------------------------------+-----------+


