*** Running vivado
    with args -log top_rod_jfex_p2.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_jfex_p2.tcl -notrace


****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source top_rod_jfex_p2.tcl -notrace
create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1561.785 ; gain = 7.961 ; free physical = 30502 ; free virtual = 77889
Command: link_design -top top_rod_jfex_p2 -part xc7vx550tffg1927-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7vx550tffg1927-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.dcp' for cell 'proc_clock_gen'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.dcp' for cell 'top_vio'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.dcp' for cell 'ttc_source_sel'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo.dcp' for cell 'Bulk_0_64_32/ILA_packet_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32.dcp' for cell 'Bulk_0_64_32/data_width_conv'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0.dcp' for cell 'Bulk_0_64_32/main_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.dcp' for cell 'alternate_cttc.fm_interface_3/clk_blk'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2.dcp' for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/ram0/RAM_0'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.dcp' for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.dcp' for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/dwidth_convert.dcp' for cell 'backplane/width_conver_s12_l1'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.dcp' for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.dcp' for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1.dcp' for cell 'backplane/readout_ctrl/ila_tx0_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.dcp' for cell 'backplane/readout_ctrl/vio_gt_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.dcp' for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_CRC.dcp' for cell 'event_builder/alt_cttc_crc/crc_check_ila'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo.dcp' for cell 'event_builder/bulk_0/data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila.dcp' for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob1_fifo_out_ila'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila.dcp' for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_clk_cross_fifo.dcp' for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo_ila'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila.dcp' for cell 'event_builder/readout_controller/readout_ctrl_ila2'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_ev_builder.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.dcp' for cell 'event_builder/ttc_input/bulk_ttc_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_in'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_out'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_l1id_cont.dcp' for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm.dcp' for cell 'fm_interface_1/u0/ila_resetfsm'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.dcp' for cell 'ipbus_blk/ip_addr_probe'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/ethernet_mac_rgmii.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i'
Netlist sorting complete. Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3056.441 ; gain = 0.000 ; free physical = 28981 ; free virtual = 76368
INFO: [Netlist 29-17] Analyzing 24972 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 7 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. proc_clock_gen/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
INFO: [Chipscope 16-324] Core: Bulk_0_64_32/ILA_packet_fifo UUID: 63e7dc4f-a901-5f5e-8f15-f44cac18b816 
INFO: [Chipscope 16-324] Core: Bulk_1_64_32/ILA_packet_fifo UUID: b894b984-cded-5bd0-92d8-292d78f9765a 
INFO: [Chipscope 16-324] Core: Bulk_2_64_32/ILA_packet_fifo UUID: 020d2b63-4e4e-5e2e-aab4-4c5b2d6046e9 
INFO: [Chipscope 16-324] Core: TOB_1_64_32/ILA_packet_fifo UUID: 1891a7cf-8d09-5fbc-9972-e4a91d21cef4 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst UUID: 80888505-1efc-57ae-9e40-8681b86a5f8c 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst UUID: 7200d9a1-8e3d-5fc2-960c-ca771d9eec86 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_0/ila_fm UUID: 8097e4b8-b92b-5960-a4df-b73ab5d6cd06 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_0/vio_fm_reset UUID: f826ca6e-8cf4-5060-b996-19bb9a7821ab 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_1/ila_fm UUID: b46515df-c8ee-5943-846a-c28f4ef519d1 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_1/vio_fm_reset UUID: 2bb4310a-a09d-5a1b-b55a-16cdaed8d8de 
INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/polarity UUID: 2cb3aefb-fa06-5db0-8650-9045388eb833 
INFO: [Chipscope 16-324] Core: backplane/combined_ttc/ila_rx2_inst UUID: f60b8007-6bf8-5822-bc32-cdf6ef756575 
INFO: [Chipscope 16-324] Core: backplane/combined_ttc/vio_gt_inst UUID: a6d99938-502c-5867-8e71-028088cb558d 
INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/ila_tx0_inst UUID: 5af42e05-e58f-565e-bd4b-e3caf0b9b4a7 
INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_gt_inst UUID: 0523908b-78fb-555c-8d31-f2c3c610733b 
INFO: [Chipscope 16-324] Core: event_builder/CTTC_receiver/ila_rx2_inst UUID: 9bcc70d8-4c9f-5ec9-860b-cad2fd9e719e 
INFO: [Chipscope 16-324] Core: event_builder/CTTC_receiver/vio_gt_inst UUID: bc513526-9cc8-5253-83cd-9ec640d281c7 
INFO: [Chipscope 16-324] Core: event_builder/alt_cttc_crc/crc_check_ila UUID: d7404ee0-8704-5433-8191-e9b8d11eb7ee 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob1_fifo_out_ila UUID: 82cd3f30-d3cc-5f1d-acb9-7b4d85794c94 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila UUID: 0f381770-7687-5ee1-b02d-be51f8868775 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila UUID: b8809af5-28d1-5d4e-8a13-03533d4b2503 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo_ila UUID: 51052443-4af5-586c-ad7a-46710b4a8e51 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo_ila UUID: ee613697-5ebb-53c3-80ae-a15b7c625a30 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob1_fifo_out_ila UUID: 4a016f5c-7832-5042-a9e4-b42c3fefae95 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila UUID: 0fabbc06-76f2-533c-ad08-a5b2c20e5954 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila UUID: f0474686-58b4-5a5f-9b69-2591b61a2403 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob1_fifo_out_ila UUID: 8cd33835-f58e-5530-91d1-493966272527 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila UUID: b69c8210-f4cf-5831-8503-72bbbb8c3540 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila UUID: e432efce-dd18-5a40-a618-8ce6e622c8cf 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob1_fifo_out_ila UUID: 6f28e824-081f-5179-941a-1f784e9f4beb 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila UUID: f30ca6de-eb22-52d4-9850-cd0004597f0b 
INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila UUID: 027a0038-1ad0-58c3-94d9-f18ae6cc7b1e 
INFO: [Chipscope 16-324] Core: event_builder/readout_controller/readout_ctrl_ila2 UUID: 2118af16-197d-5a88-95e6-28dbf9962d95 
INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/State_machine_ILA UUID: b8ade747-7d7c-5fc7-9f63-b2cb50b3a6e1 
INFO: [Chipscope 16-324] Core: event_builder/tob_processor_1/event_builder_0/State_machine_ILA UUID: ea097a34-e9b0-5b83-9743-c17a86f6e04c 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_in UUID: 0d145367-edc8-5440-8a43-c5b7fdc60185 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_out UUID: dea619c4-8196-5fc3-a887-501d70a94797 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check UUID: 0b5e705b-49ad-5d15-9efb-ec02e926d290 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/ila_fm UUID: 39f68e95-8276-57e5-b2ba-d040b8bf414c 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/vio_fm_reset UUID: b602d903-de6d-5e57-92e3-814b1496a830 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_fm UUID: 312b9249-01c3-5825-bad2-86e782be33e1 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/vio_fm_reset UUID: eec5d607-63dd-55c1-a9db-2118e9215856 
INFO: [Chipscope 16-324] Core: fm_interface_1/u0/ila_resetfsm UUID: 82d99aa3-751c-5dfe-85d1-97a24142969c 
INFO: [Chipscope 16-324] Core: fm_interface_tob1/chan_0/ila_fm UUID: b3b983dd-73ce-59f4-85c8-e6692d898ae3 
INFO: [Chipscope 16-324] Core: fm_interface_tob1/chan_0/vio_fm_reset UUID: b8bce6d1-6dd7-59e3-b635-742176384f08 
INFO: [Chipscope 16-324] Core: fm_interface_tob1/chan_1/ila_fm UUID: 3c553930-a5e4-5a9e-bab5-538e2a37419a 
INFO: [Chipscope 16-324] Core: fm_interface_tob1/chan_1/vio_fm_reset UUID: cf393243-01b3-5fc3-9f2d-c0593fc7c9d6 
INFO: [Chipscope 16-324] Core: fm_interface_tob1/u0/ila_resetfsm UUID: e8dbdfe3-afa6-50b3-b046-3f4786b86ad1 
INFO: [Chipscope 16-324] Core: ipbus_blk/ip_addr_probe UUID: d3bad9ce-591e-57bb-984d-9f6468850a46 
INFO: [Chipscope 16-324] Core: pp_out_fifo_6432/ILA_packet_fifo UUID: b136e600-ef26-57f9-8e20-f80fc6236875 
INFO: [Chipscope 16-324] Core: top_vio UUID: 7b2ee998-e565-566c-a490-bae90ac485a9 
INFO: [Chipscope 16-324] Core: ttc_source_sel UUID: c1a2c02a-9f6d-5067-b34f-a57ba8dd1b77 
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_tob1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_tob1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo_1/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo_1/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob1_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob1_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_tob1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_tob1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_tob1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_tob1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_tob1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_tob1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_tob1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_tob1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_tob1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_tob1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_tob1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_tob1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_tob1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_tob1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_tob1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_tob1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_tob1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_tob1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_1/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_1/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_1/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_1/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/rod_jfex_p2.gen/sources_1/ip/ila_clk_cross_fifo/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:54]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:54]
get_clocks: Time (s): cpu = 00:00:39 ; elapsed = 00:00:22 . Memory (MB): peak = 4873.914 ; gain = 1160.758 ; free physical = 27330 ; free virtual = 74718
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'TOB_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'TOB_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'TOB_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'TOB_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0'
WARNING: [Vivado 12-2489] -period contains time 3.118500 which will be rounded to 3.119 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc:72]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'ttc_source_sel'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'ttc_source_sel'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/polarity'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/polarity'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_tob1/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_tob1/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_tob1/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_tob1/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_tob1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_tob1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_tob1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_tob1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/rod_top.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/rod_top.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc]
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65]
get_pins: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 6082.094 ; gain = 1144.148 ; free physical = 26208 ; free virtual = 73595
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc]
WARNING: [Vivado 12-508] No pins matched 'event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:20]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:20]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched 'event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:22]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:22]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched 'event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:32]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:32]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched 'event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[10].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:110]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[10].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc:110]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/TTC_input_TE.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc]
WARNING: [Vivado 12-508] No pins matched 'event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[10].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:24]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[10].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:24]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:41]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:41]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:50]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:50]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[11].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:52]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[11].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:52]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[11].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:70]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[11].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:70]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:71]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {*/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc:71]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/full_mode_TE.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/data_input_TE.xdc]
WARNING: [Vivado 12-508] No pins matched 'event_builder/fifo_layer/*ch*/*ila/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[6].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/data_input_TE.xdc:202]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/fifo_layer/*ch*/*ila/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[6].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/data_input_TE.xdc:202]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/data_input_TE.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/aurora_rx_2_pp_clock.xdc]
WARNING: [Vivado 12-508] No pins matched 'event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[1].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/aurora_rx_2_pp_clock.xdc:24]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[1].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/aurora_rx_2_pp_clock.xdc:24]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/aurora_rx_2_pp_clock.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc:34]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/experiment.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/experiment.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/implementation_only.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/implementation_only.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/FullMode_p2.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/FullMode_p2.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/alt_cttc_TE.xdc]
WARNING: [Vivado 12-508] No pins matched 'event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/alt_cttc_TE.xdc:5]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[*]/D}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/alt_cttc_TE.xdc:5]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched 'event_builder/CTTC_receiver/inst_regs/reg_0_reg[*]_replica_2/C'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/alt_cttc_TE.xdc:34]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -include_replicated_objects {event_builder/CTTC_receiver/inst_regs/reg_0_reg[*]_replica_2/C}]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/alt_cttc_TE.xdc:34]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex_p2/xdc/alt_cttc_TE.xdc]
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports -scoped_to_current_instance ext_spi_clk]'. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_clocks.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo_1/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo_1/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:73]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:74]
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_tob1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_tob1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_tob1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_tob1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_tob1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_tob1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_tob1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_tob1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_tob1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_tob1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0'
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_tob1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_tob1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_tob1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_tob1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 
 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Project 1-1714] 764 XPM XDC files have been applied to the design.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-1687] 6 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6382.094 ; gain = 0.000 ; free physical = 25927 ; free virtual = 73316
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 12125 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 4764 instances
  IOBUF => IOBUF (IBUF, OBUFT): 23 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 58 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
  RAM64M => RAM64M (RAMD64E(x4)): 7172 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 104 instances

112 Infos, 146 Warnings, 14 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:05:19 ; elapsed = 00:04:34 . Memory (MB): peak = 6382.129 ; gain = 4645.938 ; free physical = 25927 ; free virtual = 73316
source /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it...
INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd...
INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found.
INFO: [Hog:Msg-0] All done
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
Parsing TCL File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/FullMode_tx/FullMode_tx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl]
Parsing TCL File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl]
Parsing TCL File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl]
Parsing TCL File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6390.098 ; gain = 7.969 ; free physical = 25925 ; free virtual = 73314

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup

Phase 1.1.1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
Done building netlist checker database: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.31 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25919 ; free virtual = 73313
get_clocks: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25910 ; free virtual = 73305
Netlist sorting complete. Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25910 ; free virtual = 73305
Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 235fbc701

Time (s): cpu = 00:02:04 ; elapsed = 00:02:03 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25910 ; free virtual = 73305
Phase 1.1 Core Generation And Design Setup | Checksum: 235fbc701

Time (s): cpu = 00:02:04 ; elapsed = 00:02:03 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25910 ; free virtual = 73305

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 235fbc701

Time (s): cpu = 00:02:04 ; elapsed = 00:02:03 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25910 ; free virtual = 73305
Phase 1 Initialization | Checksum: 235fbc701

Time (s): cpu = 00:02:04 ; elapsed = 00:02:03 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25910 ; free virtual = 73305

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 235fbc701

Time (s): cpu = 00:02:19 ; elapsed = 00:02:18 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25910 ; free virtual = 73305

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 235fbc701

Time (s): cpu = 00:02:20 ; elapsed = 00:02:19 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25882 ; free virtual = 73276
Phase 2 Timer Update And Timing Data Collection | Checksum: 235fbc701

Time (s): cpu = 00:02:20 ; elapsed = 00:02:19 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25882 ; free virtual = 73276

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 88 inverters resulting in an inversion of 1830 pins
INFO: [Opt 31-138] Pushed 152 inverter(s) to 354 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1d2bb1fd0

Time (s): cpu = 00:02:30 ; elapsed = 00:02:29 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25881 ; free virtual = 73276
Retarget | Checksum: 1d2bb1fd0
INFO: [Opt 31-389] Phase Retarget created 985 cells and removed 3494 cells
INFO: [Opt 31-1021] In phase Retarget, 4547 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 15c733fbd

Time (s): cpu = 00:02:34 ; elapsed = 00:02:33 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25881 ; free virtual = 73276
Constant propagation | Checksum: 15c733fbd
INFO: [Opt 31-389] Phase Constant propagation created 332 cells and removed 2052 cells
INFO: [Opt 31-1021] In phase Constant propagation, 3512 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 Sweep
INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD10638) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD10609) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
INFO: [Opt 31-120] Instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
Phase 5 Sweep | Checksum: 200423be6

Time (s): cpu = 00:02:56 ; elapsed = 00:02:56 . Memory (MB): peak = 6390.098 ; gain = 0.000 ; free physical = 25876 ; free virtual = 73271
Sweep | Checksum: 200423be6
INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 11867 cells
INFO: [Opt 31-1021] In phase Sweep, 30723 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 6 BUFG optimization
INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells
Phase 6 BUFG optimization | Checksum: 17ba3b817

Time (s): cpu = 00:03:04 ; elapsed = 00:03:00 . Memory (MB): peak = 6414.109 ; gain = 24.012 ; free physical = 25876 ; free virtual = 73271
BUFG optimization | Checksum: 17ba3b817
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells.

Phase 7 Shift Register Optimization
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from TOB_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/readout_ctrl/ila_tx0_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from backplane/readout_ctrl/ila_tx0_inst/U0/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
INFO: [Common 17-14] Message 'Opt 31-1131' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 17ba3b817

Time (s): cpu = 00:03:05 ; elapsed = 00:03:01 . Memory (MB): peak = 6414.109 ; gain = 24.012 ; free physical = 25876 ; free virtual = 73271
Shift Register Optimization | Checksum: 17ba3b817
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7vx550t is unsupported

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 21f383485

Time (s): cpu = 00:03:07 ; elapsed = 00:03:03 . Memory (MB): peak = 6414.109 ; gain = 24.012 ; free physical = 25876 ; free virtual = 73271
Post Processing Netlist | Checksum: 21f383485
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 3910 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 113d6fdd7

Time (s): cpu = 00:03:13 ; elapsed = 00:03:08 . Memory (MB): peak = 6414.109 ; gain = 24.012 ; free physical = 25876 ; free virtual = 73271

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.72 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25876 ; free virtual = 73271
Phase 9.2 Verifying Netlist Connectivity | Checksum: 113d6fdd7

Time (s): cpu = 00:03:14 ; elapsed = 00:03:09 . Memory (MB): peak = 6414.109 ; gain = 24.012 ; free physical = 25876 ; free virtual = 73271
Phase 9 Finalization | Checksum: 113d6fdd7

Time (s): cpu = 00:03:14 ; elapsed = 00:03:09 . Memory (MB): peak = 6414.109 ; gain = 24.012 ; free physical = 25876 ; free virtual = 73271
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |             985  |            3494  |                                           4547  |
|  Constant propagation         |             332  |            2052  |                                           3512  |
|  Sweep                        |              11  |           11867  |                                          30723  |
|  BUFG optimization            |               0  |               1  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                           3910  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 113d6fdd7

Time (s): cpu = 00:03:14 ; elapsed = 00:03:09 . Memory (MB): peak = 6414.109 ; gain = 24.012 ; free physical = 25876 ; free virtual = 73271
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.3 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25876 ; free virtual = 73271
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] from IP /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/axi4_subsys_jtag_axi_0_0.xci
Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc:69]
all_fanout: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25876 ; free virtual = 73271
Finished Parsing XDC File [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25876 ; free virtual = 73271
Ending Netlist Obfuscation Task | Checksum: 113d6fdd7

Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25876 ; free virtual = 73271
INFO: [Common 17-83] Releasing license: Implementation
153 Infos, 246 Warnings, 14 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:04:01 ; elapsed = 00:03:56 . Memory (MB): peak = 6414.109 ; gain = 31.980 ; free physical = 25876 ; free virtual = 73271
INFO: [runtcl-4] Executing : report_drc -file top_rod_jfex_p2_drc_opted.rpt -pb top_rod_jfex_p2_drc_opted.pb -rpx top_rod_jfex_p2_drc_opted.rpx
Command: report_drc -file top_rod_jfex_p2_drc_opted.rpt -pb top_rod_jfex_p2_drc_opted.pb -rpx top_rod_jfex_p2_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex_p2/rod_jfex_p2.runs/impl_1/top_rod_jfex_p2_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25871 ; free virtual = 73266
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.49 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25616 ; free virtual = 73269
Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25615 ; free virtual = 73269
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25615 ; free virtual = 73269
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.58 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25614 ; free virtual = 73269
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25614 ; free virtual = 73269
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25612 ; free virtual = 73269
Write Physdb Complete: Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.67 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25612 ; free virtual = 73269
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex_p2/rod_jfex_p2.runs/impl_1/top_rod_jfex_p2_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:54 ; elapsed = 00:00:57 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25756 ; free virtual = 73262
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 22 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25749 ; free virtual = 73255
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c58fd81d

Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25749 ; free virtual = 73255
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25749 ; free virtual = 73255

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e46d804e

Time (s): cpu = 00:02:12 ; elapsed = 00:02:13 . Memory (MB): peak = 6414.109 ; gain = 0.000 ; free physical = 25743 ; free virtual = 73249

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 13428e37d

Time (s): cpu = 00:04:13 ; elapsed = 00:04:14 . Memory (MB): peak = 7255.906 ; gain = 841.797 ; free physical = 24843 ; free virtual = 72349

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 13428e37d

Time (s): cpu = 00:04:15 ; elapsed = 00:04:16 . Memory (MB): peak = 7255.906 ; gain = 841.797 ; free physical = 24843 ; free virtual = 72349
Phase 1 Placer Initialization | Checksum: 13428e37d

Time (s): cpu = 00:04:16 ; elapsed = 00:04:17 . Memory (MB): peak = 7255.906 ; gain = 841.797 ; free physical = 24843 ; free virtual = 72349

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 17a746cd0

Time (s): cpu = 00:04:53 ; elapsed = 00:04:54 . Memory (MB): peak = 7255.906 ; gain = 841.797 ; free physical = 24835 ; free virtual = 72341

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 12184a448

Time (s): cpu = 00:05:26 ; elapsed = 00:05:27 . Memory (MB): peak = 7255.906 ; gain = 841.797 ; free physical = 24827 ; free virtual = 72333

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1ab0b52f1

Time (s): cpu = 00:05:27 ; elapsed = 00:05:29 . Memory (MB): peak = 7255.906 ; gain = 841.797 ; free physical = 24827 ; free virtual = 72333

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 23b3145ec

Time (s): cpu = 00:10:56 ; elapsed = 00:11:00 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24673 ; free virtual = 72180

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 3 LUTNM shape to break, 13774 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 3, two critical 0, total 3, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 6004 nets or LUTs. Breaked 3 LUTs, combined 6001 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7408.266 ; gain = 0.000 ; free physical = 24673 ; free virtual = 72180

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            3  |           6001  |                  6004  |           0  |           1  |  00:00:09  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:03  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            3  |           6001  |                  6004  |           0  |           9  |  00:00:14  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1f013686f

Time (s): cpu = 00:11:52 ; elapsed = 00:11:56 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24673 ; free virtual = 72180
Phase 2.4 Global Placement Core | Checksum: 17b5804f9

Time (s): cpu = 00:12:59 ; elapsed = 00:13:03 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24673 ; free virtual = 72180
Phase 2 Global Placement | Checksum: 17b5804f9

Time (s): cpu = 00:12:59 ; elapsed = 00:13:04 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24673 ; free virtual = 72180

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 12c5e375d

Time (s): cpu = 00:13:37 ; elapsed = 00:13:41 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24673 ; free virtual = 72179

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 24e3abbef

Time (s): cpu = 00:14:58 ; elapsed = 00:15:02 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24669 ; free virtual = 72175

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 18cf704e1

Time (s): cpu = 00:15:03 ; elapsed = 00:15:08 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24669 ; free virtual = 72175

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1954e0286

Time (s): cpu = 00:15:09 ; elapsed = 00:15:14 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24676 ; free virtual = 72182

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 1e895c6dd

Time (s): cpu = 00:16:44 ; elapsed = 00:16:50 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24675 ; free virtual = 72182

Phase 3.6 Small Shape Detail Placement

Phase 3.6.1 Place Remaining
Phase 3.6.1 Place Remaining | Checksum: 20fd394f6

Time (s): cpu = 00:19:06 ; elapsed = 00:19:12 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24674 ; free virtual = 72181
Phase 3.6 Small Shape Detail Placement | Checksum: 20fd394f6

Time (s): cpu = 00:19:10 ; elapsed = 00:19:16 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24674 ; free virtual = 72181

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 242096c1b

Time (s): cpu = 00:19:24 ; elapsed = 00:19:31 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24674 ; free virtual = 72180

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1802ea889

Time (s): cpu = 00:19:35 ; elapsed = 00:19:41 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24674 ; free virtual = 72180
Phase 3 Detail Placement | Checksum: 1802ea889

Time (s): cpu = 00:19:37 ; elapsed = 00:19:44 . Memory (MB): peak = 7408.266 ; gain = 994.156 ; free physical = 24674 ; free virtual = 72180

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: eca58779

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.444 | TNS=-582.150 |
Phase 1 Physical Synthesis Initialization | Checksum: 10d0fb430

Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24650 ; free virtual = 72156
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 10d0fb430

Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24650 ; free virtual = 72156
Phase 4.1.1.1 BUFG Insertion | Checksum: eca58779

Time (s): cpu = 00:22:55 ; elapsed = 00:23:03 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24650 ; free virtual = 72156

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.342. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 13b56cd9d

Time (s): cpu = 00:26:07 ; elapsed = 00:26:17 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154

Time (s): cpu = 00:26:07 ; elapsed = 00:26:17 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154
Phase 4.1 Post Commit Optimization | Checksum: 13b56cd9d

Time (s): cpu = 00:26:09 ; elapsed = 00:26:19 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 13b56cd9d

Time (s): cpu = 00:26:14 ; elapsed = 00:26:24 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                4x4|                4x4|
|___________|___________________|___________________|
|      South|                4x4|                4x4|
|___________|___________________|___________________|
|       East|                4x4|                2x2|
|___________|___________________|___________________|
|       West|                2x2|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 13b56cd9d

Time (s): cpu = 00:26:17 ; elapsed = 00:26:27 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154
Phase 4.3 Placer Reporting | Checksum: 13b56cd9d

Time (s): cpu = 00:26:19 ; elapsed = 00:26:29 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24647 ; free virtual = 72154

Time (s): cpu = 00:26:19 ; elapsed = 00:26:29 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 194eda741

Time (s): cpu = 00:26:22 ; elapsed = 00:26:32 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154
Ending Placer Task | Checksum: 1253a4abc

Time (s): cpu = 00:26:24 ; elapsed = 00:26:34 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154
194 Infos, 246 Warnings, 14 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:26:50 ; elapsed = 00:27:00 . Memory (MB): peak = 7440.266 ; gain = 1026.156 ; free physical = 24647 ; free virtual = 72154
INFO: [runtcl-4] Executing : report_io -file top_rod_jfex_p2_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.48 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24647 ; free virtual = 72154
INFO: [runtcl-4] Executing : report_utilization -file top_rod_jfex_p2_utilization_placed.rpt -pb top_rod_jfex_p2_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_rod_jfex_p2_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24642 ; free virtual = 72154
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.8 ; elapsed = 00:00:00.83 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24366 ; free virtual = 72156
Wrote PlaceDB: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24063 ; free virtual = 72157
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24063 ; free virtual = 72157
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.57 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24062 ; free virtual = 72156
Wrote Netlist Cache: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.3 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24044 ; free virtual = 72156
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24042 ; free virtual = 72156
Write Physdb Complete: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24042 ; free virtual = 72156
report_design_analysis: Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24035 ; free virtual = 72150
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex_p2/rod_jfex_p2.runs/impl_1/top_rod_jfex_p2_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:58 ; elapsed = 00:02:02 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24490 ; free virtual = 72153
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore

Starting Initial Update Timing Task

Time (s): cpu = 00:02:06 ; elapsed = 00:02:07 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24488 ; free virtual = 72151
INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 128.55s |  WALL: 129.20s
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24488 ; free virtual = 72151

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-134.375 |
Phase 1 Physical Synthesis Initialization | Checksum: ee35211c

Time (s): cpu = 00:01:16 ; elapsed = 00:01:16 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24505 ; free virtual = 72168

Phase 2 SLR Crossing Optimization
Phase 2 SLR Crossing Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24503 ; free virtual = 72166
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-134.375 |

Phase 3 Fanout Optimization
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 3 Fanout Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24503 ; free virtual = 72166

Phase 4 Single Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[0]
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24503 ; free virtual = 72166
Phase 4 Single Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:26 ; elapsed = 00:01:26 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24503 ; free virtual = 72166

Phase 5 Multi Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/Q
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1/O
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24503 ; free virtual = 72166
Phase 5 Multi Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:28 ; elapsed = 00:01:28 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24503 ; free virtual = 72166

Phase 6 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-241] No nets found for rewiring () optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24508 ; free virtual = 72171
Phase 6 Rewire | Checksum: ee35211c

Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24508 ; free virtual = 72171

Phase 7 Critical Cell Optimization
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 7 Critical Cell Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24508 ; free virtual = 72171

Phase 8 Fanout Optimization
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 8 Fanout Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177

Phase 9 Single Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[0]
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177
Phase 9 Single Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:34 ; elapsed = 00:01:34 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177

Phase 10 Multi Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/Q
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1/O
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177
Phase 10 Multi Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:36 ; elapsed = 00:01:36 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177

Phase 11 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-241] No nets found for rewiring () optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177
Phase 11 Rewire | Checksum: ee35211c

Time (s): cpu = 00:01:36 ; elapsed = 00:01:37 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177

Phase 12 Critical Cell Optimization
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 12 Critical Cell Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:37 ; elapsed = 00:01:37 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177

Phase 13 SLR Crossing Optimization
Phase 13 SLR Crossing Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:37 ; elapsed = 00:01:37 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72177

Phase 14 Fanout Optimization
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 14 Fanout Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:40 ; elapsed = 00:01:41 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 15 Single Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[0]
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176
Phase 15 Single Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:42 ; elapsed = 00:01:42 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 16 Multi Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/Q
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1/O
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176
Phase 16 Multi Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:43 ; elapsed = 00:01:44 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 17 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-241] No nets found for rewiring () optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176
Phase 17 Rewire | Checksum: ee35211c

Time (s): cpu = 00:01:44 ; elapsed = 00:01:45 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 18 Critical Cell Optimization
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 18 Critical Cell Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:45 ; elapsed = 00:01:45 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 19 DSP Register Optimization
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 19 DSP Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:45 ; elapsed = 00:01:45 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 20 BRAM Register Optimization
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 20 BRAM Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:45 ; elapsed = 00:01:46 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 21 URAM Register Optimization
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 21 URAM Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:45 ; elapsed = 00:01:46 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 22 Shift Register Optimization
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 22 Shift Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:45 ; elapsed = 00:01:46 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 23 DSP Register Optimization
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 23 DSP Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:46 ; elapsed = 00:01:46 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 24 BRAM Register Optimization
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 24 BRAM Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:46 ; elapsed = 00:01:46 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 25 URAM Register Optimization
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 25 URAM Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:46 ; elapsed = 00:01:47 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 26 Shift Register Optimization
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 26 Shift Register Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:46 ; elapsed = 00:01:47 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 27 Critical Pin Optimization
INFO: [Physopt 32-606] Identified 1 candidate net for critical-pin optimization.
INFO: [Physopt 32-608] Optimized 0 net.  Swapped 0 pin.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 27 Critical Pin Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:47 ; elapsed = 00:01:47 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24514 ; free virtual = 72176

Phase 28 Very High Fanout Optimization
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 461 to 94 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 94.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob1_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 462 to 95 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 95.
INFO: [Common 17-14] Message 'Physopt 32-1132' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization.
INFO: [Physopt 32-572] Net event_builder/bkpln_rst_pulse_stretcher/reset was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.19 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24519 ; free virtual = 72182
Phase 28 Very High Fanout Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:56 ; elapsed = 00:01:56 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24519 ; free virtual = 72182

Phase 29 Single Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[0]
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24519 ; free virtual = 72182
Phase 29 Single Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:01:58 ; elapsed = 00:01:58 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24519 ; free virtual = 72182

Phase 30 Multi Cell Placement Optimization
INFO: [Physopt 32-660] Identified 3 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i.  Did not re-place instance event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/Q
INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4].  Did not re-place instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M_i_1/O
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24519 ; free virtual = 72182
Phase 30 Multi Cell Placement Optimization | Checksum: ee35211c

Time (s): cpu = 00:02:00 ; elapsed = 00:02:00 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24519 ; free virtual = 72182

Phase 31 SLR Crossing Optimization
Phase 31 SLR Crossing Optimization | Checksum: ee35211c

Time (s): cpu = 00:02:00 ; elapsed = 00:02:00 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24519 ; free virtual = 72182

Phase 32 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-134.375 |
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net fm_interface_tob1/chan_1/ila_fm/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[9].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0].  Re-placed instance fm_interface_tob1/chan_1/ila_fm/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[9].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[0]
INFO: [Physopt 32-735] Processed net fm_interface_tob1/chan_1/ila_fm/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[9].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-134.254 |
INFO: [Physopt 32-663] Processed net fm_interface_tob1/chan_1/ila_fm/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0].  Re-placed instance fm_interface_tob1/chan_1/ila_fm/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[0]
INFO: [Physopt 32-735] Processed net fm_interface_tob1/chan_1/ila_fm/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-134.242 |
INFO: [Physopt 32-702] Processed net fm_interface_tob1/chan_1/ila_fm/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net fm_interface_tob1/u0/I. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net fm_interface_tob1/chan_1/SOP_compare.  Re-placed instance fm_interface_tob1/chan_1/SOP_compare_inferred_i_1
INFO: [Physopt 32-735] Processed net fm_interface_tob1/chan_1/SOP_compare. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-134.002 |
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_192_255_21_23/DOA. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[25].  Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[25]
INFO: [Physopt 32-735] Processed net backplane/combined_ttc/inst_regs/reg_3[25]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-133.642 |
INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[1].  Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[1]
INFO: [Physopt 32-735] Processed net event_builder/ttc_input/cttc_crc/crc_out[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-133.342 |
INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[5].  Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[5]
INFO: [Physopt 32-735] Processed net event_builder/ttc_input/cttc_crc/crc_out[5]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.803 |
INFO: [Physopt 32-663] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[19].  Re-placed instance event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg[19]
INFO: [Physopt 32-735] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[19]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.710 |
INFO: [Physopt 32-663] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[20].  Re-placed instance event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg[20]
INFO: [Physopt 32-735] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[20]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.646 |
INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[6].  Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[6]
INFO: [Physopt 32-735] Processed net event_builder/ttc_input/cttc_crc/crc_out[6]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.610 |
INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[8].  Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[8]
INFO: [Physopt 32-735] Processed net event_builder/ttc_input/cttc_crc/crc_out[8]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.418 |
INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[2].  Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[2]
INFO: [Physopt 32-735] Processed net event_builder/ttc_input/cttc_crc/crc_out[2]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.358 |
INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[26].  Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[26]
INFO: [Physopt 32-735] Processed net backplane/combined_ttc/inst_regs/reg_3[26]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.238 |
INFO: [Physopt 32-663] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[11].  Re-placed instance event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg[11]
INFO: [Physopt 32-735] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[11]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.206 |
INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[0].  Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[0]
INFO: [Physopt 32-735] Processed net event_builder/ttc_input/cttc_crc/crc_out[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.051 |
INFO: [Physopt 32-663] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[10].  Re-placed instance event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg[10]
INFO: [Physopt 32-735] Processed net event_builder/CTTC_receiver/gt0_frame_check/rx_data_r_reg_n_0_[10]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-132.034 |
INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[23].  Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[23]
INFO: [Physopt 32-735] Processed net backplane/combined_ttc/inst_regs/reg_3[23]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-131.997 |
INFO: [Physopt 32-702] Processed net fm_interface_tob1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[25]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net fm_interface_tob1/chan_0/u5/eop_space_trig/fifo_re.  Re-placed instance fm_interface_tob1/chan_0/u5/eop_space_trig/fifo_re_INST_0
INFO: [Physopt 32-735] Processed net fm_interface_tob1/chan_0/u5/eop_space_trig/fifo_re. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-131.995 |
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-131.995 |
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183
Phase 32 Critical Path Optimization | Checksum: ee35211c

Time (s): cpu = 00:02:10 ; elapsed = 00:02:10 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183

Phase 33 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-131.995 |
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[3].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/all_dly1[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ttc_fifo_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/u_trig/U_TM/probe_data[4]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.342 | TNS=-131.995 |
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183
Phase 33 Critical Path Optimization | Checksum: ee35211c

Time (s): cpu = 00:02:11 ; elapsed = 00:02:12 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183

Phase 34 BRAM Enable Optimization
Phase 34 BRAM Enable Optimization | Checksum: ee35211c

Time (s): cpu = 00:02:11 ; elapsed = 00:02:12 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183
INFO: [Physopt 32-960] Skip hold-fix as initial WHS does not violate hold threshold 250 ps
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183
INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-3.342 | TNS=-131.995 |

Summary of Physical Synthesis Optimizations
============================================


----------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization            |  WNS Gain (ns)  |  TNS Gain (ns)  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Fanout                  |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           3  |  00:00:12  |
|  Single Cell Placement   |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           4  |  00:00:07  |
|  Multi Cell Placement    |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           4  |  00:00:06  |
|  Rewire                  |          0.000  |          0.000  |            0  |              0  |                     0  |           3  |           3  |  00:00:02  |
|  Critical Cell           |          0.000  |          0.000  |            0  |              0  |                     0  |           3  |           3  |  00:00:02  |
|  SLR Crossing            |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           3  |  00:00:00  |
|  DSP Register            |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  BRAM Register           |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  URAM Register           |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  Shift Register          |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
|  Critical Pin            |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  Very High Fanout        |          0.000  |          0.000  |            0  |              0  |                     0  |           3  |           1  |  00:00:09  |
|  BRAM Enable             |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Path           |          0.000  |          2.379  |            0  |              0  |                    17  |           0  |           2  |  00:00:12  |
|  Total                   |          0.000  |          2.379  |            0  |              0  |                    17  |           9  |          33  |  00:00:51  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------


Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183
Ending Physical Synthesis Task | Checksum: 194ffaefc

Time (s): cpu = 00:02:18 ; elapsed = 00:02:19 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183
INFO: [Common 17-83] Releasing license: Implementation
483 Infos, 246 Warnings, 14 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:04:27 ; elapsed = 00:04:28 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24520 ; free virtual = 72183
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.66 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24259 ; free virtual = 72192
Wrote PlaceDB: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 23952 ; free virtual = 72187
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 23952 ; free virtual = 72187
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.58 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 23951 ; free virtual = 72187
Wrote Netlist Cache: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.29 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 23933 ; free virtual = 72188
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 23932 ; free virtual = 72188
Write Physdb Complete: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 23931 ; free virtual = 72187
report_design_analysis: Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 23931 ; free virtual = 72187
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex_p2/rod_jfex_p2.runs/impl_1/top_rod_jfex_p2_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:43 ; elapsed = 00:01:46 . Memory (MB): peak = 7440.266 ; gain = 0.000 ; free physical = 24368 ; free virtual = 72180
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.

Phase 1 Build RT Design
Checksum: PlaceDB: 500307ab ConstDB: 0 ShapeSum: f6b58197 RouteDB: 0
Post Restoration Checksum: NetGraph: 8a22a7c2 | NumContArr: 39144bbc | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 24888e8b8

Time (s): cpu = 00:03:19 ; elapsed = 00:03:20 . Memory (MB): peak = 7464.266 ; gain = 0.000 ; free physical = 24345 ; free virtual = 72156

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 24888e8b8

Time (s): cpu = 00:03:23 ; elapsed = 00:03:24 . Memory (MB): peak = 7464.266 ; gain = 0.000 ; free physical = 24343 ; free virtual = 72154

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 24888e8b8

Time (s): cpu = 00:03:25 ; elapsed = 00:03:26 . Memory (MB): peak = 7464.266 ; gain = 0.000 ; free physical = 24343 ; free virtual = 72154
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 246eaf9ac

Time (s): cpu = 00:07:22 ; elapsed = 00:07:24 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23709 ; free virtual = 71528
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.532 | TNS=-34.851| WHS=-2.045 | THS=-29351.117|


Phase 2.4 Update Timing for Bus Skew

Phase 2.4.1 Update Timing
Phase 2.4.1 Update Timing | Checksum: 1c093525b

Time (s): cpu = 00:09:02 ; elapsed = 00:09:05 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23705 ; free virtual = 71525
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.532 | TNS=-22.338| WHS=N/A    | THS=N/A    |

Phase 2.4 Update Timing for Bus Skew | Checksum: 1d0a983bf

Time (s): cpu = 00:09:05 ; elapsed = 00:09:08 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23705 ; free virtual = 71525

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.328883 %
  Global Horizontal Routing Utilization  = 0.330558 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 371050
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 371050
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 6

Phase 2 Router Initialization | Checksum: 27d4e36c7

Time (s): cpu = 00:09:12 ; elapsed = 00:09:15 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23697 ; free virtual = 71516

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 27d4e36c7

Time (s): cpu = 00:09:12 ; elapsed = 00:09:15 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23697 ; free virtual = 71516

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 285c6cae8

Time (s): cpu = 00:11:08 ; elapsed = 00:11:11 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23701 ; free virtual = 71521
Phase 3 Initial Routing | Checksum: 285c6cae8

Time (s): cpu = 00:11:09 ; elapsed = 00:11:12 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23698 ; free virtual = 71517
INFO: [Route 35-580] Design has 122 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+=================================+=================================+=====================================================================================================================================================================+
| Launch Setup Clock              | Launch Hold Clock               | Pin                                                                                                                                                                 |
+=================================+=================================+=====================================================================================================================================================================+
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[5]/D  |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[11]/D |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[7]/D  |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[3]/D  |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[7]/D      |
+---------------------------------+---------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 25892
 Number of Nodes with overlaps = 3096
 Number of Nodes with overlaps = 370
 Number of Nodes with overlaps = 30
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 14
 Number of Nodes with overlaps = 11
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-3009.307| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 242321894

Time (s): cpu = 00:23:20 ; elapsed = 00:23:27 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23691 ; free virtual = 71511

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2921.295| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 2abe58ac9

Time (s): cpu = 00:23:35 ; elapsed = 00:23:42 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23692 ; free virtual = 71512
Phase 4 Rip-up And Reroute | Checksum: 2abe58ac9

Time (s): cpu = 00:23:36 ; elapsed = 00:23:43 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23692 ; free virtual = 71512

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 2dcc93741

Time (s): cpu = 00:24:13 ; elapsed = 00:24:20 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23699 ; free virtual = 71518
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2750.005| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 3467c7d1b

Time (s): cpu = 00:24:21 ; elapsed = 00:24:28 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23698 ; free virtual = 71517

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 3467c7d1b

Time (s): cpu = 00:24:22 ; elapsed = 00:24:29 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23698 ; free virtual = 71517
Phase 5 Delay and Skew Optimization | Checksum: 3467c7d1b

Time (s): cpu = 00:24:23 ; elapsed = 00:24:30 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23698 ; free virtual = 71517

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 34ca3f9f2

Time (s): cpu = 00:25:06 ; elapsed = 00:25:13 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23703 ; free virtual = 71523
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2104.723| WHS=-0.545 | THS=-1010.353|


Phase 6.1.2 Lut RouteThru Assignment for hold
Phase 6.1.2 Lut RouteThru Assignment for hold | Checksum: 1e06f57f7

Time (s): cpu = 00:25:31 ; elapsed = 00:25:38 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23703 ; free virtual = 71523
Phase 6.1 Hold Fix Iter | Checksum: 1e06f57f7

Time (s): cpu = 00:25:32 ; elapsed = 00:25:39 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23703 ; free virtual = 71523

Phase 6.2 Additional Hold Fix
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2131.673| WHS=-0.545 | THS=-984.963|

Phase 6.2 Additional Hold Fix | Checksum: 21d9eb284

Time (s): cpu = 00:26:16 ; elapsed = 00:26:24 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23707 ; free virtual = 71527

Phase 6.3 Non Free Resource Hold Fix Iter
Phase 6.3 Non Free Resource Hold Fix Iter | Checksum: 17b5902f9

Time (s): cpu = 00:26:17 ; elapsed = 00:26:25 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23707 ; free virtual = 71527
WARNING: [Route 35-468] The router encountered 158 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are:
	Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[11].U_M_i_1/I0
	event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[10].U_M_i_24/I0
	event_builder/CTTC_receiver_i_10/I1
	event_builder/CTTC_receiver_i_11/I1
	event_builder/CTTC_receiver_i_2/I1
	event_builder/CTTC_receiver_i_7/I1
	event_builder/CTTC_receiver_i_8/I1
	event_builder/CTTC_receiver_i_9/I1
	event_builder/CTTC_receiver_i_1/I2
	event_builder/CTTC_receiver_i_12/I2
	.. and 148 more pins.

Phase 6 Post Hold Fix | Checksum: 17b5902f9

Time (s): cpu = 00:26:18 ; elapsed = 00:26:26 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23707 ; free virtual = 71527

Phase 7 Timing Verification

Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: 211f2571f

Time (s): cpu = 00:27:13 ; elapsed = 00:27:21 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23709 ; free virtual = 71529
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2131.634| WHS=N/A    | THS=N/A    |

Phase 7 Timing Verification | Checksum: 211f2571f

Time (s): cpu = 00:27:14 ; elapsed = 00:27:22 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23709 ; free virtual = 71529

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 20.4253 %
  Global Horizontal Routing Utilization  = 19.9032 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 90.991%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X54Y404 -> INT_L_X54Y404
   INT_L_X46Y401 -> INT_L_X46Y401
   INT_L_X78Y398 -> INT_L_X78Y398
   INT_L_X56Y383 -> INT_L_X56Y383
   INT_R_X55Y377 -> INT_R_X55Y377
South Dir 2x2 Area, Max Cong = 90.0901%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X62Y242 -> INT_R_X63Y243
   INT_L_X50Y238 -> INT_R_X51Y239
   INT_L_X62Y232 -> INT_R_X63Y233
East Dir 1x1 Area, Max Cong = 91.1765%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X56Y379 -> INT_L_X56Y379
   INT_L_X56Y371 -> INT_L_X56Y371
   INT_L_X76Y279 -> INT_L_X76Y279
   INT_L_X66Y270 -> INT_L_X66Y270
West Dir 1x1 Area, Max Cong = 86.7647%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_R_X17Y390 -> INT_R_X17Y390
   INT_L_X84Y227 -> INT_L_X84Y227
   INT_R_X63Y136 -> INT_R_X63Y136

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 2 Aspect Ratio: 0.8 Sparse Ratio: 0.5625
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1

Phase 8 Route finalize | Checksum: 211f2571f

Time (s): cpu = 00:27:16 ; elapsed = 00:27:24 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23709 ; free virtual = 71529

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 211f2571f

Time (s): cpu = 00:27:18 ; elapsed = 00:27:26 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23709 ; free virtual = 71528

Phase 10 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin alternate_cttc.fm_interface_3/combined_transceiver/common0_i/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y9/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y30/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y31/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y7/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y36/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y37/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y35/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y34/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y33/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y32/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y15/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y14/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y12/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y13/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y11/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y10/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y9/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y8/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y0/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_tob1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y3/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_tob1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y2/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_tob1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y0/GTSOUTHREFCLK1
Phase 10 Depositing Routes | Checksum: 23a772568

Time (s): cpu = 00:27:49 ; elapsed = 00:27:57 . Memory (MB): peak = 8092.758 ; gain = 628.492 ; free physical = 23711 ; free virtual = 71530

Phase 11 Incr Placement Change
Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 8092.758 ; gain = 0.000 ; free physical = 23703 ; free virtual = 71523
INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.541. For the most accurate timing information please run report_timing.
Ending IncrPlace Task | Checksum: 177676142

Time (s): cpu = 00:04:02 ; elapsed = 00:04:04 . Memory (MB): peak = 8759.250 ; gain = 666.492 ; free physical = 23037 ; free virtual = 70856
Phase 11 Incr Placement Change | Checksum: 177676142

Time (s): cpu = 00:32:31 ; elapsed = 00:32:41 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23036 ; free virtual = 70856

Phase 12 Build RT Design
Checksum: PlaceDB: b2ebb155 ConstDB: 0 ShapeSum: 26e85835 RouteDB: 9d9357b8
Post Restoration Checksum: NetGraph: 78445ccb | NumContArr: fafb7006 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 12 Build RT Design | Checksum: 2f891c20b

Time (s): cpu = 00:34:45 ; elapsed = 00:34:56 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23031 ; free virtual = 70851

Phase 13 Router Initialization

Phase 13.1 Fix Topology Constraints
Phase 13.1 Fix Topology Constraints | Checksum: 2f891c20b

Time (s): cpu = 00:34:49 ; elapsed = 00:35:01 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23031 ; free virtual = 70851

Phase 13.2 Pre Route Cleanup
Phase 13.2 Pre Route Cleanup | Checksum: 260e30799

Time (s): cpu = 00:34:53 ; elapsed = 00:35:04 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23031 ; free virtual = 70851
 Number of Nodes with overlaps = 0

Phase 13.3 Update Timing
Phase 13.3 Update Timing | Checksum: 27a02a052

Time (s): cpu = 00:38:13 ; elapsed = 00:38:25 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23032 ; free virtual = 70852
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.542 | TNS=-1631.261| WHS=-2.045 | THS=-29318.093|


Phase 13.4 Update Timing for Bus Skew

Phase 13.4.1 Update Timing
Phase 13.4.1 Update Timing | Checksum: 2084ea5bc

Time (s): cpu = 00:39:51 ; elapsed = 00:40:04 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23030 ; free virtual = 70849
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.542 | TNS=-1468.640| WHS=N/A    | THS=N/A    |

Phase 13.4 Update Timing for Bus Skew | Checksum: 1b6b652ee

Time (s): cpu = 00:39:54 ; elapsed = 00:40:07 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23030 ; free virtual = 70849

Router Utilization Summary
  Global Vertical Routing Utilization    = 20.0325 %
  Global Horizontal Routing Utilization  = 19.5296 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 754
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 364
  Number of Partially Routed Nets     = 390
  Number of Node Overlaps             = 2

Phase 13 Router Initialization | Checksum: 1fdeb0330

Time (s): cpu = 00:40:01 ; elapsed = 00:40:14 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23024 ; free virtual = 70843

Phase 14 Initial Routing

Phase 14.1 Global Routing
Phase 14.1 Global Routing | Checksum: 1fdeb0330

Time (s): cpu = 00:40:02 ; elapsed = 00:40:15 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23024 ; free virtual = 70843

Phase 14.2 Initial Net Routing
Phase 14.2 Initial Net Routing | Checksum: 2d32cbd83

Time (s): cpu = 00:41:02 ; elapsed = 00:41:15 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23023 ; free virtual = 70842
Phase 14 Initial Routing | Checksum: 2d32cbd83

Time (s): cpu = 00:41:04 ; elapsed = 00:41:17 . Memory (MB): peak = 8761.324 ; gain = 1297.059 ; free physical = 23023 ; free virtual = 70842
INFO: [Route 35-580] Design has 117 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+=================================+=================================+====================================================================================================================================================================+
| Launch Setup Clock              | Launch Hold Clock               | Pin                                                                                                                                                                |
+=================================+=================================+====================================================================================================================================================================+
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[7]/D |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[7]/D     |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[5]/D |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[0]/D |
| pp_clock_packet_processor_clock | pp_clock_packet_processor_clock | Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_1_allx_typeA_inst/probeDelay1_reg[8]/D     |
+---------------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 15 Rip-up And Reroute

Phase 15.1 Global Iteration 0
 Number of Nodes with overlaps = 2642
 Number of Nodes with overlaps = 92
 Number of Nodes with overlaps = 13
 Number of Nodes with overlaps = 7
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2405.637| WHS=N/A    | THS=N/A    |

Phase 15.1 Global Iteration 0 | Checksum: 1f77be2df

Time (s): cpu = 00:46:56 ; elapsed = 00:47:11 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23001 ; free virtual = 70821

Phase 15.2 Global Iteration 1
 Number of Nodes with overlaps = 23
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2353.735| WHS=N/A    | THS=N/A    |

Phase 15.2 Global Iteration 1 | Checksum: 24ec76670

Time (s): cpu = 00:47:10 ; elapsed = 00:47:25 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 22999 ; free virtual = 70819
Phase 15 Rip-up And Reroute | Checksum: 24ec76670

Time (s): cpu = 00:47:11 ; elapsed = 00:47:26 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 22999 ; free virtual = 70819

Phase 16 Delay and Skew Optimization

Phase 16.1 Delay CleanUp

Phase 16.1.1 Update Timing
Phase 16.1.1 Update Timing | Checksum: 2855ca6fd

Time (s): cpu = 00:47:48 ; elapsed = 00:48:03 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23001 ; free virtual = 70821
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-2212.730| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 16.1 Delay CleanUp | Checksum: 33a57508f

Time (s): cpu = 00:48:06 ; elapsed = 00:48:21 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23001 ; free virtual = 70821

Phase 16.2 Clock Skew Optimization
Phase 16.2 Clock Skew Optimization | Checksum: 33a57508f

Time (s): cpu = 00:48:07 ; elapsed = 00:48:22 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23001 ; free virtual = 70821
Phase 16 Delay and Skew Optimization | Checksum: 33a57508f

Time (s): cpu = 00:48:08 ; elapsed = 00:48:23 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23001 ; free virtual = 70821

Phase 17 Post Hold Fix

Phase 17.1 Hold Fix Iter

Phase 17.1.1 Update Timing
Phase 17.1.1 Update Timing | Checksum: 34f8fcc32

Time (s): cpu = 00:48:51 ; elapsed = 00:49:06 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 22999 ; free virtual = 70819
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-1667.703| WHS=-0.545 | THS=-989.818|

Phase 17.1 Hold Fix Iter | Checksum: 27dbc9330

Time (s): cpu = 00:48:57 ; elapsed = 00:49:13 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23009 ; free virtual = 70829

Phase 17.2 Non Free Resource Hold Fix Iter
Phase 17.2 Non Free Resource Hold Fix Iter | Checksum: 2c3f7be90

Time (s): cpu = 00:48:59 ; elapsed = 00:49:14 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23009 ; free virtual = 70829
WARNING: [Route 35-468] The router encountered 143 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are:
	Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[11].U_M_i_1/I0
	event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[10].U_M_i_24/I0
	event_builder/CTTC_receiver_i_10/I1
	event_builder/CTTC_receiver_i_11/I1
	event_builder/CTTC_receiver_i_2/I1
	event_builder/CTTC_receiver_i_7/I1
	event_builder/CTTC_receiver_i_8/I1
	event_builder/CTTC_receiver_i_9/I1
	event_builder/CTTC_receiver_i_1/I2
	event_builder/CTTC_receiver_i_12/I2
	.. and 133 more pins.

Phase 17 Post Hold Fix | Checksum: 2c3f7be90

Time (s): cpu = 00:48:59 ; elapsed = 00:49:15 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23009 ; free virtual = 70829

Phase 18 Timing Verification

Phase 18.1 Update Timing
Phase 18.1 Update Timing | Checksum: 2a76dd6f2

Time (s): cpu = 00:49:53 ; elapsed = 00:50:09 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23017 ; free virtual = 70837
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.541 | TNS=-1699.374| WHS=N/A    | THS=N/A    |

Phase 18 Timing Verification | Checksum: 2a76dd6f2

Time (s): cpu = 00:49:54 ; elapsed = 00:50:09 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23017 ; free virtual = 70837

Phase 19 Reset Design
INFO: [Route 35-307] 371372 nets already restored were skipped.
Post Restoration Checksum: NetGraph: 663442c0 | NumContArr: e260848 | Constraints: c2a8fa9d | Timing: a34e1c6a

Phase 19.1 Create Timer
Phase 19.1 Create Timer | Checksum: 1da51620f

Time (s): cpu = 00:50:04 ; elapsed = 00:50:20 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23015 ; free virtual = 70835
Phase 19 Reset Design | Checksum: 1da51620f

Time (s): cpu = 00:51:00 ; elapsed = 00:51:16 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23018 ; free virtual = 70838

Phase 20 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=-3.541 | TNS=-2131.972| WHS=0.050  | THS=0.000  |

Phase 20 Post Router Timing | Checksum: 147e434eb

Time (s): cpu = 00:53:20 ; elapsed = 00:53:37 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23024 ; free virtual = 70844
CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.
Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths.
INFO: [Route 35-253] TNS is the sum of the worst slack violation on every endpoint in the design. Review the paths with the biggest WNS violations in the timing reports and modify your constraints or your design to improve both WNS and TNS.
INFO: [Route 35-16] Router Completed Successfully

Phase 21 Post-Route Event Processing
Phase 21 Post-Route Event Processing | Checksum: 164855cbb

Time (s): cpu = 00:53:32 ; elapsed = 00:53:49 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23024 ; free virtual = 70844
Ending Routing Task | Checksum: 164855cbb

Time (s): cpu = 00:53:42 ; elapsed = 00:53:58 . Memory (MB): peak = 8786.324 ; gain = 1322.059 ; free physical = 23024 ; free virtual = 70844

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
538 Infos, 248 Warnings, 15 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:54:48 ; elapsed = 00:55:05 . Memory (MB): peak = 8786.324 ; gain = 1346.059 ; free physical = 23013 ; free virtual = 70833
INFO: [runtcl-4] Executing : report_drc -file top_rod_jfex_p2_drc_routed.rpt -pb top_rod_jfex_p2_drc_routed.pb -rpx top_rod_jfex_p2_drc_routed.rpx
Command: report_drc -file top_rod_jfex_p2_drc_routed.rpt -pb top_rod_jfex_p2_drc_routed.pb -rpx top_rod_jfex_p2_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex_p2/rod_jfex_p2.runs/impl_1/top_rod_jfex_p2_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:01:45 ; elapsed = 00:01:46 . Memory (MB): peak = 8786.324 ; gain = 0.000 ; free physical = 23018 ; free virtual = 70838
INFO: [runtcl-4] Executing : report_methodology -file top_rod_jfex_p2_methodology_drc_routed.rpt -pb top_rod_jfex_p2_methodology_drc_routed.pb -rpx top_rod_jfex_p2_methodology_drc_routed.rpx
Command: report_methodology -file top_rod_jfex_p2_methodology_drc_routed.rpt -pb top_rod_jfex_p2_methodology_drc_routed.pb -rpx top_rod_jfex_p2_methodology_drc_routed.rpx
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex_p2/rod_jfex_p2.runs/impl_1/top_rod_jfex_p2_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:04:44 ; elapsed = 00:04:46 . Memory (MB): peak = 8786.324 ; gain = 0.000 ; free physical = 23036 ; free virtual = 70858
INFO: [runtcl-4] Executing : report_power -file top_rod_jfex_p2_power_routed.rpt -pb top_rod_jfex_p2_power_summary_routed.pb -rpx top_rod_jfex_p2_power_routed.rpx
Command: report_power -file top_rod_jfex_p2_power_routed.rpt -pb top_rod_jfex_p2_power_summary_routed.pb -rpx top_rod_jfex_p2_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUP_INCLUDE.GEN_7Series_STARTUP.STARTUPE2_inst
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
550 Infos, 249 Warnings, 15 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:02:42 ; elapsed = 00:01:41 . Memory (MB): peak = 8842.352 ; gain = 56.027 ; free physical = 22994 ; free virtual = 70843
INFO: [runtcl-4] Executing : report_route_status -file top_rod_jfex_p2_route_status.rpt -pb top_rod_jfex_p2_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file top_rod_jfex_p2_timing_summary_routed.rpt -pb top_rod_jfex_p2_timing_summary_routed.pb -rpx top_rod_jfex_p2_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:01:07 ; elapsed = 00:01:07 . Memory (MB): peak = 8842.352 ; gain = 0.000 ; free physical = 22906 ; free virtual = 70848
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_rod_jfex_p2_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_rod_jfex_p2_clock_utilization_routed.rpt
report_clock_utilization: Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 8842.352 ; gain = 0.000 ; free physical = 22901 ; free virtual = 70843
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_rod_jfex_p2_bus_skew_routed.rpt -pb top_rod_jfex_p2_bus_skew_routed.pb -rpx top_rod_jfex_p2_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_timing_summary -file top_rod_jfex_p2_timing_summary_routed_1.rpt -pb top_rod_jfex_p2_timing_summary_routed_1.pb -rpx top_rod_jfex_p2_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 8842.352 ; gain = 0.000 ; free physical = 22888 ; free virtual = 70842
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
source /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:Msg-0] Evaluating Git sha for rod_jfex_p2...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Top/rod_jfex_p2 clean.
INFO: [Hog:Msg-0] Git describe set to: v1.0.5-5811E1B
INFO: [Hog:Msg-0] Evaluating last git SHA in which rod_jfex_p2 was modified...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Top/rod_jfex_p2 clean.
INFO: [Hog:Msg-0] The git SHA value 5811e1b will be embedded in the binary file.
INFO: [Hog:Msg-0] Evaluating Git sha for rod_jfex_p2...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/Top/rod_jfex_p2 clean.
INFO: [Hog:Msg-0] Git describe set to: v1.0.5-5811E1B
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3z6zVWd3g/0/atlas-l1calo-efex/RODFirmware/bin/rod_jfex_p2-v1.0.5-5811E1B...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
report_utilization: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 8842.352 ; gain = 0.000 ; free physical = 22928 ; free virtual = 70888