
// file: ClockWizard.v
// 
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
//----------------------------------------------------------------------------
// __clk200__200.50000______0.000______50.0______119.104____145.133
// ____load__40.10000______0.000______11.4______149.918____145.133
// __clk280__280.70000______0.000______50.0______113.732____145.133
// ___clk40__40.10000______0.000______50.0______149.918____145.133
//
//----------------------------------------------------------------------------
// Input Clock   Freq (MHz)    Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary__________40.100____________0.010

`timescale 1ps/1ps

module ClockWizard_clk_wiz 

 (// Clock in ports
  // Clock out ports
  output        clk200,
  output        load,
  output        clk280,
  output        clk40,
  // Status and control signals
  input         reset,
  output        locked,
  input         clk_in1_p,
  input         clk_in1_n
 );
  // Input buffering
  //------------------------------------
wire clk_in1_ClockWizard;
wire clk_in2_ClockWizard;
  IBUFDS clkin1_ibufgds
   (.O  (clk_in1_ClockWizard),
    .I  (clk_in1_p),
    .IB (clk_in1_n));




  // Clocking PRIMITIVE
  //------------------------------------

  // Instantiation of the MMCM PRIMITIVE
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused

  wire        clk200_ClockWizard;
  wire        load_ClockWizard;
  wire        clk280_ClockWizard;
  wire        clk40_ClockWizard;
  wire        clk_out5_ClockWizard;
  wire        clk_out6_ClockWizard;
  wire        clk_out7_ClockWizard;

  wire [15:0] do_unused;
  wire        drdy_unused;
  wire        psdone_unused;
  wire        locked_int;
  wire        clkfbout_ClockWizard;
  wire        clkfbout_buf_ClockWizard;
  wire        clkfboutb_unused;
    wire clkout0b_unused;
   wire clkout1b_unused;
   wire clkout2b_unused;
   wire clkout3b_unused;
   wire clkout4_unused;
  wire        clkout5_unused;
  wire        clkout6_unused;
  wire        clkfbstopped_unused;
  wire        clkinstopped_unused;
  wire        reset_high;

  MMCME2_ADV
  #(.BANDWIDTH            ("OPTIMIZED"),
    .CLKOUT4_CASCADE      ("FALSE"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (1),
    .CLKFBOUT_MULT_F      (35.000),
    .CLKFBOUT_PHASE       (0.000),
    .CLKFBOUT_USE_FINE_PS ("FALSE"),
    .CLKOUT0_DIVIDE_F     (7.000),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKOUT0_USE_FINE_PS  ("FALSE"),
    .CLKOUT1_DIVIDE       (35),
    .CLKOUT1_PHASE        (0.000),
    .CLKOUT1_DUTY_CYCLE   (0.114),
    .CLKOUT1_USE_FINE_PS  ("FALSE"),
    .CLKOUT2_DIVIDE       (5),
    .CLKOUT2_PHASE        (0.000),
    .CLKOUT2_DUTY_CYCLE   (0.500),
    .CLKOUT2_USE_FINE_PS  ("FALSE"),
    .CLKOUT3_DIVIDE       (35),
    .CLKOUT3_PHASE        (0.000),
    .CLKOUT3_DUTY_CYCLE   (0.500),
    .CLKOUT3_USE_FINE_PS  ("FALSE"),
    .CLKIN1_PERIOD        (24.938))
  mmcm_adv_inst
    // Output clocks
   (
    .CLKFBOUT            (clkfbout_ClockWizard),
    .CLKFBOUTB           (clkfboutb_unused),
    .CLKOUT0             (clk200_ClockWizard),
    .CLKOUT0B            (clkout0b_unused),
    .CLKOUT1             (load_ClockWizard),
    .CLKOUT1B            (clkout1b_unused),
    .CLKOUT2             (clk280_ClockWizard),
    .CLKOUT2B            (clkout2b_unused),
    .CLKOUT3             (clk40_ClockWizard),
    .CLKOUT3B            (clkout3b_unused),
    .CLKOUT4             (clkout4_unused),
    .CLKOUT5             (clkout5_unused),
    .CLKOUT6             (clkout6_unused),
     // Input clock control
    .CLKFBIN             (clkfbout_buf_ClockWizard),
    .CLKIN1              (clk_in1_ClockWizard),
    .CLKIN2              (1'b0),
     // Tied to always select the primary input clock
    .CLKINSEL            (1'b1),
    // Ports for dynamic reconfiguration
    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (do_unused),
    .DRDY                (drdy_unused),
    .DWE                 (1'b0),
    // Ports for dynamic phase shift
    .PSCLK               (1'b0),
    .PSEN                (1'b0),
    .PSINCDEC            (1'b0),
    .PSDONE              (psdone_unused),
    // Other control and status signals
    .LOCKED              (locked_int),
    .CLKINSTOPPED        (clkinstopped_unused),
    .CLKFBSTOPPED        (clkfbstopped_unused),
    .PWRDWN              (1'b0),
    .RST                 (reset_high));
  assign reset_high = reset; 

  assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
 // Output buffering
  //-----------------------------------

  BUFG clkf_buf
   (.O (clkfbout_buf_ClockWizard),
    .I (clkfbout_ClockWizard));






  BUFG clkout1_buf
   (.O   (clk200),
    .I   (clk200_ClockWizard));


  BUFG clkout2_buf
   (.O   (load),
    .I   (load_ClockWizard));

  BUFG clkout3_buf
   (.O   (clk280),
    .I   (clk280_ClockWizard));

  BUFG clkout4_buf
   (.O   (clk40),
    .I   (clk40_ClockWizard));



endmodule
