-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Thu Dec  3 17:16:13 2020
-- Host        : ftm-vm.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode synth_stub
--               /home/gitlab-runner/builds/CbUeS3Wi/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_stub.vhdl
-- Design      : ClockWizard
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xc7vx550tffg1927-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ClockWizard is
  Port ( 
    clk200 : out STD_LOGIC;
    load : out STD_LOGIC;
    clk280 : out STD_LOGIC;
    clk40 : out STD_LOGIC;
    reset : in STD_LOGIC;
    locked : out STD_LOGIC;
    clk_in1_p : in STD_LOGIC;
    clk_in1_n : in STD_LOGIC
  );

end ClockWizard;

architecture stub of ClockWizard is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk200,load,clk280,clk40,reset,locked,clk_in1_p,clk_in1_n";
begin
end;
