
// file: ClockWizard.v
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
//----------------------------------------------------------------------------
// __clk200__200.50000______0.000______50.0______119.104____145.133
// ____load__40.10000______0.000______11.4______149.918____145.133
// __clk280__280.70000______0.000______50.0______113.732____145.133
// ___clk40__40.10000______0.000______50.0______149.918____145.133
//
//----------------------------------------------------------------------------
// Input Clock   Freq (MHz)    Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary__________40.100____________0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "ClockWizard,clk_wiz_v6_0_4_0_0,{component_name=ClockWizard,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=24.938,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)

module ClockWizard 
 (
  // Clock out ports
  output        clk200,
  output        load,
  output        clk280,
  output        clk40,
  // Status and control signals
  input         reset,
  output        locked,
 // Clock in ports
  input         clk_in1_p,
  input         clk_in1_n
 );

  ClockWizard_clk_wiz inst
  (
  // Clock out ports  
  .clk200(clk200),
  .load(load),
  .clk280(clk280),
  .clk40(clk40),
  // Status and control signals               
  .reset(reset), 
  .locked(locked),
 // Clock in ports
  .clk_in1_p(clk_in1_p),
  .clk_in1_n(clk_in1_n)
  );

endmodule
