// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
// Date        : Wed Mar  5 08:04:48 2025
// Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit AlmaLinux 9.5 (Teal Serval)
// Command     : write_verilog -force -mode synth_stub
//               /fast/gitlab-runner-home/builds/zqy4JUuos/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/DPR_252b_512/DPR_252b_512_stub.v
// Design      : DPR_252b_512
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
module DPR_252b_512(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[8:0],dina[251:0],clkb,enb,addrb[8:0],doutb[251:0]" */;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [251:0]dina;
  input clkb;
  input enb;
  input [8:0]addrb;
  output [251:0]doutb;
endmodule
