// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Fri Aug 14 17:49:05 2020
// Host        : hog-efex3.cern.ch running 64-bit CentOS Linux release 7.8.2003 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/xeGdLrzp/3/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_332b_512/DPR_332b_512_stub.v
// Design      : DPR_332b_512
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *)
module DPR_332b_512(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[8:0],dina[331:0],clkb,enb,addrb[8:0],doutb[331:0]" */;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [331:0]dina;
  input clkb;
  input enb;
  input [8:0]addrb;
  output [331:0]doutb;
endmodule
