// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
// Date        : Mon Jul  4 11:56:07 2022
// Host        : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024_stub.v
// Design      : DPR_36b_1024
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_5,Vivado 2022.1" *)
module DPR_36b_1024(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[35:0],clkb,enb,addrb[9:0],doutb[35:0]" */;
  input clka;
  input ena;
  input [0:0]wea;
  input [9:0]addra;
  input [35:0]dina;
  input clkb;
  input enb;
  input [9:0]addrb;
  output [35:0]doutb;
endmodule
