// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
// Date        : Wed Mar  5 07:48:36 2025
// Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit AlmaLinux 9.5 (Teal Serval)
// Command     : write_verilog -force -mode synth_stub
//               /fast/gitlab-runner-home/builds/zqy4JUuos/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_stub.v
// Design      : FIFO_252b_512
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *)
module FIFO_252b_512(rst, wr_clk, rd_clk, din, wr_en, rd_en, 
  prog_full_thresh_assert, prog_full_thresh_negate, dout, full, empty, valid, rd_data_count, 
  wr_data_count, prog_full, wr_rst_busy, rd_rst_busy)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[251:0],wr_en,rd_en,prog_full_thresh_assert[8:0],prog_full_thresh_negate[8:0],dout[251:0],full,empty,valid,rd_data_count[8:0],wr_data_count[8:0],prog_full,wr_rst_busy,rd_rst_busy" */;
  input rst;
  input wr_clk;
  input rd_clk;
  input [251:0]din;
  input wr_en;
  input rd_en;
  input [8:0]prog_full_thresh_assert;
  input [8:0]prog_full_thresh_negate;
  output [251:0]dout;
  output full;
  output empty;
  output valid;
  output [8:0]rd_data_count;
  output [8:0]wr_data_count;
  output prog_full;
  output wr_rst_busy;
  output rd_rst_busy;
endmodule
