// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Fri Aug 14 17:59:29 2020
// Host        : hog-efex3.cern.ch running 64-bit CentOS Linux release 7.8.2003 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/xeGdLrzp/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_332b_512/FIFO_332b_512_stub.v
// Design      : FIFO_332b_512
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_5,Vivado 2019.2" *)
module FIFO_332b_512(rst, wr_clk, rd_clk, din, wr_en, rd_en, 
  prog_full_thresh_assert, prog_full_thresh_negate, dout, full, empty, valid, wr_data_count, 
  prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[331:0],wr_en,rd_en,prog_full_thresh_assert[8:0],prog_full_thresh_negate[8:0],dout[331:0],full,empty,valid,wr_data_count[8:0],prog_full" */;
  input rst;
  input wr_clk;
  input rd_clk;
  input [331:0]din;
  input wr_en;
  input rd_en;
  input [8:0]prog_full_thresh_assert;
  input [8:0]prog_full_thresh_negate;
  output [331:0]dout;
  output full;
  output empty;
  output valid;
  output [8:0]wr_data_count;
  output prog_full;
endmodule
