// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
// Date        : Mon Jul  4 12:00:06 2022
// Host        : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_stub.v
// Design      : FIFO_33b_8192
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_7,Vivado 2022.1" *)
module FIFO_33b_8192(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, 
  prog_full_thresh_assert, prog_full_thresh_negate, dout, full, empty, valid, rd_data_count, 
  wr_data_count, prog_full)
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[32:0],wr_en,rd_en,prog_full_thresh_assert[12:0],prog_full_thresh_negate[12:0],dout[32:0],full,empty,valid,rd_data_count[12:0],wr_data_count[12:0],prog_full" */;
  input wr_clk;
  input wr_rst;
  input rd_clk;
  input rd_rst;
  input [32:0]din;
  input wr_en;
  input rd_en;
  input [12:0]prog_full_thresh_assert;
  input [12:0]prog_full_thresh_negate;
  output [32:0]dout;
  output full;
  output empty;
  output valid;
  output [12:0]rd_data_count;
  output [12:0]wr_data_count;
  output prog_full;
endmodule
