// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
// Date        : Mon Jul  4 12:04:00 2022
// Host        : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_stub.v
// Design      : FIFO_54b_512
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_7,Vivado 2022.1" *)
module FIFO_54b_512(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, 
  empty, valid)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[53:0],wr_en,rd_en,dout[53:0],full,empty,valid" */;
  input rst;
  input wr_clk;
  input rd_clk;
  input [53:0]din;
  input wr_en;
  input rd_en;
  output [53:0]dout;
  output full;
  output empty;
  output valid;
endmodule
