-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
-- Date        : Mon Jul  4 11:50:48 2022
-- Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode synth_stub
--               /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_stub.vhdl
-- Design      : clk_ttc
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xc7vx330tffg1157-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clk_ttc is
  Port ( 
    clk40 : out STD_LOGIC;
    clk320 : out STD_LOGIC;
    clk160 : out STD_LOGIC;
    locked : out STD_LOGIC;
    clk_in1_p : in STD_LOGIC;
    clk_in1_n : in STD_LOGIC
  );

end clk_ttc;

architecture stub of clk_ttc is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk40,clk320,clk160,locked,clk_in1_p,clk_in1_n";
begin
end;
