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--

--
--  TX_GLOBAL_LOGIC_SIMPLEX
--
--
--
--  Description: The GLOBAL_LOGIC module handles channel bonding, channel
--               verification, channel error manangement and idle generation in simplex mode.
--
--               This module supports 4 2-byte lane designs
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX is

    port (

    -- Aurora Lane Interface

LANE_UP            : in std_logic_vector(0 to 3);
HARD_ERR         : in std_logic_vector(0 to 3);
GEN_A              : out std_logic_vector(0 to 3);
GEN_K              : out std_logic_vector(0 to 7);
GEN_R              : out std_logic_vector(0 to 7);
GEN_V              : out std_logic_vector(0 to 7);
RESET_LANES        : out std_logic_vector(0 to 3);

    -- Sideband Signal
            TX_BONDED          : in std_logic;
            TX_VERIFY          : in std_logic;
           
    -- System Interface

            USER_CLK           : in std_logic;
            RESET              : in std_logic;
            POWER_DOWN         : in std_logic;
            CHANNEL_UP         : out std_logic;
            CHANNEL_HARD_ERR : out std_logic

         );

end efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX;

architecture MAPPED of efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX is

-- External Register Declarations --

signal GEN_A_Buffer              : std_logic_vector(0 to 3);
signal GEN_K_Buffer              : std_logic_vector(0 to 7);
signal GEN_R_Buffer              : std_logic_vector(0 to 7);
signal GEN_V_Buffer              : std_logic_vector(0 to 7);
signal RESET_LANES_Buffer        : std_logic_vector(0 to 3);
    signal CHANNEL_UP_Buffer         : std_logic;
    signal CHANNEL_HARD_ERR_Buffer : std_logic;

-- Wire Declarations --

    signal gen_ver_i       : std_logic;
    signal reset_channel_i : std_logic;
    signal did_ver_i       : std_logic;

-- Component Declarations --

    component efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX

        port (

        -- Aurora Lane Interface

RESET_LANES       : out std_logic_vector(0 to 3);

        -- Sideband Signal
                TX_BONDED         : in std_logic;
                TX_VERIFY         : in std_logic;

        -- System Interface

                USER_CLK          : in std_logic;
                RESET             : in std_logic;
                CHANNEL_UP        : out std_logic;

        -- Idle and Verification Sequence Generator Interface

                GEN_VER           : out std_logic;

        -- Channel Init State Machine Interface

                RESET_CHANNEL     : in std_logic

             );

    end component;


    component efex_aurora_hub2_IDLE_AND_VER_GEN

        port (

        -- Channel Init SM Interface

                GEN_VER  : in std_logic;
                DID_VER  : out std_logic;

        -- Aurora Lane Interface

GEN_A    : out std_logic_vector(0 to 3);
GEN_K    : out std_logic_vector(0 to 7);
GEN_R    : out std_logic_vector(0 to 7);
GEN_V    : out std_logic_vector(0 to 7);

        -- System Interface

                RESET    : in std_logic;
                USER_CLK : in std_logic

             );

    end component;


    component efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX

        port (

        -- Aurora Lane Interface

HARD_ERR         : in std_logic_vector(0 to 3);
LANE_UP            : in std_logic_vector(0 to 3);

        -- System Interface

                USER_CLK           : in std_logic;
                POWER_DOWN         : in std_logic;

                CHANNEL_HARD_ERR : out std_logic;

        -- Channel Init SM Interface

                RESET_CHANNEL      : out std_logic

             );

    end component;

begin

    GEN_A              <= GEN_A_Buffer;
    GEN_K              <= GEN_K_Buffer;
    GEN_R              <= GEN_R_Buffer;
    GEN_V              <= GEN_V_Buffer;
    RESET_LANES        <= RESET_LANES_Buffer;
    CHANNEL_UP         <= CHANNEL_UP_Buffer;
    CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;

-- Main Body of Code --

    -- State Machine for channel bonding and verification.

    tx_channel_init_sm_simplex_i : efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX

        port map (


        -- Aurora Lane Interface

                    RESET_LANES => RESET_LANES_Buffer,

        -- Sideband Signals
                    TX_BONDED   => TX_BONDED,
                    TX_VERIFY   => TX_VERIFY,
                   
        -- System Interface

                    USER_CLK => USER_CLK,
                    RESET => RESET,
                    CHANNEL_UP => CHANNEL_UP_Buffer,

        -- Idle and Verification Sequence Generator Interface

                    GEN_VER => gen_ver_i,

        -- Channel Error Management Module Interface

                    RESET_CHANNEL => reset_channel_i

                 );


    -- Idle and verification sequence generator module.

    idle_and_ver_gen_i : efex_aurora_hub2_IDLE_AND_VER_GEN

        port map (

        -- Channel Init SM Interface

                    GEN_VER => gen_ver_i,
                    DID_VER => did_ver_i,

        -- Aurora Lane Interface

                    GEN_A => GEN_A_Buffer,
                    GEN_K => GEN_K_Buffer,
                    GEN_R => GEN_R_Buffer,
                    GEN_V => GEN_V_Buffer,

        -- System Interface

                    RESET => RESET,
                    USER_CLK => USER_CLK

                 );



    -- Channel Error Management module.

    tx_channel_err_detect_simplex_i : efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX

        port map (

        -- Aurora Lane Interface

                    HARD_ERR => HARD_ERR,
                    LANE_UP => LANE_UP,

        -- System Interface

                    USER_CLK => USER_CLK,
                    POWER_DOWN => POWER_DOWN,
                    CHANNEL_HARD_ERR => CHANNEL_HARD_ERR_Buffer,

        -- Channel Init State Machine Interface

                    RESET_CHANNEL => reset_channel_i

                 );

end MAPPED;
