// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Fri Aug 14 17:35:35 2020
// Host        : rod-vm.cern.ch running 64-bit CentOS Linux release 7.8.2003 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/bb8b4gKx/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_stub.v
// Design      : efex_aurora_hub2
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx330tffg1157-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module efex_aurora_hub2(s_axi_tx_tdata, s_axi_tx_tvalid, 
  s_axi_tx_tready, s_axi_tx_tkeep, s_axi_tx_tlast, s_axi_ufc_tx_tvalid, s_axi_ufc_tx_tdata, 
  s_axi_ufc_tx_tready, txp, txn, gt_refclk1, tx_hard_err, tx_lane_up, tx_channel_up, user_clk, 
  sync_clk, tx_system_reset, power_down, loopback, gt_reset, tx_lock, sys_reset_out, init_clk_in, 
  tx_resetdone_out, drpclk_in, drpaddr_in, drpdi_in, drpdo_out, drpen_in, drprdy_out, drpwe_in, 
  drpaddr_in_lane1, drpdi_in_lane1, drpdo_out_lane1, drpen_in_lane1, drprdy_out_lane1, 
  drpwe_in_lane1, drpaddr_in_lane2, drpdi_in_lane2, drpdo_out_lane2, drpen_in_lane2, 
  drprdy_out_lane2, drpwe_in_lane2, drpaddr_in_lane3, drpdi_in_lane3, drpdo_out_lane3, 
  drpen_in_lane3, drprdy_out_lane3, drpwe_in_lane3, gt0_qplllock_in, gt0_qpllrefclklost_in, 
  gt0_qpllreset_out, gt_qpllclk_quad5_in, gt_qpllrefclk_quad5_in, tx_out_clk, 
  pll_not_locked)
/* synthesis syn_black_box black_box_pad_pin="s_axi_tx_tdata[63:0],s_axi_tx_tvalid,s_axi_tx_tready,s_axi_tx_tkeep[7:0],s_axi_tx_tlast,s_axi_ufc_tx_tvalid,s_axi_ufc_tx_tdata[2:0],s_axi_ufc_tx_tready,txp[0:3],txn[0:3],gt_refclk1,tx_hard_err,tx_lane_up[0:3],tx_channel_up,user_clk,sync_clk,tx_system_reset,power_down,loopback[2:0],gt_reset,tx_lock,sys_reset_out,init_clk_in,tx_resetdone_out,drpclk_in,drpaddr_in[8:0],drpdi_in[15:0],drpdo_out[15:0],drpen_in,drprdy_out,drpwe_in,drpaddr_in_lane1[8:0],drpdi_in_lane1[15:0],drpdo_out_lane1[15:0],drpen_in_lane1,drprdy_out_lane1,drpwe_in_lane1,drpaddr_in_lane2[8:0],drpdi_in_lane2[15:0],drpdo_out_lane2[15:0],drpen_in_lane2,drprdy_out_lane2,drpwe_in_lane2,drpaddr_in_lane3[8:0],drpdi_in_lane3[15:0],drpdo_out_lane3[15:0],drpen_in_lane3,drprdy_out_lane3,drpwe_in_lane3,gt0_qplllock_in,gt0_qpllrefclklost_in,gt0_qpllreset_out,gt_qpllclk_quad5_in,gt_qpllrefclk_quad5_in,tx_out_clk,pll_not_locked" */;
  input [63:0]s_axi_tx_tdata;
  input s_axi_tx_tvalid;
  output s_axi_tx_tready;
  input [7:0]s_axi_tx_tkeep;
  input s_axi_tx_tlast;
  input s_axi_ufc_tx_tvalid;
  input [2:0]s_axi_ufc_tx_tdata;
  output s_axi_ufc_tx_tready;
  output [0:3]txp;
  output [0:3]txn;
  input gt_refclk1;
  output tx_hard_err;
  output [0:3]tx_lane_up;
  output tx_channel_up;
  input user_clk;
  input sync_clk;
  input tx_system_reset;
  input power_down;
  input [2:0]loopback;
  input gt_reset;
  output tx_lock;
  output sys_reset_out;
  input init_clk_in;
  output tx_resetdone_out;
  input drpclk_in;
  input [8:0]drpaddr_in;
  input [15:0]drpdi_in;
  output [15:0]drpdo_out;
  input drpen_in;
  output drprdy_out;
  input drpwe_in;
  input [8:0]drpaddr_in_lane1;
  input [15:0]drpdi_in_lane1;
  output [15:0]drpdo_out_lane1;
  input drpen_in_lane1;
  output drprdy_out_lane1;
  input drpwe_in_lane1;
  input [8:0]drpaddr_in_lane2;
  input [15:0]drpdi_in_lane2;
  output [15:0]drpdo_out_lane2;
  input drpen_in_lane2;
  output drprdy_out_lane2;
  input drpwe_in_lane2;
  input [8:0]drpaddr_in_lane3;
  input [15:0]drpdi_in_lane3;
  output [15:0]drpdo_out_lane3;
  input drpen_in_lane3;
  output drprdy_out_lane3;
  input drpwe_in_lane3;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  output tx_out_clk;
  input pll_not_locked;
endmodule
