-----------------------------------------------------------------------
-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------------------------------
--  efex_aurora_hub2
--
--
--  Description: This is the top level module for a 4 2-byte lane
--               Simplex Aurora reference design module.
--
--               This module is a Simplex TX module. All GTs are used for
--               transmission only.
--               This module supports the following features:
--
--               * User Flow Control
--               * Supports GT
------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on

entity efex_aurora_hub2_core is
   generic(
          SIM_GTRESET_SPEEDUP : string  :=   "FALSE";
    CC_FREQ_FACTOR : integer := 24;
          EXAMPLE_SIMULATION  : integer :=  0      
          );
    port  (

    -- TX Stream Interface
S_AXI_TX_TDATA         : in  std_logic_vector(63 downto 0);
S_AXI_TX_TKEEP         : in std_logic_vector(7 downto 0);
            S_AXI_TX_TVALID        : in  std_logic;
            S_AXI_TX_TREADY        : out std_logic;
            S_AXI_TX_TLAST         : in  std_logic;


    -- User Flow Control TX Interface

            S_AXI_UFC_TX_REQ       : in std_logic;
            S_AXI_UFC_TX_MS        : in std_logic_vector(2 downto 0);
            S_AXI_UFC_TX_ACK       : out std_logic;


TXP              : out std_logic_vector(0 to 3);
TXN              : out std_logic_vector(0 to 3);

    -- GT Reference Clock Interface

            gt_refclk1    : in std_logic;
    -- Error Detection Interface

            TX_HARD_ERR    : out std_logic;

    -- Status

            TX_CHANNEL_UP    : out std_logic;
TX_LANE_UP       : out std_logic_vector(0 to 3);



    -- System Interface

            user_clk         : in  std_logic;
            sync_clk         : in  std_logic;
            TX_SYSTEM_RESET  : in  std_logic;
            TX_RESETDONE_OUT : out std_logic;
            POWER_DOWN       : in  std_logic;
            GT_RESET         : in  std_logic;
            TX_LOCK          : out std_logic;
            init_clk_in   : in  std_logic;
            PLL_NOT_LOCKED      : in  std_logic;
drpclk_in                                      : in   std_logic;
DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
DRPDI_IN                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
DRPEN_IN                                : in   std_logic;
DRPRDY_OUT                              : out  std_logic;
DRPWE_IN                                : in   std_logic;
DRPADDR_IN_LANE1                              : in   std_logic_vector(8 downto 0);
DRPDI_IN_LANE1                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE1                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE1                                : in   std_logic;
DRPRDY_OUT_LANE1                              : out  std_logic;
DRPWE_IN_LANE1                                : in   std_logic;
DRPADDR_IN_LANE2                              : in   std_logic_vector(8 downto 0);
DRPDI_IN_LANE2                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE2                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE2                                : in   std_logic;
DRPRDY_OUT_LANE2                              : out  std_logic;
DRPWE_IN_LANE2                                : in   std_logic;
DRPADDR_IN_LANE3                              : in   std_logic_vector(8 downto 0);
DRPDI_IN_LANE3                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE3                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE3                                : in   std_logic;
DRPRDY_OUT_LANE3                              : out  std_logic;
DRPWE_IN_LANE3                                : in   std_logic;
 
            TX_OUT_CLK       : out std_logic;
--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad5_in   : in  std_logic;
   gt_qpllrefclk_quad5_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}


            sys_reset_out   : out std_logic; 
            LOOPBACK         : in  std_logic_vector(2 downto 0)
         );

end efex_aurora_hub2_core;

architecture MAPPED of efex_aurora_hub2_core is
  attribute core_generation_info           : string;
attribute core_generation_info of MAPPED : architecture is "efex_aurora_hub2,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=left,c_gt_clock_1=GTHQ4,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=1,c_gt_loc_18=2,c_gt_loc_19=3,c_gt_loc_2=X,c_gt_loc_20=4,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=64120,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160300,c_simplex=true,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=TX-only_Simplex}";

    -- Parameter Declarations --
    constant DLY : time := 1 ns;
           -- Simplex timer parameters
    constant C_SIMPLEX_TIMER       : integer  := 18;     -- Simplex Timer 
    constant C_ALIGNED_TIMER       : integer  := 158990;  -- Timer to assert TX_ALIGNED signal 
    constant C_BONDED_TIMER        : integer  := C_ALIGNED_TIMER + 4096;  -- Timer to assert TX_BONDED signal 
    constant C_VERIFY_TIMER        : integer  := C_BONDED_TIMER + 512;  -- Timer to assert TX_VERIFY signal 
    constant WATCHDOG_TIMEOUT      : integer := 14;

--*********************************Component Declarations****************************

    component efex_aurora_hub2_RESET_LOGIC
    port (
           RESET                  : in std_logic;
           USER_CLK               : in std_logic;
           INIT_CLK_IN            : in std_logic;
           TX_LOCK_IN             : in std_logic;
           PLL_NOT_LOCKED         : in std_logic;
           LINK_RESET_IN          : in std_logic;
           TX_RESETDONE_IN        : in std_logic;
           SYSTEM_RESET           : out std_logic
         );
     end component;

   -- AXI Shim modules
   component efex_aurora_hub2_LL_TO_AXI is
   generic
   (
    DATA_WIDTH  : integer :=   16;      -- DATA bus width
    USE_UFC_REM : integer :=   0;       -- UFC REM bus width identifier
    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
    REM_WIDTH   : integer :=   1        -- REM bus width
   );  

   port
   (

    ----------------------  AXI4-S Interface -------------------------------
    AXI4_S_OP_TDATA                 : out   std_logic_vector (DATA_WIDTH-1 downto 0);
    AXI4_S_OP_TKEEP                 : out   std_logic_vector (STRB_WIDTH-1 downto 0);
    AXI4_S_OP_TVALID                : out   std_logic;
    AXI4_S_OP_TLAST                 : out   std_logic;
    AXI4_S_IP_TREADY                : in    std_logic;

    ----------------------  LocalLink Interface ----------------------------
    LL_IP_DATA                      : in    std_logic_vector (0 to DATA_WIDTH-1);
    LL_IP_REM                       : in    std_logic_vector (0 to REM_WIDTH-1);
    LL_IP_SRC_RDY_N                 : in    std_logic;
    LL_IP_SOF_N                     : in    std_logic;
    LL_IP_EOF_N                     : in    std_logic;
    LL_OP_DST_RDY_N                 : out   std_logic

   );
   end component;

   component efex_aurora_hub2_AXI_TO_LL is
   generic
   (
    DATA_WIDTH  : integer :=   16;      -- DATA bus width
    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
    REM_WIDTH   : integer :=   1;       -- REM bus width
    USE_4_NFC   : integer :=   0;       --  0 => PDU, 1 => NFC, 2 => UFC
    USE_UFC_REM : integer :=   0        -- UFC REM bus width identifier
   );  

   port
   (

     ----------------------  AXI4-S Interface -------------------------------
     AXI4_S_IP_TX_TDATA              : in    std_logic_vector (DATA_WIDTH-1 downto 0);
     AXI4_S_IP_TX_TKEEP              : in    std_logic_vector (STRB_WIDTH-1 downto 0);
     AXI4_S_IP_TX_TVALID             : in    std_logic;
     AXI4_S_IP_TX_TLAST              : in    std_logic;
     AXI4_S_OP_TX_TREADY             : out   std_logic;

     ----------------------  LocalLink Interface ----------------------------
     LL_OP_DATA                      : out   std_logic_vector (0 to DATA_WIDTH-1);
     LL_OP_REM                       : out   std_logic_vector (0 to REM_WIDTH -1);
     LL_OP_SRC_RDY_N                 : out   std_logic;
     LL_OP_SOF_N                     : out   std_logic;
     LL_OP_EOF_N                     : out   std_logic;
     LL_IP_DST_RDY_N                 : in    std_logic;

     ----------------------  System Interface ----------------------------
     USER_CLK                        : in    std_logic;
     RESET                           : in    std_logic;
     CHANNEL_UP                      : in    std_logic

   );
   end component;
   

  component  efex_aurora_hub2_cdc_sync is
    generic (
        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
                                    -- 0 is pulse synch
                                    -- 1 is level synch
                                    -- 2 is ack based level sync
        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
                                    -- 0 is reset not needed 
                                    -- 1 is reset needed 
        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
                                    -- 0 is bus input
                                    -- 1 is single bit input
        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
        C_VECTOR_WIDTH              : integer range 0 to 32 := 32               ;
        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
            -- Vector Data witdth
    );

    port (
        prmry_aclk                  : in  std_logic                             ;               --
        prmry_resetn                : in  std_logic                             ;               --
        prmry_in                    : in  std_logic                             ;               --
        prmry_vect_in               : in  std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
        prmry_ack                   : out std_logic                             ;
                                                                                                --
        scndry_aclk                 : in  std_logic                             ;               --
        scndry_resetn               : in  std_logic                             ;               --
                                                                                                --
        -- Primary to Secondary Clock Crossing                                                  --
        scndry_out                  : out std_logic                             ;               --
                                                                                                --
        scndry_vect_out             : out std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)                           --

    );
  end component;


    component efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5
        port (
        -- GT Interface

                TX_BUF_ERR        : in std_logic;                      -- Overflow/Underflow of TX buffer detected.
                TX_K_ERR          : in std_logic_vector(1 downto 0);   -- Attempt to send bad control byte detected.
                TX_CHAR_IS_K      : out std_logic_vector(1 downto 0);  -- TX_DATA byte is a control character.
                TX_DATA           : out std_logic_vector(15 downto 0); -- 2-byte data bus to the GT.
                V5_TX_RESET       : out std_logic;                     -- Reset TX side of GT logic.

        -- TX_LL Interface

                GEN_SCP           : in std_logic;                      -- SCP generation request from TX_LL.
                GEN_ECP           : in std_logic;                      -- ECP generation request from TX_LL.
                GEN_SUF           : in std_logic;                      -- SUF generation request from TX_LL.
                GEN_PAD           : in std_logic;                      -- PAD generation request from TX_LL.
                FC_NB             : in std_logic_vector(0 to 3);       -- Size code for SUF and SNF messages.
                TX_PE_DATA        : in std_logic_vector(0 to 15);      -- Data from TX_LL to send over lane.
                TX_PE_DATA_V      : in std_logic;                      -- Indicates TX_PE_DATA is Valid.
                GEN_CC            : in std_logic;                      -- CC generation request from TX_LL.

        -- Sideband Signals

               TX_ALIGNED         : in  std_logic;                    -- RX lane partner is aligned

        -- Global Logic Interface

                GEN_A             : in std_logic;                      -- 'A character' generation request from Global Logic.
                GEN_K             : in std_logic_vector(0 to 1);       -- 'K character' generation request from Global Logic.
                GEN_R             : in std_logic_vector(0 to 1);       -- 'R character' generation request from Global Logic.
                GEN_V             : in std_logic_vector(0 to 1);       -- Verification data generation request.
                LANE_UP           : out std_logic;                     -- Lane is ready for bonding and verification.
                HARD_ERR        : out std_logic;                     -- Hard error detected.
                CHANNEL_UP          : in  std_logic;

        -- System Interface

                USER_CLK          : in std_logic;                      -- System clock for all non-GT Aurora Logic.
                RESET_SYMGEN      : in std_logic;                      -- Reset the SYM_GEN module.
                RESET             : in std_logic                       -- Reset the lane.
             );
    end component;



    component efex_aurora_hub2_GT_WRAPPER
       generic(
          SIM_GTRESET_SPEEDUP : string :=   "FALSE";     -- Set to "true" to speed up sim reset
          EXAMPLE_SIMULATION  : integer :=  0      
              );
        port  (
RXFSM_DATA_VALID                        : in    std_logic; 
--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad5_in   : in  std_logic;
   gt_qpllrefclk_quad5_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}

    gt0_txresetdone_out         : out    std_logic;
    gt0_rxresetdone_out         : out    std_logic;
    gt0_rxpmaresetdone_out      : out    std_logic;
    gt0_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt0_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt1_txresetdone_out         : out    std_logic;
    gt1_rxresetdone_out         : out    std_logic;
    gt1_rxpmaresetdone_out      : out    std_logic;
    gt1_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt1_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt2_txresetdone_out         : out    std_logic;
    gt2_rxresetdone_out         : out    std_logic;
    gt2_rxpmaresetdone_out      : out    std_logic;
    gt2_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt2_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt3_txresetdone_out         : out    std_logic;
    gt3_rxresetdone_out         : out    std_logic;
    gt3_rxpmaresetdone_out      : out    std_logic;
    gt3_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt3_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);


                -- DRP I/F
DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN                               : in   std_logic;
DRPDI_IN                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
DRPEN_IN                                : in   std_logic;
DRPRDY_OUT                              : out  std_logic;
DRPWE_IN                                : in   std_logic;
DRPADDR_IN_LANE1                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE1                               : in   std_logic;
DRPDI_IN_LANE1                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE1                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE1                                : in   std_logic;
DRPRDY_OUT_LANE1                              : out  std_logic;
DRPWE_IN_LANE1                                : in   std_logic;
DRPADDR_IN_LANE2                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE2                               : in   std_logic;
DRPDI_IN_LANE2                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE2                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE2                                : in   std_logic;
DRPRDY_OUT_LANE2                              : out  std_logic;
DRPWE_IN_LANE2                                : in   std_logic;
DRPADDR_IN_LANE3                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE3                               : in   std_logic;
DRPDI_IN_LANE3                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE3                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE3                                : in   std_logic;
DRPRDY_OUT_LANE3                              : out  std_logic;
DRPWE_IN_LANE3                                : in   std_logic;

                INIT_CLK_IN        : in    std_logic;
        	PLL_NOT_LOCKED           : in    std_logic;
        	TX_RESETDONE_OUT         : out   std_logic;
        	RX_RESETDONE_OUT         : out   std_logic;

ENCHANSYNC_IN           : in    std_logic;
ENCHANSYNC_IN_LANE1           : in    std_logic;
ENCHANSYNC_IN_LANE2           : in    std_logic;
ENCHANSYNC_IN_LANE3           : in    std_logic;
ENMCOMMAALIGN_IN        : in    std_logic;
ENMCOMMAALIGN_IN_LANE1        : in    std_logic;
ENMCOMMAALIGN_IN_LANE2        : in    std_logic;
ENMCOMMAALIGN_IN_LANE3        : in    std_logic;
ENPCOMMAALIGN_IN        : in    std_logic;
ENPCOMMAALIGN_IN_LANE1        : in    std_logic;
ENPCOMMAALIGN_IN_LANE2        : in    std_logic;
ENPCOMMAALIGN_IN_LANE3        : in    std_logic;

                REFCLK                  : in    std_logic;
                LOOPBACK_IN             : in    std_logic_vector (2 downto 0);
RXPOLARITY_IN           : in    std_logic;
RXPOLARITY_IN_LANE1           : in    std_logic;
RXPOLARITY_IN_LANE2           : in    std_logic;
RXPOLARITY_IN_LANE3           : in    std_logic;
RXRESET_IN              : in    std_logic;
RXRESET_IN_LANE1              : in    std_logic;
RXRESET_IN_LANE2              : in    std_logic;
RXRESET_IN_LANE3              : in    std_logic;
                RXUSRCLK_IN             : in    std_logic;
                RXUSRCLK2_IN            : in    std_logic;
RX1N_IN                 : in    std_logic;
RX1N_IN_LANE1                 : in    std_logic;
RX1N_IN_LANE2                 : in    std_logic;
RX1N_IN_LANE3                 : in    std_logic;
RX1P_IN                 : in    std_logic;
RX1P_IN_LANE1                 : in    std_logic;
RX1P_IN_LANE2                 : in    std_logic;
RX1P_IN_LANE3                 : in    std_logic;
TXCHARISK_IN            : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE1            : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE2            : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE3            : in    std_logic_vector (1 downto 0);
TXDATA_IN               : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE1               : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE2               : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE3               : in    std_logic_vector (15 downto 0);
                GTRESET_IN                                     : in    std_logic;
TXRESET_IN              : in    std_logic;
TXRESET_IN_LANE1              : in    std_logic;
TXRESET_IN_LANE2              : in    std_logic;
TXRESET_IN_LANE3              : in    std_logic;
                TXUSRCLK_IN             : in    std_logic;
                TXUSRCLK2_IN            : in    std_logic;
RXBUFERR_OUT            : out   std_logic;
RXBUFERR_OUT_LANE1            : out   std_logic;
RXBUFERR_OUT_LANE2            : out   std_logic;
RXBUFERR_OUT_LANE3            : out   std_logic;
RXCHARISCOMMA_OUT       : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE1       : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE2       : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE3       : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT           : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE1           : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE2           : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE3           : out   std_logic_vector (1 downto 0);
RXDATA_OUT              : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE1              : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE2              : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE3              : out   std_logic_vector (15 downto 0);
RXDISPERR_OUT           : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE1           : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE2           : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE3           : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT        : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE1        : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE2        : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE3        : out   std_logic_vector (1 downto 0);
RXREALIGN_OUT           : out   std_logic;
RXREALIGN_OUT_LANE1           : out   std_logic;
RXREALIGN_OUT_LANE2           : out   std_logic;
RXREALIGN_OUT_LANE3           : out   std_logic;
CHBONDDONE_OUT          : out   std_logic;
CHBONDDONE_OUT_LANE1          : out   std_logic;
CHBONDDONE_OUT_LANE2          : out   std_logic;
CHBONDDONE_OUT_LANE3          : out   std_logic;
TXBUFERR_OUT            : out   std_logic;
TXBUFERR_OUT_LANE1            : out   std_logic;
TXBUFERR_OUT_LANE2            : out   std_logic;
TXBUFERR_OUT_LANE3            : out   std_logic;
               GTRXRESET_IN            :  in std_logic;

                LINK_RESET_IN          : in std_logic;                     -- Link reset for hotplug scenerio.
PLLLKDET_OUT            : out   std_logic;
PLLLKDET_OUT_LANE1            : out   std_logic;
PLLLKDET_OUT_LANE2            : out   std_logic;
PLLLKDET_OUT_LANE3            : out   std_logic;
TXOUTCLK1_OUT           : out   std_logic;
TXOUTCLK1_OUT_LANE1           : out   std_logic;
TXOUTCLK1_OUT_LANE2           : out   std_logic;
TXOUTCLK1_OUT_LANE3           : out   std_logic;
TX1N_OUT                : out   std_logic;
TX1N_OUT_LANE1                : out   std_logic;
TX1N_OUT_LANE2                : out   std_logic;
TX1N_OUT_LANE3                : out   std_logic;
TX1P_OUT                : out   std_logic;
TX1P_OUT_LANE1                : out   std_logic;
TX1P_OUT_LANE2                : out   std_logic;
TX1P_OUT_LANE3                : out   std_logic;

                POWERDOWN_IN            : in    std_logic

             );
    end component;

    component BUFG
        port (
                O : out STD_ULOGIC;
                I : in STD_ULOGIC
             );
    end component;

    component efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX
        port (

        -- Aurora Lane Interface

LANE_UP            : in std_logic_vector(0 to 3);
HARD_ERR         : in std_logic_vector(0 to 3);
GEN_A              : out std_logic_vector(0 to 3);
GEN_K              : out std_logic_vector(0 to 7);
GEN_R              : out std_logic_vector(0 to 7);
GEN_V              : out std_logic_vector(0 to 7);
RESET_LANES        : out std_logic_vector(0 to 3);

        -- Sideband Signal
                TX_BONDED          : in std_logic;
                TX_VERIFY          : in std_logic;

        -- System Interface

                USER_CLK           : in std_logic;
                RESET              : in std_logic;
                POWER_DOWN         : in std_logic;
                CHANNEL_UP         : out std_logic;
                CHANNEL_HARD_ERR : out std_logic
             );
    end component;


    component efex_aurora_hub2_TX_LL
        port (
        -- LocalLink PDU Interface

                TX_D           : in std_logic_vector(0 to 63);
                TX_REM         : in std_logic_vector(0 to 2);
                TX_SRC_RDY_N   : in std_logic;
                TX_SOF_N       : in std_logic;
                TX_EOF_N       : in std_logic;
                TX_DST_RDY_N   : out std_logic;

        -- UFC Interface

                UFC_TX_REQ_N   : in std_logic;
                UFC_TX_MS      : in std_logic_vector(0 to 3);
                UFC_TX_ACK_N   : out std_logic;
        -- Clock Compensation Interface
                WARN_CC        : in std_logic;
                DO_CC          : in std_logic;
        -- Global Logic Interface

                CHANNEL_UP     : in std_logic;

        -- Aurora Lane Interface

                GEN_SCP        : out std_logic;
                GEN_ECP        : out std_logic;
                GEN_SUF        : out std_logic;
                FC_NB          : out std_logic_vector(0 to 3);
                TX_PE_DATA_V   : out std_logic_vector(0 to 3);
                GEN_PAD        : out std_logic_vector(0 to 3);
                TX_PE_DATA     : out std_logic_vector(0 to 63);
                GEN_CC         : out std_logic_vector(0 to 3);

        -- System Interface

                USER_CLK       : in std_logic
             );
    end component;


component efex_aurora_hub2_STANDARD_CC_MODULE
    generic
    (
        CC_FREQ_FACTOR : integer := 24
    );
    port (
    -- Clock Compensation Control Interface
            WARN_CC        : out std_logic;
            DO_CC          : out std_logic;
    -- System Interface
            PLL_NOT_LOCKED : in std_logic;
            USER_CLK       : in std_logic;
            RESET          : in std_logic
         );
    end component;

--*********************************Signal Declarations**********************************
signal TX1N_OUT_unused                 : std_logic_vector(0 to 3);
signal TX1P_OUT_unused                 : std_logic_vector(0 to 3);
signal RX1N_IN_unused                  : std_logic_vector(0 to 3);
signal RX1P_IN_unused                  : std_logic_vector(0 to 3);
signal rx_char_is_comma_i_unused        : std_logic_vector(7 downto 0);    
signal rx_char_is_k_i_unused            : std_logic_vector(7 downto 0);    
signal rx_data_i_unused                : std_logic_vector(63 downto 0);    
signal rx_disp_err_i_unused            : std_logic_vector(7 downto 0);    
signal rx_not_in_table_i_unused        : std_logic_vector(7 downto 0);    
signal rx_realign_i_unused             : std_logic_vector(3 downto 0);    
signal ch_bond_done_i_unused           : std_logic_vector(3 downto 0);


signal ch_bond_done_i                   :   std_logic_vector(3 downto 0);
signal ch_bond_done_r1                  :   std_logic_vector(3 downto 0);
signal ch_bond_done_r2                  :   std_logic_vector(3 downto 0);
    signal en_chan_sync_i                   :   std_logic;
signal ena_comma_align_i                :   std_logic_vector(3 downto 0);
    signal fc_nb_i                          :   std_logic_vector(0 to 3);
signal gen_a_i                          :   std_logic_vector(0 to 3);
signal gen_cc_i                         :   std_logic_vector(0 to 3);
    signal gen_ecp_i                        :   std_logic;
signal gen_k_i                          :   std_logic_vector(0 to 7);
signal gen_pad_i                        :   std_logic_vector(0 to 3);
signal gen_r_i                          :   std_logic_vector(0 to 7);
    signal gen_scp_i                        :   std_logic;
    signal gen_suf_i                        :   std_logic;
signal gen_v_i                          :   std_logic_vector(0 to 7);
signal gtp_rx_reset_i                   :   std_logic_vector(3 downto 0);
signal gtp_tx_reset_i                   :   std_logic_vector(3 downto 0);
signal open_rx_rec1_clk_i               :   std_logic_vector(3 downto 0);
signal open_rx_rec2_clk_i               :   std_logic_vector(3 downto 0);
signal tx_out_clk_i                     :   std_logic_vector(0 to 3);
signal raw_tx_out_clk_i             :   std_logic_vector(0 to 3);
signal rx_buf_err_i                     :   std_logic_vector(3 downto 0);
signal rx_char_is_comma_i               :   std_logic_vector(7 downto 0);
signal rx_char_is_k_i                   :   std_logic_vector(7 downto 0);
signal rx_clk_cor_cnt_i                 :   std_logic_vector(11 downto 0);
signal rx_data_i                        :   std_logic_vector(63 downto 0);
signal rx_disp_err_i                    :   std_logic_vector(7 downto 0);
signal rx_not_in_table_i                :   std_logic_vector(7 downto 0);
signal rx_polarity_i                    :   std_logic_vector(3 downto 0);
signal rx_realign_i                     :   std_logic_vector(3 downto 0);
signal rxmclk_out_not_used_i            :   std_logic_vector(0 to 3);
signal rxpcshclkout_not_used_i          :   std_logic_vector(0 to 3);
    signal tied_to_ground_i                 :   std_logic;
    signal tied_to_ground_vec_i             :   std_logic_vector(47 downto 0);
    signal tied_to_vcc_i                    :   std_logic;
signal tx_buf_err_i                     :   std_logic_vector(3 downto 0);
    signal tx_channel_up_i                  :   std_logic;
signal tx_char_is_k_i                   :   std_logic_vector(7 downto 0);
signal tx_data_i                        :   std_logic_vector(63 downto 0);
signal tx_hard_err_i                  :   std_logic_vector(0 to 3);
signal tx_lane_up_i                     :   std_logic_vector(0 to 3);
signal lane_up_reduce_i    : std_logic;
signal rst_cc_module_i     : std_logic;
signal tx_lock_i                        :   std_logic_vector(0 to 3);
signal tx_pe_data_i                     :   std_logic_vector(0 to 63);
signal tx_pe_data_v_i                   :   std_logic_vector(0 to 3);
signal tx_reset_lanes_i                 :   std_logic_vector(0 to 3);
    signal tx_system_reset_c                :   std_logic;

    signal simplex_timer_r                  :   std_logic_vector(C_SIMPLEX_TIMER-1 downto 0);
    signal tx_reset_simplex_r               :   std_logic;
    signal tx_aligned_simplex_r             :   std_logic;
    signal tx_verify_simplex_r              :   std_logic;
    signal TX_HARD_ERR_W                  :   std_logic;
    signal tx_bonded_simplex_w              :   std_logic;
    signal tx_bonded1_simplex_r             :   std_logic;

    signal ufc_tx_ms_i                      :   std_logic_vector(0 to 3);
signal ch_bond_load_pulse_i             : std_logic_vector(0 to 3);
signal ch_bond_done_dly_i               : std_logic_vector(0 to 3);


signal tied_to_gnd_vec_i        : std_logic_vector(0 to 63);
    -- TX AXI PDU I/F signals
signal tx_data                  : std_logic_vector(0 to 63);
signal tx_rem                   : std_logic_vector(0 to 2);
signal tx_src_rdy               : std_logic;
signal tx_sof                   : std_logic;
signal tx_eof                   : std_logic;
signal tx_dst_rdy               : std_logic;


    -- TX AXI UFC I/F signals
signal tx_ufc_data               : std_logic_vector(0 to 3);
signal tx_ufc_src_rdy            : std_logic;
signal tx_ufc_dst_rdy            : std_logic;



signal   gtrxreset_i              : std_logic;
signal   system_reset_i           : std_logic;
signal   tx_lock_comb_i           : std_logic;
signal   tx_resetdone_i           : std_logic;
signal   reset_sync_user_clk      : std_logic;
signal   gt_reset_sync_init_clk   : std_logic;

signal  rxfsm_data_valid_r       : std_logic;
signal DO_CC_I            : std_logic;
signal WARN_CC            : std_logic;
begin
--*********************************Main Body of Code**********************************

    -- Tie off constant signals

    tied_to_ground_vec_i        <=  (others => '0');
    tied_to_ground_i            <=  '0';
    tied_to_vcc_i               <=  '1';


   TX_HARD_ERR <= TX_HARD_ERR_W;

   process (user_clk)
   begin

       if (user_clk 'event and user_clk = '1') then

          if (system_reset_i='1' or TX_HARD_ERR_W='1') then
              simplex_timer_r  <=  (others => '0');

          elsif(tx_verify_simplex_r='1') then

              simplex_timer_r  <=  simplex_timer_r;

          else

            simplex_timer_r  <=  simplex_timer_r + 1;
          end if;
       end if;
  end process;

   process (user_clk)
   begin
       if (user_clk 'event and user_clk = '1') then
          if (simplex_timer_r="0000000000000000" or system_reset_i='1' or
              TX_HARD_ERR_W='1') then
              tx_reset_simplex_r  <=  '0';

          elsif(simplex_timer_r="0000000000000001") then

              tx_reset_simplex_r  <=  '1';

          elsif(simplex_timer_r="0000000000000110") then

              tx_reset_simplex_r  <=  '0';

          end if;
       end if;
   end process;

   process (user_clk)
   begin
       if (user_clk 'event and user_clk = '1') then
          if (tx_system_reset_c='1' or TX_HARD_ERR_W='1') then

              tx_aligned_simplex_r  <=  '0';

          elsif(simplex_timer_r=C_ALIGNED_TIMER) then 

              tx_aligned_simplex_r  <=  '1';

          end if;
       end if;
   end process;

   process (user_clk)
   begin
       if (user_clk 'event and user_clk = '1') then
          if (tx_system_reset_c='1' or TX_HARD_ERR_W='1') then

              tx_verify_simplex_r  <=  '0';

          elsif(simplex_timer_r=C_VERIFY_TIMER) then  

              tx_verify_simplex_r  <=  '1';

          end if;
       end if;
   end process;


   process (user_clk)
   begin
       if (user_clk 'event and user_clk = '1') then

          if (tx_system_reset_c='1' or TX_HARD_ERR_W='1') then

              tx_bonded1_simplex_r  <=  '0';

          elsif(simplex_timer_r=C_BONDED_TIMER) then  

              tx_bonded1_simplex_r  <=  '1';

          end if;
       end if;
   end process;

   tx_bonded_simplex_w <= tx_bonded1_simplex_r xor tx_verify_simplex_r;

    -- Connect global external signals to their internal counterparts

    tx_lock              <=  tx_lock_comb_i;
    sys_reset_out        <=  system_reset_i;



    TX_CHANNEL_UP      <= tx_channel_up_i;
    tx_resetdone_out     <=  tx_resetdone_i;

    tx_system_reset_c  <= system_reset_i or tx_reset_simplex_r;


    --Connect the TXOUTCLK of lane 0 to TX_OUT_CLK
TX_OUT_CLK  <= tx_out_clk_i(2);
   
    -- Connect TX_LOCK to the tx_lock_i from lane 0
    tx_lock_comb_i    <=   AND_REDUCE(tx_lock_i);

 reset_sync_user_clk_cdc_sync : efex_aurora_hub2_cdc_sync
   generic map
     (
       c_cdc_type        => 1,   
       c_flop_input      => 0,  
       c_reset_state     => 0,  
       c_single_bit      => 1,  
       c_vector_width    => 2,  
       c_mtbf_stages     => 3 
     )
  port map
     (
       prmry_aclk        => '0'                ,
       prmry_resetn      => '1'                ,
       prmry_in          => TX_SYSTEM_RESET    ,
       prmry_vect_in     => "00"               ,
       scndry_aclk       => user_clk           ,
       scndry_resetn     => '1'                ,
       prmry_ack         => open               ,
       scndry_out        => reset_sync_user_clk,
       scndry_vect_out   => open           
     );

 gt_reset_cdc_sync : efex_aurora_hub2_cdc_sync
   generic map
     (
       c_cdc_type        => 1,   
       c_flop_input      => 0,  
       c_reset_state     => 0,  
       c_single_bit      => 1,  
       c_vector_width    => 2,  
       c_mtbf_stages     => 3 
     )
  port map
     (
       prmry_aclk        => '0'                   ,
       prmry_resetn      => '1'                   ,
       prmry_in          => GT_RESET              ,
       prmry_vect_in     => "00"                  ,
       scndry_aclk       => init_clk_in           ,
       scndry_resetn     => '1'                   ,
       prmry_ack         => open                  ,
       scndry_out        => gt_reset_sync_init_clk,
       scndry_vect_out   => open           
     );

    -- RESET_LOGIC instance
    core_reset_logic_i  :  efex_aurora_hub2_RESET_LOGIC 
    port map
    (
        RESET                    =>   reset_sync_user_clk,
        USER_CLK                 =>   user_clk,
        INIT_CLK_IN              =>   init_clk_in,
        TX_LOCK_IN               =>   tx_lock_comb_i,
        PLL_NOT_LOCKED           =>   pll_not_locked,
     	  TX_RESETDONE_IN          =>   tx_resetdone_i,
        LINK_RESET_IN            =>   '0',
        SYSTEM_RESET             =>   system_reset_i
    );



rx_polarity_i (0)     <= '0';
gtp_rx_reset_i (0)    <= '0';
ena_comma_align_i (0) <= '0';

    -- Instantiate TX Lane 0 --

TX_LANE_UP (0) <= tx_lane_up_i (0);

    tx_aurora_lane_simplex_v5_0_i : efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5
        port map (
        -- GT Interface

TX_BUF_ERR   => tx_buf_err_i (0),
                    TX_K_ERR     => tied_to_ground_vec_i(1 downto 0),
                    TX_CHAR_IS_K => tx_char_is_k_i(1 downto 0),
                    TX_DATA      => tx_data_i(15 downto 0),
V5_TX_RESET  => gtp_tx_reset_i (0),

        -- TX_LL Interface

                    GEN_SCP      => gen_scp_i,
                    GEN_SUF      => gen_suf_i,
                    FC_NB        => fc_nb_i,
                    GEN_ECP      => tied_to_ground_vec_i(0),
GEN_PAD      => gen_pad_i (0),
                    TX_PE_DATA   => tx_pe_data_i(0 to 15),
TX_PE_DATA_V => tx_pe_data_v_i (0),
GEN_CC       => gen_cc_i (0),

            -- Sideband Signals

                    TX_ALIGNED   => tx_aligned_simplex_r,
            -- Global Logic Interface

GEN_A        => gen_a_i (0),
                    GEN_K        => gen_k_i(0 to 1),
                    GEN_R        => gen_r_i(0 to 1),
                    GEN_V        => gen_v_i(0 to 1),
LANE_UP      => tx_lane_up_i (0),
HARD_ERR   => tx_hard_err_i (0),
                    CHANNEL_UP        => tx_channel_up_i,

            -- System Interface

                    USER_CLK     => user_clk,
                    RESET_SYMGEN => tx_system_reset_c,
RESET        => tx_reset_lanes_i (0)
                 );



rx_polarity_i (1)     <= '0';
gtp_rx_reset_i (1)    <= '0';
ena_comma_align_i (1) <= '0';

    -- Instantiate TX Lane 1 --

TX_LANE_UP (1) <= tx_lane_up_i (1);

    tx_aurora_lane_simplex_v5_1_i : efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5
        port map (
        -- GT Interface

TX_BUF_ERR   => tx_buf_err_i (1),
                    TX_K_ERR     => tied_to_ground_vec_i(1 downto 0),
                    TX_CHAR_IS_K => tx_char_is_k_i(3 downto 2),
                    TX_DATA      => tx_data_i(31 downto 16),
V5_TX_RESET  => gtp_tx_reset_i (1),

        -- TX_LL Interface

                    GEN_SCP      => tied_to_ground_vec_i(0),
                    GEN_SUF      => tied_to_ground_vec_i(0),
                    FC_NB        => tied_to_ground_vec_i(3 downto 0),
                    GEN_ECP      => tied_to_ground_vec_i(0),
GEN_PAD      => gen_pad_i (1),
                    TX_PE_DATA   => tx_pe_data_i(16 to 31),
TX_PE_DATA_V => tx_pe_data_v_i (1),
GEN_CC       => gen_cc_i (1),

            -- Sideband Signals

                    TX_ALIGNED   => tx_aligned_simplex_r,
            -- Global Logic Interface

GEN_A        => gen_a_i (1),
                    GEN_K        => gen_k_i(2 to 3),
                    GEN_R        => gen_r_i(2 to 3),
                    GEN_V        => gen_v_i(2 to 3),
LANE_UP      => tx_lane_up_i (1),
HARD_ERR   => tx_hard_err_i (1),
                    CHANNEL_UP        => tx_channel_up_i,

            -- System Interface

                    USER_CLK     => user_clk,
                    RESET_SYMGEN => tx_system_reset_c,
RESET        => tx_reset_lanes_i (1)
                 );



rx_polarity_i (2)     <= '0';
gtp_rx_reset_i (2)    <= '0';
ena_comma_align_i (2) <= '0';

    -- Instantiate TX Lane 2 --

TX_LANE_UP (2) <= tx_lane_up_i (2);

    tx_aurora_lane_simplex_v5_2_i : efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5
        port map (
        -- GT Interface

TX_BUF_ERR   => tx_buf_err_i (2),
                    TX_K_ERR     => tied_to_ground_vec_i(1 downto 0),
                    TX_CHAR_IS_K => tx_char_is_k_i(5 downto 4),
                    TX_DATA      => tx_data_i(47 downto 32),
V5_TX_RESET  => gtp_tx_reset_i (2),

        -- TX_LL Interface

                    GEN_SCP      => tied_to_ground_vec_i(0),
                    GEN_SUF      => tied_to_ground_vec_i(0),
                    FC_NB        => tied_to_ground_vec_i(3 downto 0),
                    GEN_ECP      => tied_to_ground_vec_i(0),
GEN_PAD      => gen_pad_i (2),
                    TX_PE_DATA   => tx_pe_data_i(32 to 47),
TX_PE_DATA_V => tx_pe_data_v_i (2),
GEN_CC       => gen_cc_i (2),

            -- Sideband Signals

                    TX_ALIGNED   => tx_aligned_simplex_r,
            -- Global Logic Interface

GEN_A        => gen_a_i (2),
                    GEN_K        => gen_k_i(4 to 5),
                    GEN_R        => gen_r_i(4 to 5),
                    GEN_V        => gen_v_i(4 to 5),
LANE_UP      => tx_lane_up_i (2),
HARD_ERR   => tx_hard_err_i (2),
                    CHANNEL_UP        => tx_channel_up_i,

            -- System Interface

                    USER_CLK     => user_clk,
                    RESET_SYMGEN => tx_system_reset_c,
RESET        => tx_reset_lanes_i (2)
                 );



rx_polarity_i (3)     <= '0';
gtp_rx_reset_i (3)    <= '0';
ena_comma_align_i (3) <= '0';

    -- Instantiate TX Lane 3 --

TX_LANE_UP (3) <= tx_lane_up_i (3);

    tx_aurora_lane_simplex_v5_3_i : efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5
        port map (
        -- GT Interface

TX_BUF_ERR   => tx_buf_err_i (3),
                    TX_K_ERR     => tied_to_ground_vec_i(1 downto 0),
                    TX_CHAR_IS_K => tx_char_is_k_i(7 downto 6),
                    TX_DATA      => tx_data_i(63 downto 48),
V5_TX_RESET  => gtp_tx_reset_i (3),

        -- TX_LL Interface

                    GEN_SCP      => tied_to_ground_vec_i(0),
                    GEN_SUF      => tied_to_ground_vec_i(0),
                    FC_NB        => tied_to_ground_vec_i(3 downto 0),
                    GEN_ECP      => gen_ecp_i,
GEN_PAD      => gen_pad_i (3),
                    TX_PE_DATA   => tx_pe_data_i(48 to 63),
TX_PE_DATA_V => tx_pe_data_v_i (3),
GEN_CC       => gen_cc_i (3),

            -- Sideband Signals

                    TX_ALIGNED   => tx_aligned_simplex_r,
            -- Global Logic Interface

GEN_A        => gen_a_i (3),
                    GEN_K        => gen_k_i(6 to 7),
                    GEN_R        => gen_r_i(6 to 7),
                    GEN_V        => gen_v_i(6 to 7),
LANE_UP      => tx_lane_up_i (3),
HARD_ERR   => tx_hard_err_i (3),
                    CHANNEL_UP        => tx_channel_up_i,

            -- System Interface

                    USER_CLK     => user_clk,
                    RESET_SYMGEN => tx_system_reset_c,
RESET        => tx_reset_lanes_i (3)
                 );

    gt_wrapper_i : efex_aurora_hub2_GT_WRAPPER
        generic map(
                     SIM_GTRESET_SPEEDUP  => SIM_GTRESET_SPEEDUP,
                     EXAMPLE_SIMULATION          => EXAMPLE_SIMULATION
                   )
        port map   (
--____________________________COMMON PORTS INST_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in        =>  gt0_qplllock_in,
      gt0_qpllrefclklost_in  =>  gt0_qpllrefclklost_in,
      gt0_qpllreset_out      =>  gt0_qpllreset_out,
        gt_qpllclk_quad5_in     => gt_qpllclk_quad5_in    ,
        gt_qpllrefclk_quad5_in  => gt_qpllrefclk_quad5_in ,
--____________________________COMMON PORTS INST_______________________________}

        gt0_txresetdone_out        => open,
        gt0_rxresetdone_out        => open,
        gt0_rxpmaresetdone_out     => open,
        gt0_txbufstatus_out             => open,
        gt0_rxbufstatus_out             => open,
        gt1_txresetdone_out        => open,
        gt1_rxresetdone_out        => open,
        gt1_rxpmaresetdone_out     => open,
        gt1_txbufstatus_out             => open,
        gt1_rxbufstatus_out             => open,
        gt2_txresetdone_out        => open,
        gt2_rxresetdone_out        => open,
        gt2_rxpmaresetdone_out     => open,
        gt2_txbufstatus_out             => open,
        gt2_rxbufstatus_out             => open,
        gt3_txresetdone_out        => open,
        gt3_rxresetdone_out        => open,
        gt3_rxpmaresetdone_out     => open,
        gt3_txbufstatus_out             => open,
        gt3_rxbufstatus_out             => open,


        -- DRP I/F
DRPCLK_IN                      => drpclk_in,
DRPADDR_IN                     => DRPADDR_IN,
DRPDI_IN                       => DRPDI_IN,
DRPDO_OUT                      => DRPDO_OUT,
DRPEN_IN                       => DRPEN_IN,
DRPRDY_OUT                     => DRPRDY_OUT,
DRPWE_IN                       => DRPWE_IN,
DRPCLK_IN_LANE1                      => drpclk_in,
DRPADDR_IN_LANE1                     => DRPADDR_IN_LANE1,
DRPDI_IN_LANE1                       => DRPDI_IN_LANE1,
DRPDO_OUT_LANE1                      => DRPDO_OUT_LANE1,
DRPEN_IN_LANE1                       => DRPEN_IN_LANE1,
DRPRDY_OUT_LANE1                     => DRPRDY_OUT_LANE1,
DRPWE_IN_LANE1                       => DRPWE_IN_LANE1,
DRPCLK_IN_LANE2                      => drpclk_in,
DRPADDR_IN_LANE2                     => DRPADDR_IN_LANE2,
DRPDI_IN_LANE2                       => DRPDI_IN_LANE2,
DRPDO_OUT_LANE2                      => DRPDO_OUT_LANE2,
DRPEN_IN_LANE2                       => DRPEN_IN_LANE2,
DRPRDY_OUT_LANE2                     => DRPRDY_OUT_LANE2,
DRPWE_IN_LANE2                       => DRPWE_IN_LANE2,
DRPCLK_IN_LANE3                      => drpclk_in,
DRPADDR_IN_LANE3                     => DRPADDR_IN_LANE3,
DRPDI_IN_LANE3                       => DRPDI_IN_LANE3,
DRPDO_OUT_LANE3                      => DRPDO_OUT_LANE3,
DRPEN_IN_LANE3                       => DRPEN_IN_LANE3,
DRPRDY_OUT_LANE3                     => DRPRDY_OUT_LANE3,
DRPWE_IN_LANE3                       => DRPWE_IN_LANE3,

        INIT_CLK_IN                => init_clk_in,   
	PLL_NOT_LOCKED                   => PLL_NOT_LOCKED,
RXFSM_DATA_VALID                              => '1',
	TX_RESETDONE_OUT                 => tx_resetdone_i,
	RX_RESETDONE_OUT                 => OPEN,   
        -- Aurora Lane Interface
RXPOLARITY_IN           => rx_polarity_i (0),
RXPOLARITY_IN_LANE1           => rx_polarity_i (1),
RXPOLARITY_IN_LANE2           => rx_polarity_i (2),
RXPOLARITY_IN_LANE3           => rx_polarity_i (3),
RXRESET_IN              => gtp_rx_reset_i (0),
RXRESET_IN_LANE1              => gtp_rx_reset_i (1),
RXRESET_IN_LANE2              => gtp_rx_reset_i (2),
RXRESET_IN_LANE3              => gtp_rx_reset_i (3),
TXCHARISK_IN            => tx_char_is_k_i(1 downto 0),
TXCHARISK_IN_LANE1            => tx_char_is_k_i(3 downto 2),
TXCHARISK_IN_LANE2            => tx_char_is_k_i(5 downto 4),
TXCHARISK_IN_LANE3            => tx_char_is_k_i(7 downto 6),
TXDATA_IN               => tx_data_i(15 downto 0),
TXDATA_IN_LANE1               => tx_data_i(31 downto 16),
TXDATA_IN_LANE2               => tx_data_i(47 downto 32),
TXDATA_IN_LANE3               => tx_data_i(63 downto 48),
TXRESET_IN              => gtp_tx_reset_i (0),
TXRESET_IN_LANE1              => gtp_tx_reset_i (1),
TXRESET_IN_LANE2              => gtp_tx_reset_i (2),
TXRESET_IN_LANE3              => gtp_tx_reset_i (3),
RXDATA_OUT              => rx_data_i(15 downto 0),
RXDATA_OUT_LANE1              => rx_data_i(31 downto 16),
RXDATA_OUT_LANE2              => rx_data_i(47 downto 32),
RXDATA_OUT_LANE3              => rx_data_i(63 downto 48),
RXNOTINTABLE_OUT        => rx_not_in_table_i(1 downto 0),
RXNOTINTABLE_OUT_LANE1        => rx_not_in_table_i(3 downto 2),
RXNOTINTABLE_OUT_LANE2        => rx_not_in_table_i(5 downto 4),
RXNOTINTABLE_OUT_LANE3        => rx_not_in_table_i(7 downto 6),
RXDISPERR_OUT           => rx_disp_err_i(1 downto 0),
RXDISPERR_OUT_LANE1           => rx_disp_err_i(3 downto 2),
RXDISPERR_OUT_LANE2           => rx_disp_err_i(5 downto 4),
RXDISPERR_OUT_LANE3           => rx_disp_err_i(7 downto 6),
RXCHARISK_OUT           => rx_char_is_k_i(1 downto 0),
RXCHARISK_OUT_LANE1           => rx_char_is_k_i(3 downto 2),
RXCHARISK_OUT_LANE2           => rx_char_is_k_i(5 downto 4),
RXCHARISK_OUT_LANE3           => rx_char_is_k_i(7 downto 6),
RXCHARISCOMMA_OUT       => rx_char_is_comma_i(1 downto 0),
RXCHARISCOMMA_OUT_LANE1       => rx_char_is_comma_i(3 downto 2),
RXCHARISCOMMA_OUT_LANE2       => rx_char_is_comma_i(5 downto 4),
RXCHARISCOMMA_OUT_LANE3       => rx_char_is_comma_i(7 downto 6),
TXBUFERR_OUT            => tx_buf_err_i (0),
TXBUFERR_OUT_LANE1            => tx_buf_err_i (1),
TXBUFERR_OUT_LANE2            => tx_buf_err_i (2),
TXBUFERR_OUT_LANE3            => tx_buf_err_i (3),
RXBUFERR_OUT            => rx_buf_err_i (0),
RXBUFERR_OUT_LANE1            => rx_buf_err_i (1),
RXBUFERR_OUT_LANE2            => rx_buf_err_i (2),
RXBUFERR_OUT_LANE3            => rx_buf_err_i (3),
RXREALIGN_OUT           => rx_realign_i (0),
RXREALIGN_OUT_LANE1           => rx_realign_i (1),
RXREALIGN_OUT_LANE2           => rx_realign_i (2),
RXREALIGN_OUT_LANE3           => rx_realign_i (3),
        -- Reset due to channel initialization watchdog timer expiry  
                    GTRXRESET_IN                =>  '0',

        -- reset for hot plug
                    LINK_RESET_IN      => '0',
        --  Phase Align Interface

ENMCOMMAALIGN_IN        => ena_comma_align_i (0),
ENMCOMMAALIGN_IN_LANE1        => ena_comma_align_i (1),
ENMCOMMAALIGN_IN_LANE2        => ena_comma_align_i (2),
ENMCOMMAALIGN_IN_LANE3        => ena_comma_align_i (3),
ENPCOMMAALIGN_IN        => ena_comma_align_i (0),
ENPCOMMAALIGN_IN_LANE1        => ena_comma_align_i (1),
ENPCOMMAALIGN_IN_LANE2        => ena_comma_align_i (2),
ENPCOMMAALIGN_IN_LANE3        => ena_comma_align_i (3),
        -- Global Logic Interface

ENCHANSYNC_IN           => tied_to_vcc_i,
ENCHANSYNC_IN_LANE1           => en_chan_sync_i,
ENCHANSYNC_IN_LANE2           => tied_to_vcc_i,
ENCHANSYNC_IN_LANE3           => tied_to_vcc_i,
CHBONDDONE_OUT          => ch_bond_done_i (0),
CHBONDDONE_OUT_LANE1          => ch_bond_done_i (1),
CHBONDDONE_OUT_LANE2          => ch_bond_done_i (2),
CHBONDDONE_OUT_LANE3          => ch_bond_done_i (3),

        -- Serial IO
RX1N_IN       => tied_to_ground_i,
RX1N_IN_LANE1       => tied_to_ground_i,
RX1N_IN_LANE2       => tied_to_ground_i,
RX1N_IN_LANE3       => tied_to_ground_i,
RX1P_IN       => tied_to_ground_i,
RX1P_IN_LANE1       => tied_to_ground_i,
RX1P_IN_LANE2       => tied_to_ground_i,
RX1P_IN_LANE3       => tied_to_ground_i,
TX1N_OUT      => TXN (0),
TX1N_OUT_LANE1      => TXN (1),
TX1N_OUT_LANE2      => TXN (2),
TX1N_OUT_LANE3      => TXN (3),
TX1P_OUT      => TXP (0),
TX1P_OUT_LANE1      => TXP (1),
TX1P_OUT_LANE2      => TXP (2),
TX1P_OUT_LANE3      => TXP (3),

        -- Reference Clocks and User Clock

                    RXUSRCLK_IN             => sync_clk,
                    RXUSRCLK2_IN            => user_clk,
                    TXUSRCLK_IN             => sync_clk,
                    TXUSRCLK2_IN            => user_clk,
                    REFCLK                  =>  gt_refclk1,

TXOUTCLK1_OUT           => tx_out_clk_i (0),
TXOUTCLK1_OUT_LANE1           => tx_out_clk_i (1),
TXOUTCLK1_OUT_LANE2           => tx_out_clk_i (2),
TXOUTCLK1_OUT_LANE3           => tx_out_clk_i (3),
PLLLKDET_OUT            => tx_lock_i (0),       
PLLLKDET_OUT_LANE1            => tx_lock_i (1),       
PLLLKDET_OUT_LANE2            => tx_lock_i (2),       
PLLLKDET_OUT_LANE3            => tx_lock_i (3),       

        -- System Interface

                    GTRESET_IN                                     => gt_reset_sync_init_clk,
                    LOOPBACK_IN                                         => LOOPBACK,

                    POWERDOWN_IN                                       => POWER_DOWN
                 );


    -- Tie off RX Global Logic signals to the GT

    en_chan_sync_i <= '0';


    -- Instantiate TX Global Logic --

    tx_global_logic_simplex_i : efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX
        port map (

        -- Aurora Lane Interface

                    LANE_UP             =>  tx_lane_up_i,
                    HARD_ERR          =>  tx_hard_err_i,
                    GEN_A               =>  gen_a_i,
                    GEN_K               =>  gen_k_i,
                    GEN_R               =>  gen_r_i,
                    GEN_V               =>  gen_v_i,
                    RESET_LANES         =>  tx_reset_lanes_i,

        -- Sideband Signal
                    TX_BONDED           =>  tx_bonded_simplex_w,
                    TX_VERIFY           =>  tx_verify_simplex_r,

        -- System Interface

                    USER_CLK            =>  user_clk,
                    RESET               =>  tx_system_reset_c,
                    POWER_DOWN          =>  POWER_DOWN,
                    CHANNEL_UP          =>  tx_channel_up_i,
                    CHANNEL_HARD_ERR  =>  TX_HARD_ERR_W
                 );



    --_____________________________ TX AXI SHIM _______________________________
    axi_to_ll_pdu_i : efex_aurora_hub2_AXI_TO_LL
    generic map
    (
       DATA_WIDTH           => 64,
       STRB_WIDTH           => 8,
       REM_WIDTH            => 3,
       USE_4_NFC            => 0,
       USE_UFC_REM          => 0
    )

    port map
    (
      AXI4_S_IP_TX_TVALID   => S_AXI_TX_TVALID,
      AXI4_S_IP_TX_TDATA    => S_AXI_TX_TDATA,
      AXI4_S_IP_TX_TKEEP    => S_AXI_TX_TKEEP,
      AXI4_S_IP_TX_TLAST    => S_AXI_TX_TLAST,
      AXI4_S_OP_TX_TREADY   => S_AXI_TX_TREADY,

      LL_OP_DATA            => tx_data,
      LL_OP_SOF_N           => tx_sof,
      LL_OP_EOF_N           => tx_eof,
      LL_OP_REM             => tx_rem,
      LL_OP_SRC_RDY_N       => tx_src_rdy,
      LL_IP_DST_RDY_N       => tx_dst_rdy,

      -- System Interface
      USER_CLK              => user_clk,
      RESET                 => tx_system_reset_c, 
      CHANNEL_UP            => tx_channel_up_i
    );


    axi_to_ll_ufc_i : efex_aurora_hub2_AXI_TO_LL
    generic map
    (
       DATA_WIDTH           => 4,
       STRB_WIDTH           => 8,
       REM_WIDTH            => 3,
       USE_4_NFC            => 2,
       USE_UFC_REM          => 1
    )

    port map
    (
     AXI4_S_IP_TX_TVALID    => S_AXI_UFC_TX_REQ,
     AXI4_S_OP_TX_TREADY    => S_AXI_UFC_TX_ACK,
     AXI4_S_IP_TX_TDATA     => ufc_tx_ms_i,
AXI4_S_IP_TX_TKEEP     => "00000000",
     AXI4_S_IP_TX_TLAST     => tied_to_ground_i,

     LL_OP_DATA             => tx_ufc_data,
     LL_OP_SOF_N            => OPEN,
     LL_OP_EOF_N            => OPEN,
     LL_OP_REM              => OPEN,
     LL_OP_SRC_RDY_N        => tx_ufc_src_rdy,
     LL_IP_DST_RDY_N        => tx_ufc_dst_rdy,

     -- System Interface
     USER_CLK               => user_clk,
     RESET                  => tx_system_reset_c, 
     CHANNEL_UP             => tx_channel_up_i
    );



    process (user_clk)
    begin
      if (user_clk 'event and user_clk = '1') then
         lane_up_reduce_i    <=  AND_REDUCE(tx_lane_up_i);
       end if;
    end process;

    rst_cc_module_i  <= system_reset_i; 
    standard_cc_module_i : efex_aurora_hub2_STANDARD_CC_MODULE
        generic map
        (
            CC_FREQ_FACTOR => CC_FREQ_FACTOR
        )
        port map (
        -- Clock Compensation Control Interface
                    WARN_CC        => WARN_CC,
                    DO_CC          => DO_CC_I,
        -- System Interface
                    PLL_NOT_LOCKED => pll_not_locked,
                    USER_CLK       => user_clk,
                    RESET          => rst_cc_module_i
                 );

    -- Instantiate TX_LL --

    ufc_tx_ms_i <= S_AXI_UFC_TX_MS & '1';

    tx_ll_i : efex_aurora_hub2_TX_LL
        port map (

        -- AXI PDU Interface
                    TX_D                    => tx_data,
                    TX_REM                  => tx_rem,
                    TX_SRC_RDY_N            => tx_src_rdy,
                    TX_SOF_N                => tx_sof,
                    TX_EOF_N                => tx_eof,
                    TX_DST_RDY_N            => tx_dst_rdy,
        -- UFC Interface

                    UFC_TX_REQ_N    => tx_ufc_src_rdy,
                    UFC_TX_MS       => tx_ufc_data,
                    UFC_TX_ACK_N    => tx_ufc_dst_rdy,
        -- Clock Compenstaion Interface
                    WARN_CC                 => WARN_CC,
                    DO_CC                   => DO_CC_I,

        -- Global Logic Interface

                    CHANNEL_UP    => tx_channel_up_i,

        -- Aurora Lane Interface

                    GEN_SCP       => gen_scp_i,
                    GEN_ECP       => gen_ecp_i,
                    GEN_SUF       => gen_suf_i,
                    FC_NB         => fc_nb_i,
                    TX_PE_DATA_V  => tx_pe_data_v_i,
                    GEN_PAD       => gen_pad_i,
                    TX_PE_DATA    => tx_pe_data_i,
                    GEN_CC        => gen_cc_i,

        -- System Interface

                    USER_CLK      => user_clk

                 );




end MAPPED;
